CN104617140B - 凹入式沟道存取晶体管器件及其制作方法 - Google Patents

凹入式沟道存取晶体管器件及其制作方法 Download PDF

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CN104617140B
CN104617140B CN201410026351.XA CN201410026351A CN104617140B CN 104617140 B CN104617140 B CN 104617140B CN 201410026351 A CN201410026351 A CN 201410026351A CN 104617140 B CN104617140 B CN 104617140B
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吴铁将
廖伟明
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Abstract

本发明公开了一种凹入式沟道存取晶体管器件及其制造方法，所述晶体管器件包括：一半导体衬底，其上具有一沟渠，自半导体衬底的一主表面延伸至一预定深度；一埋入式栅极，设于沟渠的一下部；一栅极氧化层，设于埋入式栅极与半导体衬底之间；一漏极掺杂区，设于沟渠的一第一侧的半导体衬底中；以及一源极掺杂区，设于沟渠的一第二侧，其中源极掺杂区的结深度深于漏极掺杂区的结深度。一L型沟道区域介于漏极掺杂区与源极掺杂区之间，其顺着所述沟渠的第一侧的一侧壁表面至沟渠的一底部表面。

Description

凹入式沟道存取晶体管器件及其制作方法
技术领域
本发明涉及半导体器件，特别是涉及一种凹入式沟道存取晶体管(recessedchannel access transistor,RCAT)器件，其可应用于高密度动态随机存储器(dynamicrandom access memory,DRAM)的领域中。
背景技术
随着半导体组件尺寸的微缩，栅极的沟道长度也随之骤减，这使得短沟道效应以及接点漏电流成为严重的问题。凹入式沟道存取晶体管(recessed channel accesstransistor,RCAT)器件于是被发展出来，其在不增加栅极横向面积的前提下能够增加栅极的沟道长度，故能抑制短沟道效应。
通常，RCAT器件会具有一栅极氧化层，其形成在衬底中凹槽的侧壁及底部表面，再以导电材料填满凹槽。相较于平面型的栅极晶体管栅极是形成在衬底的平坦表面上，RCAT衬底的沟道是顺着凹槽表面的U型，因此利用RCAT器件可以提升积集度。
然而，过去的RCAT器件仍有缺点需要克服，例如，当漏极电压施加于一电连结于NMOS晶体管的电容时，栅极诱发漏极漏电流(gate induced drain leakage,GIDL)即可能发生，会影响到动态随机存储器(dynamic random access memory,DRAM)器件的数据保存特性。
发明内容
本发明的主要目的在于提供一种凹入式沟道存取晶体管器件，以解决上述现有技术的不足与缺点。
本发明的一实施例提出了一种凹入式沟道存取晶体管器件，包含有：一半导体衬底，其上具有一沟渠自半导体衬底的一主表面延伸至一预定深度；一埋入式栅极设于沟渠的一下部；一栅极氧化层设于埋入式栅极与半导体衬底之间；一漏极掺杂区设于沟渠的一第一侧的半导体衬底中；以及一源极掺杂区设于沟渠的一第二侧，其中源极掺杂区的结深度深于漏极掺杂区的结深度。一L型沟道区域介于漏极掺杂区与源极掺杂区之间，其顺着所述第一侧的一侧壁表面至沟渠的一底部表面。
本发明另一实施例提出了一种制作凹入式沟道存取晶体管器件的方法，其步骤包含有：提供一半导体衬底，其上具有一沟渠自所述半导体衬底的一主表面延伸至一预定深度；于所述沟渠的内面形成一栅极氧化层；于所述沟渠的一下部形成一埋入式栅极；以一介电层将所述埋入式栅极盖住；于所述半导体衬底的主表面上形成一垫层以及一硬掩膜层；经由所述垫层以及所述硬掩膜层刻蚀所述半导体衬底，仅于所述沟渠的一侧形成一凹陷区域，其中部分的所述介电层在所述凹陷区域中被裸露出来；去除所述硬掩膜层；以及进行一离子注入工艺以将掺质注入所述沟渠的两侧，于所述半导体衬底中形成一源极掺杂区以及一漏极掺杂区，其中所述源极掺杂区的结深度深于所述漏极掺杂区的结深度。
为让本发明的上述目的、特征及优点能更为明显易懂，下文中列举出几种实施方式配合附图作详细说明。然而如下的实施方式与附图是仅供参考与说明用，并非用来对本发明加以限制。
附图说明
图1至图7以横断面图依序例示出本发明实施例中制作凹入式沟道存取晶体管器件的步骤。
图8至图10以横断面图依序例示出本发明另一实施例中制作凹入式沟道存取晶体管器件的步骤。
图11至图13以横断面图依序例示出本发明又另一实施例中制作凹入式沟道存取晶体管器件的步骤。
其中，附图标记说明如下：
1、1a、1c 凹入式沟道存取晶体管器件
10 半导体衬底， 10a 主表面， 10b 低位上表面
12 沟渠， 12a 侧壁表面， 12b 底面
14 栅极氧化层
16 栅极层， 16a 埋入式栅极
18 介电层
22 垫层
24 硬掩膜层
30 凹陷区域
40、142、144 离子注入工艺
42 漏极掺杂区， 42a： PN结深度
43 掺杂区
44 源极掺杂区， 44a： PN结深度
50 L型沟道区域
60 接触组件
d 深度
具体实施方式
下文中将参照附图来说明本发明的实施细节，该些附图中的内容构成了本发明说明书一部份，并且以可实行实施例的特例描述方式来绘示。下文的实施例已然公开出足够的细节使得本领域的一般技术人员得具以实施。当然，本发明中也可实行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述将不欲被视为是一种限定，反而，其中所包含的实施例将由随附的权利要求来加以界定。
同样地，附图所表示的为实施例中的装置示意图，须注意其并未特别限定装置的尺寸，特别是为了使本发明得以更清晰地呈现，部分组件的尺寸可能夸大地呈现于图中。再者，揭示于多个实施例中的相同组件将会以相同或相似的符号来标示，以更容易且清晰地理解。
对于晶体管与集成电路的制造而言，如在一平面工艺的场合中，「主表面」一词是指那些内部或近处制有多个晶体管的半导体层表面。如文中所使用的，「垂直」一词意指与所述主表面大体上呈直角。一般而言，所述主表面是沿着所制作出的场效应晶体管上的单晶硅层的一<100>平面延伸。
图1至图7以横断面图依序例示出本发明实施例中制作凹入式沟道存取晶体管(recessed channel access transistor,RCAT)器件的制作步骤。如图1所示，首先提供一半导体衬底10，其可以是硅衬底、硅锗衬底、镓砷衬底或其它半导体材料。举例而言，半导体衬底10可以是P型硅衬底。接着在半导体衬底中形成一沟渠12。沟渠12具有一深度d(自半导体衬底10的主表面10a)。沟渠12可以具有一垂直或接近垂直的侧壁表面12a以及一衔接侧壁表面12a的底面12b。
如图2所示，接着进行一氧化工艺于沟渠12的内面形成一栅极氧化层14。再于栅极氧化层14上沉积一栅极层16，并填满沟渠12。例如，栅极层16可以包含多晶硅。
如图3所示，进行一回刻蚀步骤来刻蚀栅极层16，使得凹入的栅极层16的上表面低于半导体衬底10的主表面10a。接着，于半导体衬底10上全面沉积一介电层18，使介电层18填满沟渠12，如此于沟渠12的下部会形成一埋入式栅极16a。
如图4所示，进行一平坦化工艺，例如化学机械抛光工艺，将半导体衬底10主表面10a上多余的介电层18去除。此时，抛光过的介电层18表面将与主表面10a齐平。
如图5所示，接着全面沉积一垫层22，例如硅氧化层，但不限于此。再于垫层22上沉积一硬掩膜层24，例如氮化硅层。
如图6所示，接着进行一光刻及刻蚀工艺仅于沟渠12一侧的半导体衬底10中形成一凹陷区域30，此时部分的介电层18会经由凹陷区域30裸露出来。凹陷区域30中则形成半导体衬底10的低位上表面10b。
如图7所示，将硬掩膜层24剥除但留下垫层22。接着进行一离子注入工艺40将掺质，例如N型掺质，注入沟渠12两侧的半导体衬底10中，意即此实施例中的数字侧(digitside)及胞侧(cell side)，如此形成具有不对称漏极掺杂区42与源极掺杂区44的凹入式沟道存取晶体管器件1。
由于凹入式沟道存取晶体管(RCAT)器件1的数字侧形成有凹陷区域30，故位于数字侧的源极掺杂区44的PN结深度44a将深于位于胞侧的漏极掺杂区42的PN结深度42a。沿着胞侧的侧壁表面12a至沟渠12底面12b则界定有一L型沟道区域50介于漏极掺杂区42与源极掺杂区44之间。
根据本发明实施例，在较佳的情况下，位于数字侧的源极掺杂区44的PN结深度44a约略等于沟渠12的深度d。相较于公知的RCAT器件，本发明位于胞侧的漏极掺杂区42的PN结深度42a可相对较浅，以在运作RCAT器件1时维持足够的运作电流水平。另外，可以在源极掺杂区44形成一接触结构(未示于图中)，以电耦接至一数位线(未示于图中)。
从结构上来说，请参阅图7，本发明的RCAT器件1包含了一半导体衬底10，其上具有一沟渠12自半导体衬底10的一主表面10a延伸至一预定深度d；一埋入式栅极16a设于沟渠12的一下部；一栅极氧化层14设于埋入式栅极16a与半导体衬底10之间；一漏极掺杂区42设于沟渠12的一第一侧(胞侧)的半导体衬底10中；以及一源极掺杂区44设于沟渠12的一第二侧(数字侧)，其中源极掺杂区44的结深度深于漏极掺杂区42的结深度。一L型沟道区域50介于漏极掺杂区42与源极掺杂区44之间，其顺着所述第一侧的一侧壁表面至沟渠12的一底部表面。
图8至图10以横断面图例示出本发明另一实施例中制作凹入式沟道存取晶体管器件的方法。如图8所示，在形成埋入式栅极(或字线)16a之后，如同图4中所示步骤，接着进行一平坦化工艺，例如化学机械抛光工艺，将半导体衬底10主表面10a上多余的介电层18去除。此时抛光过的介电层18表面将会与主表面10a齐平。
接着，进行一离子注入工艺142，将掺质，如N型掺质，注入半导体衬底10的主表面10a中，以于胞侧形成一漏极掺杂区42，以及于数位侧形成一掺杂区43。此时漏极掺杂区42的结深度约等于掺杂区43的结深度。
如图9所示，接着全面沉积一垫层22，例如硅氧化层，但不限于此。再于垫层22上沉积一硬掩膜层24，例如氮化硅层。接着进行一光刻及刻蚀工艺，仅于沟渠12的数位侧半导体衬底10中形成一凹陷区域30，此时部分的介电层18会经由凹陷区域30裸露出来。
利用硬掩膜层24作为离子注入掩膜进行一离子注入工艺144，以将掺质，例如N型掺质，注入沟渠12数字侧的半导体衬底10中，如此形成具有不对称漏极掺杂区42与源极掺杂区44的凹入式沟道存取晶体管器件1a。
由于在凹入式沟道存取晶体管(RCAT)器件1a的数字侧形成有凹陷区域30，位于数字侧的源极掺杂区44的PN结深度44a将深于位于胞侧的漏极掺杂区42的PN结深度42a。沿着胞侧侧壁表面12a至沟渠12底面12b则界定有一L型沟道区域50介于漏极掺杂区42与源极掺杂区44之间。
根据本发明实施例，在较佳的情况下，位于数字侧的源极掺杂区44的PN结深度44a约略等于沟渠12的深度d。相较于公知的RCAT器件，本发明位于胞侧的漏极掺杂区42的PN结深度42a可相对较浅，以在运作RCAT器件1a时维持足够的操作电流水平。另外，可以在源极掺杂区44形成一接触结构(未示于图中)以电耦接至一数位线(未示于图中)。
如图10所示，在完成离子注入工艺144后，可以将硬掩膜层24剥除。
图11至图13以横断面图例示出本发明又另一实施例中一制作凹入式沟道存取晶体管器件的方法。如图11所示，在形成埋入式栅极(或字线)16a之后，如同图4中所示步骤，接着进行一平坦化工艺，例如化学机械抛光工艺，将半导体衬底10主表面10a上多余的介电层18去除。此时，抛光过的介电层18表面将与主表面10a齐平。
接着，同样进行一离子注入工艺142，将掺质，例如N型掺质，注入半导体衬底10的主表面10a中，以于胞侧形成一漏极掺杂区42，于数位侧形成一掺杂区43。此时，漏极掺杂区42的结深度约等于掺杂区43的结深度。
如图12所示，接着全面沉积一垫层22，例如硅氧化层，但不限于此。再于垫层22上沉积一硬掩膜层(未示于图中)，例如氮化硅层。接着进行一光刻及刻蚀工艺，仅于沟渠12的数位侧半导体衬底10中形成一凹陷区域30，此时，部分的介电层18经由凹陷区域30裸露出来。之后再将硬掩膜层剥除，但留下垫层22。
如图13所示，于半导体基底10上沉积一掺杂多晶硅层(未示于图中)并填满凹陷区域30。接着进行一光刻及刻蚀工艺图案化所述掺杂多晶硅层，如此直接在凹陷区域30内形成一接触组件60。再进行一热工艺，将接触组件60内的掺质扩散至与接触组件60直接接触的半导体衬底10中，以形成一源极掺杂区44。
根据本发明实施例，在较佳的情况下，位于数字侧的源极掺杂区44的PN结深度44a约略等于沟渠12的深度d。相较于公知的RCAT器件，本发明位于胞侧的漏极掺杂区42的PN结深度42a可以相对较浅，以在运作RCAT器件1c时维持足够的操作电流水平。另外，在源极掺杂区44形成的接触结构60可以电耦接至一数字线(未示于图中)。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (3)

1.一种制作凹入式沟道存取晶体管器件的方法，其特征在于，包含：
提供一半导体衬底，所述半导体衬底上具有一沟渠，自所述半导体衬底的一主表面延伸至一预定深度；
于所述沟渠的内面形成一栅极氧化层；
于所述沟渠的一下部形成一埋入式栅极；
以一介电层将所述埋入式栅极盖住；
于所述半导体衬底的所述主表面上形成一垫层以及一硬掩膜层；
经由所述垫层以及所述硬掩膜层刻蚀所述半导体衬底，仅于所述沟渠的一侧形成一凹陷区域，其中部分的所述介电层在所述凹陷区域中被裸露出来；
去除所述硬掩膜层；以及
在去除所述硬掩膜层之后，进行一离子注入工艺，将掺质注入所述沟渠的两侧，于所述半导体衬底中形成一源极掺杂区以及一漏极掺杂区，其中所述源极掺杂区的结深度深于所述漏极掺杂区的结深度，其中所述介电层具有一上表面与所述漏极掺杂区的一上表面齐平。
2.根据权利要求1所述的制作凹入式沟道存取晶体管器件的方法，其特征在于，于所述漏极掺杂区和所述源极掺杂区之间形成一L型沟道区域，且所述L型沟道区域顺着所述沟渠的一侧壁表面延伸至所述沟渠的一底部表面。
3.根据权利要求1所述的制作凹入式沟道存取晶体管器件的方法，其特征在于，所述源极掺杂区的结深度等于所述沟渠的所述预定深度。
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