TWI352432B - Trench junction barrier controlled schottky - Google Patents

Trench junction barrier controlled schottky Download PDF

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TWI352432B
TWI352432B TW096131570A TW96131570A TWI352432B TW I352432 B TWI352432 B TW I352432B TW 096131570 A TW096131570 A TW 096131570A TW 96131570 A TW96131570 A TW 96131570A TW I352432 B TWI352432 B TW I352432B
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Taiwan
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trench
schottky
sidewall
schottky diode
region
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TW096131570A
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TW200818519A (en
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Bhalla Anup
K Lui Sik
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Alpha & Omega Semiconductor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H01L29/782—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

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  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

1352432
穿過該溝槽之侧壁；該半導體裝置更包含有一 mosfet裝置與該蕭特 基二極體相整合’以裂備成一溝槽接面阻障蕭特基二極體；該 MOSFET裝置係與該蕭特基二極體同時相互整合並製造，以裝備成一 溝槽接面阻障蕭特基二極體；在一較佳實施例中，該MOSFET係一平 面式（planar)MOSFET裝置與該蕭特基二極體同時相互整合並製造， 其中該平面式MOSFET更包含有一基體區（body region)，延伸並包 圍該蕭特基二極體溝槽之頂端部分，用以屏蔽該逆向漏電流穿過該溝 槽之側壁。在另一個較佳實施例中，該MOSFET係一溝槽式MOSFET 裝置’其係與該蕭特基二極體同時相互整合並製造，以裝備成一溝槽 接面阻障蕭特基（TJBS)二極體，其中該溝槽式MOSFET更包含有 溝槽式閘極，其係位於該TjBS二極體之溝槽周圍；該溝槽式M〇SFET 裝置更包含有一基體區域（body regi〇n )，延伸並包圍在該蕭特基二極 體溝槽之頂端部分，用以屏蔽該逆向漏電流穿過該溝槽之側壁。 在一項試範實施例中，本發明更揭露一種溝槽接面阻障控制式蕭 ^基裝置之製造方法’該方法包含在―第—傳導型半導縣板上開設 -溝槽至中間深度，植人（_丨antjng )—第二傳導型摻雜物在該溝槽 之底部’在實際0。時植入（丨mP丨anting)至該溝槽；該方法更包含一 ，步驟’其係形成—第二傳導型掺雜區，包圍在該溝槽側壁接近該溝 槽之頂端表面’肋屏蔽—逆向難流穿職溝槽之繼；接著，該 =法，續執行另—個步驟，其係填滿_9)—蕭特基阻障金屬於該溝 ^較佳實關中，在—第—傳導型半導體基板開設—溝槽之步 p ’/、係在N型半導體基板開設該溝槽之步驟，而該第二雜區係一 簫特項試範實施例中，本發明更揭露—種溝槽接面阻障控制式 肅特基裝置之·|ι/ j告为.本，封· + 設一溝豸方法包3在—第-傳導型半導體基板上開 2巾間深度，並植人—第二傳導型摻雜物， 9 1^52432 溝槽*度’具有巾間深度之摻雜區包_溝槽之側壁，約在該溝 =中間深度’用以屏蔽—逆向漏電流穿過該溝槽之側壁；接著，該 =執行另—步驟，其係在實際『時填滿·溝射，以摻雜該第二 Z型之—底部摻，包圍該溝槽之底部表面，接著，該方法執行 步驟’其係植入並摻雜一第二傳導型之頂摻雜區，包圍該溝槽側 之^端部分，並填滿(训丨ng>一蕭特基接面阻障金屬於該溝槽；在一 二佳貝施例，中’在—第—傳導型半導體基板開設—溝槽之步驟，其係 人N-型半導體基板開設該溝槽，並掺雜該中間深度之換雜區，其包 ^有-Ρ»雜區；該開設_溝槽至—全龍深度之步驟，其係以非 圓弧型溝槽部分（coners)開設該溝槽至一全深度。 【實施方式】 & 以下所提供之說明内容使具有一般技術之人士能據以實施本發 明，f且翻於—特別顧之情況及其需求。對於熟悉此項技術之人 士而言’針對實施例所做的不同修改則為淺顯易懂的，且在此所定義 之原理可適用於其他實施例及刺，而不會脫離本發明之精神及範 圍，因此，本發明並非僅限制於所述之實施例，故舉凡依本發明申請 專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，其 所產生之功能、作用仍未超出說明書及圖式所涵蓋之精神時，均應包 括於本發明之申請專利範圍内。兹為使f審查委員對本發明找 構、特徵及所達成之功效能有更進-步之瞭解與認識，謹佐以圖式及 較佳具體實施例之詳細說明如后： “請參閱第2A圖，其係本發明一蕭特基二極體1〇〇之剖面圖，該 蕭特基二極體彻係在由—半導體基板所支賴形成在—半導體基板 上，例如：一 N-型摻雜矽基板105。該蕭特基二極體1〇〇包含有複數
個/冓槽’形成複數個半導體平臺（semiconductor mesas)。如第2A 圖中所示之一較佳實施例中，該溝槽係填滿(训ed with)了蕭特基阻障 金屬，例如：鈦(Ti)/石夕化鈦(TiN)或鎢(Tungsten)金屬110 ;在另一較

Claims (1)

1352432 申請專利範圍： 種蕭特基二極體，係包含有： rf5;3i綠正替換頁 100年05月31日修正替換頁 至少一溝槽，其開口在一半導體基板，該半導體基板係摻雜一第一 傳導型換雜物(dopant)’其中，在該溝槽側壁内裡形成(丨丨ned _) 一蕭特基阻障金屬（Schottky barrier metal); 一第二傳導型之頂摻雜區（t〇p_d〇ped「egi〇n)，包圍在該溝槽側壁 之頂端部分，以作為一蕭特基二極體之一逆向電流屏蔽；及 s亥第二傳導型之一底摻雜區（bo^om-dopedregjon)，包圍在該溝 槽之所有底部轉角（comers)，並延伸覆蓋該溝槽之底部表面之 一實質區域，沿該溝槽之側壁形成之該蕭特基阻障金屬，係以一 實質區域直接接觸該第一傳導型之該半導體基板，在該溝槽側壁 上形成該蕭特基二極體，以增強通過該溝槽側壁之順向電流。 2·如申請專利範圍第1項所述之蕭特基二極體，更包括有一個或複數 個第二傳導型摻雜區（d叩ant regi〇n),包圍在該溝槽之側壁 (sidewa丨丨s) ’其係沿著介於該頂摻雜區（top-doped region)及該 底摻雜區（bottom-doped region)之間的溝槽深度而分散，以作 為額外的”亥蕭特基一極體之逆向電流屏蔽，其中在介於該些第二傳 導型摻雜區之間沿該溝槽之側壁的區域形成蕭特基接面，以增強通 過該溝槽側壁之順向電流。 3. 如申明專利範圍第1項所述之蕭特基二極體，其中該溝槽内裡係形 成(lined with) — 蕭特基阻障金屬詹（Schottky barrier metal)。 4. 如申請專利範圍第1項所述之蕭特基二極體，其中該蕭特基阻障金 屬層（Schottky barrier metal)更形成於(lining)該溝槽之底部表 面，以便在ό玄溝槽之底部表面上形成一蕭特基接面。 5·如申請專利範圍第1項所述之蕭特基二極體，其中該第二傳導型之 底摻雜區（bottom-doped region)係完全包圍在該溝槽之底部表 面0 18 1352432 Hi日修正頁100年05月31曰修正替換頁 6·如申請專利範圍第1項所述之蕭特基二^ (〇verlayi ng )在s亥半導體基板之頂端表面係之該蕭特基阻障金屬 層，與介於該第二傳導型之頂摻雜區（t〇p_d〇pedregj〇n)之間之 半導體基板，形成一蕭特基接面。 7.如申請專利範圍第1項所述之蕭特基二極體，其中該第二傳導型之 頂摻雜區（top-doped region)係完全植入介於該溝槽之間之空 内。 二B 8·如申請專利範圍第1項所述之蕭特基二極體，其中該溝槽包含有非 圓狐型轉角（corners)。 9. -種半導體裝置包含有-蕭特基二極體，其係包含一溝槽，該溝槽 位於一第一傳導型之半導體基板（semiconductorsubstrate)中， 其中該半導體裝置包含有： 一第二傳導型之頂摻雜區（top-doped region)，其係相對於該第一 傳導型並包圍該溝槽之側壁之頂端部分，以作為一蕭特基二極體 之一逆向電流屏蔽； Α 一第一傳導型之底摻雜區（bottom-doped region )，其係包圍該溝 槽之底層部分；及 ~ 其中該溝槽之該側壁係形成(丨ine With)一蕭特基阻障金屬層 (Schottky barrier metal),其係具有介於該頂摻雜區與該底^ 雜區之一實質區域，以直接接觸該第一傳導型之該半導體基板: 以增強通過該溝槽側壁之順向電流。 1 〇·如申請專利範圍第9項所述之半導體裝置，更包括有—個或複數個 第二傳導型摻雜區，其係沿著該側壁並分散在介於該頂摻雜區 (top-doped region)及該底摻雜區（bottom-doped region)之間， 以作為額外的該蕭特基二極體之逆向電流屏蔽，其中在介於該些第 二傳導型換雜區之間沿該溝槽之側壁的區域形成蕭特基接面:增 強通過該溝槽側壁之順向電流。 曰 19 1352432 、修正替換頁 1〇〇年〇5月31曰修正替換頁 11.如申專利範圍第9項所述之半導體裝置’其中^肅特基阻障金屬 層係元全地形成(line with)該溝槽之該側壁令。 12·如申請專利範圍第9項所述之半導體裝置，其中該第二傳導型之頂 摻雜區（top-doped region)係在介於該溝槽之該側壁與該半導體 基板之頂端表面形成。 13·如申請專利範圍第9項所述之半導體裝置，其中該第二傳導型之底 摻雜區（bottom-doped region)係包圍在該溝槽之所有底部轉角 (comers) ’並延伸覆蓋該溝槽之底部表面之一實質區域。 14·如申請專利範圍第9項所述之半導體裝置？其中鍍覆於該半導體基 板頂端表面之鋪縣_金屬，其餘介_第二傳導型之頂推 雜區（top-doped region)之間形成一蕭特基接面。 15. 如申請專利範圍第9項所述之半導體裝置，其中該第二傳導型之頂 摻雜區（top-doped region)係延伸至遍及該半導體基板之整個頂 部表面。 16. 如申請專利範圍第9項所述之半導體裂置，其中該溝槽係包含有非 圓孤型底部轉角(corner)。 17·如申請專利範圍第9項所述之半_裝置更包含有一 丁 裝置’其係與該蕭特基二極體相互整合，結構成為一溝槽接面阻障 蕭特基二極體。 18·如申請專利範圍第9項所述之半導體裝置，更包含有一 m〇sfet 裝置，其係同時與該蕭特基二極體相互整合及製造，結構成為一溝 槽接面阻障蕭特基二極體。 19·如申明專利範圍第9項所述之半導體裝置更包含有一平面 (planar) MOSFET裝置，其係同時與該蕭特基二極體相互整合 並’造，其中該平面MOSFET裝置更包含有一基體區（b〇dy reg丨on ’其係延伸並建立該第二傳導型之該頂摻雜區 ，其係包圍 “ .土一極體溝槽之頂端部分，作為屏蔽（访㈣逆向漏 1352432
電流（reverse leakage current)穿過該溝槽之 2〇.如申請專利範圍第9項所述之半導體裝置，更包含有一電晶體胞溝 槽MOSFETg置’其係同時與該蕭特基二極體相互整合並製造， 結構成為一溝槽接面阻障蕭特基二極體’其中該溝槽Mqsfet裝 置更包含有一溝槽式閘極，其係位於該溝槽接面阻障蕭特基二極體 之溝周圍。 21. 如申請專利賴第2G項所述之半導體裝置，其巾該M〇SFET裝 置更包含有-基體區（body region)，其係延伸並建立該第二傳導 型之，頂換雜區’其係包圍在該蕭特基二極體溝槽之頂端部分，作 為屏蔽（shielding) s亥逆向漏電流（reverse |eakage current)穿 過該溝槽之侧壁。 22. 種裝蕭特基一極體之方法，係包含有： 提供第一傳導型摻雜物於一區域中，相對於一第一傳導型，以便 β在該第-料型之半導體基板形成一頂摻雜區； 提供溝槽’穿過#獅雜區至—預定之深度，該頂摻雜區係包圍 槽之侧壁之頂端部分，以作為—蕭特基二極體之-逆向電流 屏蔽’並提供《第二料區型雜物，以形成該第二傳導型之底 摻雜區’其係包圍該溝槽之底層部分；及 " 在該溝槽之侧壁内形成(丨丨ng _)_蕭特基阻障金屬層至少從該 頂摻雜區之-底部延伸至該底摻祕之頂端，以直接接觸該第一 之ί半導體基板’以增強通過該溝槽側壁之順向電流。 •二乾，第22所述之方法’更包含有提供該第二傳導型至 二审tv雜區’包圍在該溝槽之側壁’直到該深度較所預定之深 展更淺些。 24·如申請專利範圍第22所述之方法，更包含、^ ::以換雜該第二傳導型之-底編並包圍:該溝槽=; 21 1352432 9ς由社^ …丁…正替 :蕭所述之方法，更包含有在麟彻填滿陶g) 26·=物議第22所述之方法，其中在u導型之半導體 二换上提供—溝槽之步驟係、在N型半導體基底開設該溝槽，並以P 型摻雜物摻雜於該摻雜區。 27.如^專利顔第25職之方法，其中在該親内填滿—蕭特基 ^金屬層之步驟係包含填滿—鈦(聊化鈦(™)金屬層於該溝 巩如:請專利範圍第25所述之方法，其中在該溝槽内填滿一蕭特基 ΓΪΪ屬層，步驟係包含填滿—鶴(―)金屬層於該溝槽内。 .°睛專她圍第22職之方法，其巾開設該溝槽至該預定深度 （C()me「s)來開設該溝槽至該預 疋之深度。 30. —種蕭特基二極體，係包含有： 至少-溝槽’其開口在-料體基板，該半導體基板係摻雜一第一 ，導型換雜物（dopant)，其中，在該溝槽填滿⑽_丨⑴一 蕭特基阻障金屬（Schottky barrier metal);以及 複數個第二傳導型摻雜d，相對於第-傳導型，包圍在該溝槽側 壁，散佈在該溝槽之深度，以屏蔽一逆向漏電流（咖⑼丨触辦 current)穿過該溝槽之側壁，該複數個第二#導型播雜區更包含 有-頂摻雜區’包圍在該溝槽側壁之頂端部分，以及一底摻雜 區’包圍在s玄溝槽之所有底部轉角（c〇mers)，並延伸覆蓋該溝 槽之底部表面之-實質區域，沿該溝槽之側壁形成之該蕭特基阻 障金屬’係直接接觸該第-傳導型之該半導體基板，以增強通過 該溝槽側壁之順向電流。 22
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TW200818519A (en) 2008-04-16
US20100258897A1 (en) 2010-10-14
US20070034901A1 (en) 2007-02-15
US7737522B2 (en) 2010-06-15
CN101523583A (zh) 2009-09-02
US8445370B2 (en) 2013-05-21
WO2008039548A3 (en) 2008-06-19
WO2008039548A2 (en) 2008-04-03
CN101523583B (zh) 2012-02-29

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