TWI685106B - 高電壓蕭特基二極體 - Google Patents

高電壓蕭特基二極體 Download PDF

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TWI685106B
TWI685106B TW107108139A TW107108139A TWI685106B TW I685106 B TWI685106 B TW I685106B TW 107108139 A TW107108139 A TW 107108139A TW 107108139 A TW107108139 A TW 107108139A TW I685106 B TWI685106 B TW I685106B
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trench
layer
schottky diode
voltage
epitaxial layer
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TW201939742A (zh
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徐信佑
王振煌
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全宇昕科技股份有限公司
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Priority to CN201810366529.3A priority patent/CN110246901A/zh
Priority to US16/296,128 priority patent/US20190280129A1/en
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Abstract

一種高電壓蕭特基二極體，適用於高電壓範圍，其包括基板、磊晶層、複數個摻雜區、複數個溝槽以及金屬層。磊晶層設置於基板上；複數個摻雜區設置於磊晶層內，複數個溝槽分別間隔設置於各摻雜區上且位於磊晶層內，各溝槽具有溝槽氧化層以及半導體層，各溝槽氧化層形成於各溝槽的底部和側壁，各半導體層填滿各溝槽；金屬層設置於磊晶層上，並與磊晶層形成蕭特基接面。其中，由於各溝槽的深度為微米等級且具有溝槽氧化層的配置，因此本發明於高電壓範圍時仍能正常運作。

Description

高電壓蕭特基二極體
本發明關於一種蕭特基二極體，特別是，一種具有溝槽結構且耐高電壓的高電壓蕭特基二極體。
隨著電子技術的進步以及電子產品的小型化趨勢，越來越多電子元件利用積體電路製程的方式生產，然而，積體電路型式的電子元件需考慮許多層面，例如耐壓、相互干擾或抗雜訊之類的問題，尤其是應用在電源電路的電子元件，由於電源電路需接受高電壓的輸入，而高電壓的輸入會導致積體電路型式的電子元件燒毀，進而導致電源電路的故障，其為造成電源電路的尺寸無法縮小的主因。
另外，二極體在電源電路中扮演相當重要的角色，因為二極體具備順向導通及逆向截止的特性，所以在電源電路中，二極體作為整流使用以輸出穩定電壓，而為因應電子產品的小型化趨勢，二極體也逐漸邁向積體電路化的方向，但是當電源電路承受高電壓時，積體電路型式的二極體同樣也會因耐不住高壓而燒毀。
綜觀前所述，本發明之發明者思索並設計一種高電壓蕭特基二極體，以期針對習知技術之缺失加以改善，進而增進產業上之實施利用。
有鑑於上述習知之問題，本發明的目的在於提供一種高電壓蕭特基二極體，用以解決習知技術中所面臨之問題。
基於上述目的，本發明提供一種高電壓蕭特基二極體，適用於高電壓範圍，其包括基板、磊晶層、複數個摻雜區、複數個溝槽以及金屬層。磊晶層設置於基板上；複數個摻雜區設置於磊晶層內，複數個溝槽分別間隔設置於各摻雜區上且位於磊晶層內，各溝槽具有溝槽氧化層以及半導體層，各溝槽氧化層形成於各溝槽的底部和側壁，各半導體層填滿各溝槽；金屬層設置於磊晶層上，並與磊晶層形成蕭特基接面。
較佳地，基板為矽基板，各溝槽氧化層由二氧化矽組成，各半導體層由多晶矽組成。
較佳地，各溝槽氧化層和各半導體層間具有溝槽氮化層，各溝槽氮化層由氮化矽組成。
較佳地，各溝槽氮化層和各半導體層間具有溝槽氧化層，溝槽氮化層位於兩層溝槽氧化層之間。
較佳地，各溝槽的深度為7微米至15微米之間。
較佳地，磊晶層為p型，複數個摻雜區為n型。
較佳地，磊晶層為n型，複數個摻雜區為p型。
較佳地，高電壓範圍為200伏特至800伏特。
承上所述，本發明之高電壓蕭特基二極體，由於各溝槽的深度為微米等級且具有溝槽氧化層和溝槽氮化層的配置，因此本發明在高電壓範圍下仍能正常運行，可將本發明應用於接受高電壓輸入的電源電路中，以達到電源電路小型化的目的。
10‧‧‧基板
20‧‧‧磊晶層
30‧‧‧摻雜區
40‧‧‧溝槽
41‧‧‧溝槽氧化層
42‧‧‧半導體層
43‧‧‧溝槽氮化層
50‧‧‧金屬層
60‧‧‧電極層
SCH‧‧‧蕭特基接面
第1圖為本發明之高電壓蕭特基二極體的第一實施例的結構圖。
第2圖為本發明之高電壓蕭特基二極體的第一實施例的電壓和電流圖。
第3圖為本發明之高電壓蕭特基二極體的第二實施例的結構圖。
第4圖為本發明之高電壓蕭特基二極體的第三實施例的結構圖。
本發明之優點、特徵以及達到之技術方法將參照例示性實施例及所附圖式進行更詳細地描述而更容易理解，且本發明可以不同形式來實現，故不應被理解僅限於此處所陳述的實施例，相反地，對所屬技術領域具有通常知識者而言，所提供的實施例將使本揭露更加透徹與全面且完整地傳達本發明的 範疇，且本發明將僅為所附加的申請專利範圍所定義。
如第1圖所示，其為本發明之高電壓蕭特基二極體的第一實施例的結構圖。於本實施例中，本發明之高電壓蕭特基二極體，其包括基板10、磊晶層20、複數個摻雜區30、複數個溝槽40以及金屬層50。基板10為矽基板；磊晶層20設置於基板10上且為p型；複數個摻雜區30設置於磊晶層20內且為n型，複數個溝槽40分別間隔設置於各摻雜區30上且位於磊晶層20內，各溝槽40具有溝槽氧化層41以及半導體層42，各溝槽氧化層41形成於各溝槽40的底部和側壁，各半導體層42填滿各溝槽40，而各溝槽氧化層41由二氧化矽組成，各半導 體層42由多晶矽組成；金屬層50設置於磊晶層20上，並與磊晶層20形成蕭特基接面SCH。且在基板10下設有電極層60以作為負極，金屬層50作為正極，當施加電壓於本發明時，金屬層50和磊晶層20間形成蕭特基接面SCH，以作為高電壓電源電路的整流元件。
由於各溝槽40的深度為7微米至15微米之間以及各溝槽40具有溝槽氧化層41，且溝槽氧化層41由二氧化矽組成而具備相當高的電阻值而不易導電，因此本發明能承受200伏特至800伏特的高電壓範圍，當然也可根據電子元件的電壓規格需求調整各溝槽40的深度，進而應用於不同電壓規格的電源電路，而不會因為高電壓而燒毀。此時，溝槽氧化層41的厚度設計相當重要，因為若溝槽氧化層41之厚度太薄，則會因為電阻降低而無法承受高電壓。較佳地，溝槽氧化層41的厚度為600奈米至1000奈米，以達成不容易導電之目的，進而能承受高電壓。
另外，複數個摻雜區30和磊晶層20需為低濃度摻雜，因為高濃度摻雜會增加導電性，假若複數個摻雜區30和磊晶層20高濃度摻雜，則會因為導電性增加而在高電壓時燒毀，而需低濃度摻雜複數個摻雜區30和磊晶層20以降低其導電性，從而讓本發明能承受高電壓。較佳地，各摻雜區30的濃度為1015~1017/cm3，磊晶層20的濃度為1014~1016/cm3，基板10本身的濃度1019/cm3，複數個摻雜區30和磊晶層20之濃度與基板10的濃度約相差1000倍，於施加高電壓於本發明時，由於複數個摻雜區30和磊晶層20之低濃度而不容易導通，讓本發明於高電壓時仍能正常運作。
請參閱第2圖，其為本發明之高電壓蕭特基二極體的第一實施例的電壓和電流圖。如第2圖所示，此為本發明之第一實施例之電性圖，並顯露本 發明之第一實施例的電性為蕭特基二極體的特性，量測條件為於電極層60施加高電壓和於金屬層50施加低電壓，造成負極的電壓值比正極的電壓值高，使本發明之高電壓蕭特基二極體於逆偏狀態，其中，逆向臨界電壓約為625V，顯露本發明於600V以上仍能正常運作，進而使本發明於高電壓時仍未燒毀。
請參閱第3圖，其本發明之高電壓蕭特基二極體的第二實施例的結構圖。於本實施例中，相同元件符號之元件，其配置與前述類似，其類似處於此便不再加以贅述。
如第3圖所示，各溝槽氧化層41和各半導體層42間具有溝槽氮化層43，各溝槽氮化層43由氮化矽組成，各溝槽氮化層43和各溝槽氧化層41之間的堆疊順序可互換，亦即，可先分別沉積複數層溝槽氮化層43於複數個溝槽40中，接續沉積複數層溝槽氧化層41和複數層半導體層42，由於氮化矽材料的電阻值也相當高，因此，複數層溝槽氧化層41和複數層溝槽氮化層43的搭配更能耐高電壓。且在基板10下設有電極層60以作為負極，金屬層50作為正極，當施加電壓於本發明時，金屬層50和磊晶層20間形成蕭特基接面SCH，以作為高電壓電源電路的整流元件。
此外，磊晶層20為n型，複數個摻雜區30為p型，當然也可根據實際應用的需求，可將磊晶層20改為p型及複數個摻雜區30改為n型，並未侷限於本發明所列舉的範圍。
請參閱第4圖，其為本發明之高電壓蕭特基二極體的第三實施例的結構圖。於本實施例中，相同元件符號之元件，其配置與前述類似，其類似處於此便不再加以贅述。
如第4圖所示，各溝槽氮化層43和各半導體層42間具有溝槽氧化層41，溝槽氮化層43位於兩層溝槽氧化層41之間，由於兩層溝槽氧化層41和溝槽氮化層43的設置，進而提高電阻值以承受較高的電壓，此外，可根據電子元件的電壓規格調整兩層溝槽氧化層41和溝槽氮化層43的厚度，以符合不同電壓規格的電源電路，而不會因為高電壓而燒毀。
綜上所述，本發明之高電壓蕭特基二極體，利用複數層溝槽氧化層41和複數層溝槽氮化層43的搭配，使本發明於高電壓範圍仍能正常運作，且根據電源電路的電壓規格需求，設計各溝槽40的深度以符合不同的高電壓規格，並在高電壓的電源電路中發揮整流的功能。總而言之，本發明之高電壓蕭特基二極體具有如上述優點，利用複數層溝槽氧化層41和複數層溝槽氮化層43的設置，達成在高電壓運作正常的目的。
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。
10‧‧‧基板
20‧‧‧磊晶層
30‧‧‧摻雜區
40‧‧‧溝槽
41‧‧‧溝槽氧化層
42‧‧‧半導體層
50‧‧‧金屬層
60‧‧‧電極層
SCH‧‧‧蕭特基接面

Claims (7)

  1. 一種高電壓蕭特基二極體，適用於一高電壓範圍，其包含：一基板；一磊晶層，設置於該基板上；複數個摻雜區，設置於該磊晶層內；複數個溝槽，分別間隔設置於各該摻雜區上且位於該磊晶層內，各該溝槽具有一溝槽氧化層以及一半導體層，各該溝槽氧化層形成於各該溝槽的底部和側壁，各該半導體層填滿各該溝槽；一溝槽氮化層，位於該溝槽氧化層和各該半導體層間，該溝槽氮化層由氮化矽組成；以及一金屬層，設置於該磊晶層上，並與該磊晶層形成一蕭特基接面。
  2. 如申請專利範圍第1項所述之高電壓蕭特基二極體，其中，該基板為矽基板，各該溝槽氧化層由二氧化矽組成，各該半導體層由多晶矽組成。
  3. 如申請專利範圍第1項所述之高電壓蕭特基二極體，其中，各該溝槽氮化層和各該半導體層間具有該溝槽氧化層，該溝槽氮化層位於兩層該溝槽氧化層之間。
  4. 如申請專利範圍第1項所述之高電壓蕭特基二極體，其中，各該溝槽的深度為7微米至15微米之間。
  5. 如申請專利範圍第1項所述之高電壓蕭特基二極體，其中，該磊晶層為p型，該複數個摻雜區為n型。
  6. 如申請專利範圍第1項所述之高電壓蕭特基二極體，其中，該 磊晶層為n型，該複數個摻雜區為p型。
  7. 如申請專利範圍第1項所述之高電壓蕭特基二極體，其中，該高電壓範圍為200伏特至800伏特。
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TW200818519A (en) * 2006-09-30 2008-04-16 Alpha & Amp Omega Semiconductor Ltd Trench junction barrier controlled schottky

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