CN101523583B - 沟槽结势垒可控肖特基二极管 - Google Patents

沟槽结势垒可控肖特基二极管 Download PDF

Info

Publication number
CN101523583B
CN101523583B CN200780034677.5A CN200780034677A CN101523583B CN 101523583 B CN101523583 B CN 101523583B CN 200780034677 A CN200780034677 A CN 200780034677A CN 101523583 B CN101523583 B CN 101523583B
Authority
CN
China
Prior art keywords
groove
doped region
conductivity type
schottky
schottky diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN200780034677.5A
Other languages
English (en)
Other versions
CN101523583A (zh
Inventor
雷燮光
安荷·叭剌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nations Semiconductor (Cayman) Ltd.
Original Assignee
Alpha and Omega Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha and Omega Semiconductor Inc filed Critical Alpha and Omega Semiconductor Inc
Publication of CN101523583A publication Critical patent/CN101523583A/zh
Application granted granted Critical
Publication of CN101523583B publication Critical patent/CN101523583B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H01L29/782—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明提供一种肖特基二极管，其包含至少一个开设在具有第一电传导型掺杂物的半导体衬底上的沟槽，其中，该沟槽由肖特基结势垒金属填充。该肖特基二极管还包含一个或多个具有第二电传导型的掺杂区，该掺杂区包围沟槽侧壁，并沿着该沟槽的深度分布，用以屏蔽反向漏电流穿过该沟槽的侧壁。该肖特基二极管还包含一包围沟槽底部表面的具有第二电传导型的底部掺杂区，以及一包围沟槽侧壁顶端部分的具有第二电传导型的顶部掺杂区。在一较佳实施例中，该第一电传导型是N-型电传导型，且中间深度掺杂区包含有一P-掺杂区。

Description

沟槽结势垒可控肖特基二极管
背景技术
本发明涉及一种半导体功率装置，特别是指一种改良且新颖的制造方法与器件结构，以提供一具有屏蔽沟槽栅极的MOSFET装置，其单元提供肖特基源极接触，以改善高频率功率开关、半桥式电路与同步整流应用的性能。 
1.技术领域
随着肖特基二极管(Schottky diode)的应用越来越广泛，特别是在减少功率消耗与增加开关速度上，因此改善器件结构与制作过程，以减少生产肖特基整流器件的成本就变得相当重要。其中一特别重要的考虑是，减少被肖特基二极管占据的半导体衬底上的表面区域。减少利用肖特基二极管的表面区域是减少制造成本的关键，并且可最小化电子器件的尺寸与形状，以达到增强的可携式性与功能性。然而，为了达到上述表面利用的目标，且同时维持电流传导区域，肖特基二极管有时会通过在沟槽(trench)中填充势垒材料来实现。该沟槽肖特基二极管结构中，由于沟槽角落具有尖锐边缘，故非常容易被击穿，因此导致了另一项技术难题。为了解决这项难题，圆弧型的沟槽底是必要的，但是如此会造成生产成本的增加。正因为这些原因，本领域的普通技术人员所设计及制造的包含肖特基二极管的器件仍然面临着技术上的困境及限制，因而无法轻易达成降低生产成本的目的。 
在许多应用上，肖特基二极管已经被用来取代PN二极管。在正向传导模式中，肖特基二极管的低正向下降(drop)可降低器件的功率消耗。肖特基是通过多数载流子传导的，所以在器件的开关特性上，不会发生少数载流子的电荷储存效应。因此，在许多的功率应用中，肖特基二极管是较PN结二极管显得更优异。图1A显示了一典型的肖特基二极管的结构，其中肖特基势垒金属是与n型硅接触的。P+结是位于势垒金属接触区域的边缘，以消除器件的提前击穿。二极管的正向电压是直接正比于肖特基势垒金属的高度的。因此，需要使用具有低肖特基势垒金属的二极管，以减少二极管的传导损失。然而，在反向阻断模式(reverse blocking mode)中，肖特基二极管的漏电流也是由肖特基势垒层的高度决定的。二极管在反向阻断运行时，低的肖特基势垒层高度将引起高的漏电流。 
为了减少肖特基二极管的反向漏电流，P型结被如图1B所示的设置于硅中。在反向阻断模式中，N-硅相较于肖特基势垒金属是处在较高的电位。PN结也是反向偏置。两邻接的P型结所产生的消耗被合并，并且对肖特基势垒屏蔽高反向电压，由此可减少二极管的漏电流。JBS的缺点在于由于P型结而减小了肖特基的表面区域。对较高的击穿电压肖特基二极管，经常需要较深的P型结。较深的结也具有较多的横向扩散。所以，对于高击穿电压JBS而言，可利用的肖特基区域将是相当低的。另一种用来对肖特基势垒屏蔽反向电压的方式是如图1C所示的沟槽MOS势垒肖特基二极管。相对于沟槽肖特基势垒，环绕于沟槽较低部分产生的损耗夹断(pinch off)并且屏蔽了在台面顶上的肖特基势垒结。沟槽的形状会影响沟槽中的电介质的击穿。对底部与顶部角落的磨圆去角是必要的，这样可用来减少TMBS的漏电流。锐角的磨圆去角需要额外的操作步骤与特殊的设备，并且这些需求都会引起制作成本的增加。 
因此，对包含有功率半导体器件的电子器件来说，肖特基二极管的实施一直存在一需求，即其能提供新的器件结构与制作方法来克服并解决上述问题与限制。 
发明内容
本发明的主要目的是提供一种既新颖而又经改良的肖特基二极管，其具有沉积在沟槽中的结势垒金属，该沟槽具有掺杂区域，用以防止在该沟槽侧壁、以及在包围该沟槽的顶端及底部角落处所产生的反向漏电流。来自PN结的损耗提供一种功能以将该肖特基二极管屏蔽于反向电压。由于硅区域的利 用大幅提升，且圆弧型沟槽底部需求的消除，因此，上述所讨论到的传统肖特基所面临的限制与难题因而得以解决。 
本发明的另一个主要目的是提供一种既新颖而又经改良的肖特基器件结构，其通过在沟槽侧壁上形成肖特基结，以达成改良结势垒肖特基(JBS)的硅区域利用的目的。 
本发明的另一个主要目的是提供一种既新颖而又经改良的肖特基器件结构，除了通过在沟槽侧壁上形成肖特基结，以改良结势垒肖特基(JBS)的硅区域的利用的外，该结势垒肖特基(JBS)还沿着沟槽侧壁设置，与平面式或沟槽式MOSFET器件相互组合集成，以改良半导体功率器件的性能。 
本发明的另一个目的是提供一种既新颖而又经改良的肖特基器件结构，除了通过在沟槽侧壁上形成肖特基结，以改良结势垒肖特基(JBS)的硅区域的利用外，该肖特基器件目前是以减少工艺复杂性的简化制程来制造的。此外，和一般制造典型的MOSFET功率器件一样，该经简化的制造过程是以标准制程步骤来执行的，因此可大幅减低生产的成本，又可方便地与标准MOSFET器件相互组合集成。 
简单而言，在一个较佳实施例中，本发明所公开的肖特基二极管，其至少包含一个沟槽，该沟槽开设在具有第一电传导型掺杂物的半导体衬底上，其中该沟槽内填满肖特基结势垒金属。该肖特基二极管更包含有一具有第二电传导型的掺杂区，其在接近沟槽顶部以及在沟槽底部处包围该沟槽侧壁，以屏蔽反向漏电流穿过该沟槽侧壁。在一较佳实施例中，该第一电传导型为一N型电传导型，而位于沟槽中间深度的掺杂区是一P-掺杂区。 
在另一个较佳实施例中，本发明公开一肖特基二极管，其至少包含一个沟槽，该沟槽开设在具有第一电传导型掺杂物的半导体衬底上，其中该沟槽内填满肖特基结势垒金属。该肖特基二极管更包含有一个或多个具有第二电传导型的掺杂区，其包围沟槽测壁，且沿着该沟槽深度方向分布，用以屏蔽一反向漏电流穿过该沟槽的侧壁。该肖特基二极管更包含有一具有第二电传导型的包围沟槽底部表面的底部掺杂区，以及一具有第二电传导型的包围沟槽侧壁顶部部分的顶端掺杂区。 
本发明的另一个较佳实施例包含有一半导体器件，该半导体器件包含有一肖特基二极管，该肖特基二极管至少包含一个沟槽，该沟槽开设在具有第 一电传导型掺杂物的半导体衬底上，其中该沟槽内填满肖特基结势垒金属。该半导体器件更包含一具有第二电传导型的掺杂区，其包围该沟槽顶端的侧壁及沟槽的侧壁，用以屏蔽一反向漏电流穿过该沟槽的侧壁。该半导体器件还包含有一MOSFET器件与该肖特基二极管集成，以装配成一沟槽结势垒肖特基(TJBS)二极管。该MOSFET器件与该肖特基二极管同时相互集成并制造，以装配成一沟槽结势垒肖特基(TJBS)二极管。在一较佳实施例中，该MOSFET是一平面式(planar)MOSFET器件，其与该肖特基二极管同时集成并制造，其中该平面式MOSFET更包含有一本体区域(body region)，该本体区域延伸至该肖特基二极管沟槽的顶端部分，并将其包围，用以屏蔽该反向漏电流穿过该沟槽的侧壁。在另一个较佳实施例中，该MOSFET是一沟槽MOSFET器件，其与该肖特基二极管同时集成并制造，以装配成一沟槽结势垒肖特基(TJBS)二极管，其中该沟槽式MOSFET还包含有沟槽栅极，其位于该TJBS二极管的沟槽周围。该沟槽MOSFET器件还包含有一本体区域，其延伸至该肖特基二极管沟槽的顶端部分，并将其包围，用以屏蔽该反向漏电流穿过该沟槽的侧壁。 
在一个具体实施例中，本发明还公开了一种沟槽结势垒可控肖特基器件的制造方法。该方法包含步骤：在一具有第一电传导型的半导体衬底上开设一沟槽至中间深度，在基本为0度的角度将具有第二电传导型的掺杂物植入到沟槽的底部。该方法还包含形成一个具有第二电传导型的掺杂区的步骤，该掺杂区域包围接近沟槽顶端表面的沟槽侧壁，用以屏蔽一反向漏电流穿过该沟槽的侧壁。接着，该方法继续执行另一个步骤：用肖特基势垒金属填充该沟槽。在一较佳实施例中，所述的在具有第一电传导型的半导体衬底上开设沟槽的步骤，是在一N型半导体衬底上开设该沟槽，而该具有第二电传导型的掺杂区是P-型的。 
在另一个具体实施例中，本发明还公开了一种沟槽结势垒可控肖特基器件的制造方法。该方法包含步骤：在一具有第一电传导型的半导体衬底上开设一沟槽至中间深度，并植入具有第二电传导型的掺杂物，以形成一具有第二电传导型的中间深度掺杂区。该方法还包含一步骤：开设该沟槽至一全沟槽深度，使得该具有中间深度的掺杂区大约在该沟槽的中间深度处包围该沟槽的侧壁，用以屏蔽一反向漏电流穿过该沟槽的侧壁。接着，该方法执行另 一步骤：在基本为0角度时对沟槽进行植入，以在围绕该沟槽的底部表面上掺杂形成具有第二电传导型的底部掺杂区。接着，该方法执行另一步骤：在包围沟槽侧壁的顶端部分植入并掺杂形成具有第二电传导型的顶部掺杂区，并在沟槽中填充肖特基结势垒金属。在一较佳实施例中，所述的在具有第一电传导型的半导体衬底上开设沟槽的步骤，是在一N型半导体衬底上开设该沟槽，并掺杂形成为P型掺杂区的中间深度掺杂区。所述的将沟槽开设到全沟槽深度的步骤，是以非圆弧型沟槽角落开设该沟槽到全深度。 
对于本发明的普通技术人员来说，当阅读以下结合附图的详细说明后，本发明的以上和其他的目的和特点无疑是显而易见的。 
附图说明
图1A-1C是现有技术中所公开的肖特基二极管的剖面图。 
图2A和图2B是本发明肖特基二极管的剖面图。 
图3和图4分别是图2A所显示的二极管与平面沟槽MOSFET器件集成的剖面图。 
图5A-5N是一系列描述制造图2B中所示的肖特基器件的制程剖面图。 
具体实施方式
图2A是本发明肖特基二极管100的剖面图。该肖特基二极管100由一半导体衬底支撑并形成在该半导体衬底中，例如：N-型掺杂硅衬底105。该肖特基二极管100包含有若干个沟槽，形成若干个半导体平台(semiconductormesas)。在图2A中所示的一较佳实施例中，该沟槽中填充有例如钛(Ti)/氮化钛(TiN)或钨金属110的肖特基势垒金属。在另一较佳实施例中(图中未示)，半导体平台的至少一部分垂直表面上填满肖特基势垒金属。为了防止因反向电压而产生的漏电流，P-掺杂区130在平台上形成，其包围在沟槽的顶端部分周围，而P-掺杂区140形成并包围在该沟槽的底部。 
如图2A所示，P-掺杂区130形成在平台顶端的角落部分(corners)，并未延伸至该平台的整个顶端表面。肖特基结也形成在介于P-掺杂区130之间的半导体平台的顶端表面。在另一较佳实施例中(图中未示)，P-掺杂区130延伸到该若干沟槽之间的整个空间，且没有在半导体平台的顶端表面形成肖特基 结。如图2A所示，P-掺杂区140包围在沟槽较低的角落(corners)及底部表面，且没有在该底部表面上形成肖特基结。在另一较佳实施例中(图中未示)，P-掺杂区140只在该沟槽的底部角落周围形成，且肖特基结形成在沟槽的部分底部表面上。通过在该沟槽的底部角落周围形成P-掺杂区140，圆弧化沟槽底部表面的需求将不复存在。此外，用于电流传导的硅利用大幅改良，且可有效地防止反向漏电流穿过该P-掺杂区130及P-掺杂区140，以形成一道反向电流屏蔽。 
图2B是本发明所公开肖特基二极管200的剖面图，其通过深沟槽中的额外沟槽侧壁区域，可进一步提高硅利用。肖特基二极管200类似于肖特基二极管100，除了该肖特基二极管200中的沟槽深度较深。此外，一个或多个P-掺杂区120沿着该沟槽的深度分布，并形成在该沟槽侧壁的周围。可有效防止该反向漏电流穿过该P-掺杂区120、P-掺杂区130及P-掺杂区140，以形成一道反向电流屏蔽。而且，通过沿着深沟槽侧壁所增加的更多的P-掺杂区，可大幅改良用于电流传导的硅区域利用。 
图2A及图2B的肖特基器件通过在沟槽侧壁上形成肖特基二极管，达到了改良该结势垒肖特基二极管(JBS)的硅区域利用的目的。此外，图2B中所示的肖特基器件还达到了减少工艺复杂性的目的，这将会在以下对图5A-5N的描述中进一步加以说明。图2A和2B中所示的结构，可通过标准制程步骤来制造，如同典型MOSFET功率器件的常规实现方式，因此可大幅减低生产的成本，又可方便地与标准MOSFET器件组合集成，此部分也将会在下面进一步描述和说明。 
本发明中，该肖特基势垒二极管形成在该沟槽的侧壁上。该P-型扩散区形成在该沟槽侧壁上，因此，来自PN结的消耗可将肖特基势垒屏蔽于反向电压。如图2B所示，只有两个垂直肖特基的表面片段(segments)，然而，该肖特基的表面片段的数量是可增加的，并且肖特基沟槽室(cab)的数量也可进一步增加，其仅受到制造工艺的限制。此方法的硅区域利用大副超越了如图1A-1C中所示的使用JBS结构的传统肖特基二极管的硅区域利用。 
由于该沟槽的顶端及底部角落被P-型扩散区域所包围。其弯曲率并不会影响电场，如TMBS。如图2A和2B所示的沟槽结势垒可控肖特基二极管不再为了减少漏电流而需要使该沟槽角落变成圆弧状。所以，就不需要再执行一 圆弧化制程。与图1C中所示的沟槽MOS势垒肖特基二极管相比，由于简化了制造过程因而使得生产成本随之减低。 
此外，本发明可以极小的制作复杂性，轻易地与功率MOSFET技术集成。图5和图6分别显示了该肖特基二极管是如何与一平面功率MOSFET及一沟槽功率MOSFET集成的。 
如图3所示，显示的是一平面MOSFET与图2A中所示的沟槽结势垒可控肖特基的集成。该平面MOSFET器件150由一由外延层155所形成的衬底支撑。该平面MOSFET器件150包含一如图2A所示的沟槽结势垒可控肖特基器件100。该MOSFET器件包含本体区域130’(body regions)，其可能是该沟槽结势垒可控肖特基的顶端P-掺杂区的热扩散区。该平面MOSFET器件还还包含有一被本体区域130’包围的源极区160。一平面栅极170位于该衬底的顶端表面，该衬底填塞(padded with)有一栅极氧化层175，用以控制一在相邻的源极区160和本体区域130’之间所形成的沟道。该沟槽结势垒可控肖特基电连接于一金属接触区域110’，且该平面栅极电连接于一分离栅极接触衬垫(图中未示)。该MOSFET的源极及本体触点是通过该源极和本体与肖特基沟槽内部的金属相接触来提供的。更高浓度的本体掺杂区130可植入到肖特基二极管的沟槽周围，以增加顶部掺杂区的浓度，并改善MOSFET本体区域的欧姆接触。 
图4所示为一沟槽MOSFET与图2A所示的沟槽结势垒可控肖特基的集成。该沟槽MOSFET器件150’由一由外延层155所形成的衬底支撑。该沟槽MOSFET器件150’包含有一如图2A所示的沟槽结势垒可控肖特基器件100。该MOSFET器件包含本体区域130，其可是该沟槽结势垒可控肖特基的P-掺杂区的热扩散区。该沟槽MOSFET器件还包含有一被本体区域130包围的源极区160。一沟槽栅极170’位于一沟槽中，该沟槽由一位于两个MOSFET单元(cells)之间的栅极氧化层175’所填衬，用以控制一沿着该沟槽栅极170’的侧壁而形成的垂直沟道，该沟槽栅极170’的侧壁位于源极区160和漏极之间，而该漏极位于该衬底底部。该沟槽结势垒可控肖特基电连接一金属接触区域110’，且该平面栅极电连接一分离的栅极接触衬垫(图中未示)。 
图5A到5N是说明图2B中所示的沟槽结势垒可控肖特基器件的制程步骤的一系列侧剖面图。如图5A所示，进行初始氧化，随后利用光致抗蚀剂掩模208进行氧化蚀刻，从而在半导体衬底205的顶部上图案化若干遮蔽氧化层 (screen oxide layer)210。如图5B所示，移除该光致抗蚀剂掩模208，随后进行硼植入以形成若干个P-掺杂区。如图5C所示，执行一退火(annealing)和氧化程序，来退火并生长该氧化层210，使其覆盖该衬底的整个顶端表面。在图5D中，应用沟槽掩模212在氧化层210上开设若干个蚀刻开口218。 
如图5E所示，执行一硅蚀刻以开设若干个沟槽218，接着，移除光致抗蚀剂掩模212。如图5F所示，在0角度倾斜时执行硼(boron)植入，随后进行扩散以在该沟槽218的底部形成若干个P-掺杂区220。如图5G所示，再执行一硅蚀刻，以将沟槽蚀刻到更深的深度，留下该P-掺杂区220如一环状般在该沟槽大约中间点处包围该沟槽侧壁。如图5H所示，进行垂直0角度的硼植入，以形成一围绕在沟槽218底部的P-掺杂区225。 
如图5I所示，执行一氧化湿蚀刻(wet oxide etch)，通过将沟槽开口处的氧化层210的一部分蚀刻掉，以扩大该沟槽的开口。如图5J所示，沉积一钛(Ti)/氮化钛的薄膜层，随后通过化学气相沉积(CVD)制程来沉积一钨层230。如图5K所示，执行一钛/氮化钛或钨的回蚀刻，以便从该顶端表面移除该钛/氮化钛或钨层。如图5L所示，利用一接触掩模来移除该沟槽上方顶端表面的氧化层210。如图5M所示，一钛/氮化钛/铝接触层240被沉积在顶端表面上。接着，如图5N所示，利用一金属掩模(图中未示)来将金属接触层240蚀刻成接触部分(contact segment)240，以完成本发明的沟槽结势垒可控肖特基器件的制造过程。 
该半导器件包含一形成在具有第一电传导型的半导体平台上的肖特基二极管，在该半导体平台中，一具有相对于第一电传导型的第二电传导型的顶端掺杂区是沿着侧壁的顶端部分设置的。一具有第二电传导型的底部掺杂区位于沿着该侧壁的底部部分。该侧壁的一部分布满肖特基势垒金属，至少从具有第二电传导型的顶端掺杂区的底部延伸至具有第二电传导型的底部掺杂区的顶端。该具有第二电传导型的一个或多个掺杂区是在顶端掺杂区和底部掺杂区之间沿着该侧壁的深度方向分布设置的，且肖特基势垒金属是完全地排列布满在该侧壁上。该具有第二电传导型的顶端掺杂区形成在该半导体平台的顶端角落(corner)上。该具有第二电传导型的底部掺杂区形成在该半导体平台的至少一个底部角落周围。该肖特基结金属镀覆在该半导体平台的顶端表面，以在位于具有第二电传导型的顶端掺杂区之间的区域形成一肖特 基结。该具有第二电传导型的顶端掺杂区延伸到该半导体平台的整个顶端表面，且该半导体平台包含有非圆弧状角落。一MOSFET器件与该肖特基二极管集成，以装配成一沟槽结势垒肖特基(TJBS)二极管，且该MOSFET器件是与该肖特基二极管同时制造，来装配成一沟槽结势垒肖特基(TJBS)二极管。该半导体器件还包含有一平面MOSFET器件，其与该肖特基二极管同时集成和制造，其中该平面MOSFET还包含有一本体区域，延伸到该肖特基二极管沟槽的顶端部分，并将其包围，以屏蔽一反向漏电流穿过该沟槽的侧壁。在一较佳实施例中，该半导体器件还包含有一沟槽MOSFET器件，其是与该肖特基二极管同时集成及制造，来装配成一沟槽结势垒肖特基(TJBS)二极管，其中所述的沟槽MOSFET还包含沟槽式栅极，其位于该TJBS二极管沟槽的周围。在一较佳实施例中，该MOSFET器件还包含有一本体区域，延伸至该肖特基二极管沟槽的顶端部分，并将其包围，用以屏蔽反向漏电流穿过该沟槽的侧壁。 
根据上述描述，本发明公开了一肖特基二极管，其在掺杂有第一电传导型掺杂物的半导体衬底上至少开设一个沟槽，其中所述的该沟槽由肖特基势垒金属填充。该肖特基二极管还包含具有相对于第一电传导型的第二电传导型的若干掺杂区，其包围沟槽侧壁，并沿着该沟槽的深度方向分布，用以屏蔽一反向漏电流穿过该沟槽侧壁；该些具有第二电传导型的若干掺杂区还包含一覆盖在肖特基势垒金属顶端的顶端掺杂区，以及一覆盖在肖特基势垒金属底部的底部掺杂区。 
虽然本发明对上述优选实施例进行了详细的描述，但是这些公开不应该理解为对发明的限制。本领域的普通技术人员在阅读上述公开的内容后，无疑可以实现本发明的各种替代和变形。因此，应该认为本发明的所有替换和修改都包含在本发明的精神和范围之内。 

Claims (30)

1.一种肖特基二极管，其特征在于，包含：
至少一沟槽，其开设在由第一电传导型掺杂物掺杂的半导体衬底上，所述的沟槽侧壁上填满肖特基势垒金属；
一具有第二电传导型的顶部掺杂区，其包围该沟槽侧壁的顶端部分；和
一具有第二电传导型的底部掺杂区，其包围该沟槽的全部底部角落区域，并且延伸遍布至该沟槽的底部下方的区域；该沟槽侧壁上填满肖特基势垒金属的区域直接与由第一电传导型掺杂物掺杂的半导体衬底连接接触。
2.如权利要求1所述的肖特基二极管，其特征在于，还包含：
一个或若干个具有第二电传导型的掺杂区，所述的掺杂区包围该沟槽的侧壁，并在所述的顶部掺杂区及底部掺杂区之间沿着沟槽的深度分布；同时该沟槽仍然保留部分开放的区域并未被所述的具有第二电传导型、且沿着沟槽侧壁设置的若干掺杂区包围；该些沟槽的开放区域上填满肖特基势垒金属，且直接与由第一电传导型掺杂物掺杂的半导体衬底连接接触。
3.如权利要求1所述的肖特基二极管，其特征在于，所述的沟槽由肖特基势垒金属填充。
4.如权利要求1所述的肖特基二极管，其特征在于，所述的肖特基势垒金属还分布在沟槽的底部表面上，在该沟槽的底部表面上形成一肖特基结。
5.如权利要求1所述的肖特基二极管，其特征在于，所述的具有第二电传导型的底部掺杂区完全包围该沟槽的底部表面。
6.如权利要求1所述的肖特基二极管，其特征在于，所述的肖特基势垒金属镀覆在该半导体衬底的顶端表面，在位于具有第二电传导型的顶部掺杂区之间的区域，与半导体衬底形成肖特基结。
7.如权利要求1所述的肖特基二极管，其特征在于，所述的具有第二电传导型的顶部掺杂区完全填充在位于沟槽之间的空间内。
8.如权利要求1所述的肖特基二极管，其特征在于，所述的沟槽包含非圆弧型沟槽角落区域。
9.一种半导体器件，其包含有一肖特基二极管，所述的肖特基二极管包含一沟槽，其设置在一具有第一电传导型的半导体衬底上，其中，所述的半导体器件还包含：
一具有相对于第一电传导型的第二电传导型的顶部掺杂区，所述的顶部掺杂区包围该沟槽的顶端部分设置，以作为所述肖特基二极管的一反向电流屏蔽；
一具有第二电传导型的底部掺杂区，其包围该沟槽的底层部分设置；且
所述的沟槽侧壁布满肖特基势垒金属，其位于顶部掺杂区和底部掺杂区之间的那部分区域直接与具有第一电传导型的半导体衬底连接接触。
10.如权利要求9所述的半导体器件，其特征在于，还包括：
一个或若干个具有第二电传导型的掺杂区，所述的掺杂区在该顶部掺杂区和底部掺杂区之间沿着侧壁的深度方向分布；同时该沟槽仍然保留部分开放的区域并未被所述的具有第二电传导型、且沿着沟槽侧壁设置的若干掺杂区包围；该些沟槽的开放区域上填满肖特基势垒金属，且直接与由第一电传导型掺杂物掺杂的半导体衬底连接接触。
11.如权利要求9所述的半导体器件，其特征在于，所述的肖特基势垒金属完全布满在所述沟槽的侧壁上。
12.如权利要求9所述的半导体器件，其特征在于，所述的具有第二电传导型的顶部掺杂区形成在所述沟槽侧壁和半导体衬底顶部表面之间的一个顶端角落区域。
13.如权利要求9所述的半导体器件，其特征在于，所述的具有第二电传导型的底部掺杂区包围该沟槽的全部底部角落区域，并且延伸遍布至该沟槽的底部下方的区域。
14.如权利要求9所述的半导体器件，其特征在于，所述的肖特基势垒金属镀覆在该半导体衬底的顶端表面，其在具有第二电传导型的顶部掺杂区之间的区域处形成一肖特基结。
15.如权利要求9所述的半导体器件，其特征在于，所述的具有第二电传导型的顶部掺杂区延伸到遍及该半导体衬底的整个顶部表面。
16.如权利要求9所述的半导体器件，其特征在于，所述的沟槽包含有非圆弧型底部角落区域。
17.如权利要求9所述的半导体器件，其特征在于，还包含：
一MOSFET器件，其与该肖特基二极管集成，构成一沟槽结势垒肖特基二极管。
18.如权利要求9所述的半导体器件，其特征在于，还包含：
一MOSFET器件，其与该肖特基二极管同时制造并集成，构成一沟槽结势垒肖特基二极管。
19.如权利要求9所述的半导体器件，其特征在于，还包含：
一平面MOSFET器件，其与该肖特基二极管同时集成和制造，其中该平面MOSFET器件还包含有一本体区域，所述的本体区域延伸并构成具有第二电传导型的顶部掺杂区域，该顶部掺杂区域包围该肖特基二极管沟槽的顶端部分，以屏蔽反向漏电流穿过该沟槽的侧壁。
20.如权利要求9所述的半导体器件，其特征在于，还包含：
一沟槽MOSFET器件，其与该肖特基二极管同时集成和制造，构成一沟槽结势垒肖特基二极管，其中，所述的沟槽MOSFET还包含沟槽栅极，其设置在该沟槽结势垒肖特基二极管的沟槽周围。
21.如权利要求20所述的半导体器件，其特征在于，所述的MOSFET器件还包含一本体区域，其延伸并构成具有第二电传导型的顶部掺杂区域，该顶部掺杂区域包围该肖特基二极管沟槽的顶端部分，以屏蔽该反向漏电流穿过该沟槽的侧壁。
22.一种制造肖特基二极管的方法，其特征在于，包含：
提供一个具有与第一电传导型相反的第二电传导型掺杂物的区域，以在该具有第一电传导型的半导体衬底上形成一顶部掺杂区；
提供一沟槽，其穿过该顶部掺杂区到一预定的深度，并提供具有第二电传导型的掺杂物以形成具有第二电传导型的底部掺杂区，该底部掺杂区包围沟槽的全部底部角落区域，并且延伸遍布至该沟槽的底部下方区域；且
在该沟槽的侧壁上形成一肖特基势垒金属层，所述的肖特基势垒金属层至少从该顶部掺杂区的底部延伸到该底部掺杂区的顶端，该肖特基势垒金属层直接与具有第一电传导型的半导体衬底连接接触。
23.如权利要求22所述的方法，其特征在于，还包含：
提供至少一个具有第二电传导型中间掺杂区，其在比所述的预定深度较浅的深度处包围该沟槽侧壁。
24.如权利要求22所述的方法，其特征在于，还包含：
在基本0角度时对该沟槽进行植入的步骤，以掺杂形成包围该沟槽底部表面的具有第二电传导型的底部掺杂区。
25.如权利要求24所述的方法，其特征在于，还包含在该沟槽内填充肖特基势垒金属的步骤。
26.如权利要求22所述的方法，其特征在于，所述的在具有第一电传导型的半导体衬底上提供一沟槽的步骤，是在一N型半导体衬底上开设该沟槽，并以P型掺杂物掺杂该掺杂区的步骤。
27.如权利要求25所述的方法，其特征在于，所述的在沟槽内填充肖特基势垒金属的步骤，包含填充钛/氮化钛金属到该沟槽内的步骤。
28.如权利要求25所述的方法，其特征在于，所述的在沟槽内填满肖特基势垒金属的步骤，包含填充钨金属到该沟槽内的步骤。
29.如权利要求22所述的方法，其特征在于，所述的开设沟槽到预定深度的步骤，包含以非圆弧沟槽角落区域来开设该沟槽到预定深度的步骤。
30.一种肖特基二极管，其特征在于，包括：
至少一个沟槽，其开设在以第一电传导型掺杂物掺杂的半导体衬底上，所述的沟槽内填充肖特基势垒金属；且
若干个具有与第一电传导型相反的第二电传导型的掺杂区域，其围绕沟槽侧壁，且沿着沟槽的深度分布，以屏蔽反向漏电流穿过所述沟槽的侧壁；所述的若干具有第二电传导型的掺杂区还包含一覆盖肖特基势垒金属顶端的顶端掺杂区，以及一覆盖肖特基势垒金属底部的底部掺杂区；
所述的底部掺杂区包围该沟槽的全部底部角落区域，并且延伸遍布至该沟槽的底部下方的区域；该沟槽侧壁上填满肖特基势垒金属、且未被所述掺杂区域包围的区域直接与由第一电传导型掺杂物掺杂的半导体衬底连接接触。
CN200780034677.5A 2006-09-30 2007-09-30 沟槽结势垒可控肖特基二极管 Active CN101523583B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/541,189 US7737522B2 (en) 2005-02-11 2006-09-30 Trench junction barrier controlled Schottky device with top and bottom doped regions for enhancing forward current in a vertical direction
US11/541,189 2006-09-30
PCT/US2007/021107 WO2008039548A2 (en) 2006-09-30 2007-09-30 Trench junction barrier controlled schottky

Publications (2)

Publication Number Publication Date
CN101523583A CN101523583A (zh) 2009-09-02
CN101523583B true CN101523583B (zh) 2012-02-29

Family

ID=39230842

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200780034677.5A Active CN101523583B (zh) 2006-09-30 2007-09-30 沟槽结势垒可控肖特基二极管

Country Status (4)

Country Link
US (2) US7737522B2 (zh)
CN (1) CN101523583B (zh)
TW (1) TWI352432B (zh)
WO (1) WO2008039548A2 (zh)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7671439B2 (en) * 2005-02-11 2010-03-02 Alpha & Omega Semiconductor, Ltd. Junction barrier Schottky (JBS) with floating islands
US7737522B2 (en) * 2005-02-11 2010-06-15 Alpha & Omega Semiconductor, Ltd. Trench junction barrier controlled Schottky device with top and bottom doped regions for enhancing forward current in a vertical direction
US8432012B2 (en) * 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
US8232558B2 (en) 2008-05-21 2012-07-31 Cree, Inc. Junction barrier Schottky diodes with current surge capability
JP5439763B2 (ja) 2008-08-14 2014-03-12 富士電機株式会社 半導体装置および半導体装置の製造方法
US8188538B2 (en) 2008-12-25 2012-05-29 Rohm Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
JP5588670B2 (ja) 2008-12-25 2014-09-10 ローム株式会社 半導体装置
US7943989B2 (en) * 2008-12-31 2011-05-17 Alpha And Omega Semiconductor Incorporated Nano-tube MOSFET technology and devices
US8148749B2 (en) * 2009-02-19 2012-04-03 Fairchild Semiconductor Corporation Trench-shielded semiconductor device
JP2011134910A (ja) 2009-12-24 2011-07-07 Rohm Co Ltd ＳｉＣ電界効果トランジスタ
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
CN102263138A (zh) * 2010-05-31 2011-11-30 刘晓健 新型结构的保护用二极管
US8431470B2 (en) * 2011-04-04 2013-04-30 Alpha And Omega Semiconductor Incorporated Approach to integrate Schottky in MOSFET
US8502302B2 (en) 2011-05-02 2013-08-06 Alpha And Omega Semiconductor Incorporated Integrating Schottky diode into power MOSFET
US9331065B2 (en) 2011-05-17 2016-05-03 Semiconductor Components Industries, Llc Semiconductor diode and method of manufacture
US8502336B2 (en) 2011-05-17 2013-08-06 Semiconductor Components Industries, Llc Semiconductor diode and method of manufacture
US8507978B2 (en) 2011-06-16 2013-08-13 Alpha And Omega Semiconductor Incorporated Split-gate structure in trench-based silicon carbide power device
CN102931215B (zh) * 2011-08-11 2015-02-04 上海华虹宏力半导体制造有限公司 集成有低漏电肖特基二极管的igbt结构及其制备方法
US9059329B2 (en) * 2011-08-22 2015-06-16 Monolithic Power Systems, Inc. Power device with integrated Schottky diode and method for making the same
US8680587B2 (en) 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
US8610235B2 (en) 2011-09-22 2013-12-17 Alpha And Omega Semiconductor Incorporated Trench MOSFET with integrated Schottky barrier diode
US8836024B2 (en) * 2012-03-20 2014-09-16 Semiconductor Components Industries, Llc Electronic device including a trench and a conductive structure therein having a contact within a Schottky region and a process of forming the same
CN103367436B (zh) * 2012-04-03 2017-08-08 朱江 一种沟槽肖特基mos半导体装置及其制造方法
JP2014120685A (ja) * 2012-12-18 2014-06-30 Toshiba Corp 半導体装置
US9024383B2 (en) * 2013-05-01 2015-05-05 Infineon Technologies Austria Ag Semiconductor device with a super junction structure with one, two or more pairs of compensation layers
US9117694B2 (en) 2013-05-01 2015-08-25 Infineon Technologies Austria Ag Super junction structure semiconductor device based on a compensation structure including compensation layers and a fill structure
US9741851B2 (en) * 2013-05-13 2017-08-22 Alpha And Omega Semiconductor Incorporated Trench junction barrier controlled Schottky
KR101999407B1 (ko) 2013-05-23 2019-10-02 매그나칩 반도체 유한회사 쇼트키 다이오드 내장 반도체 소자 및 그 제조 방법
US9331197B2 (en) 2013-08-08 2016-05-03 Cree, Inc. Vertical power transistor device
US10868169B2 (en) 2013-09-20 2020-12-15 Cree, Inc. Monolithically integrated vertical power transistor and bypass diode
US20150084063A1 (en) * 2013-09-20 2015-03-26 Cree, Inc. Semiconductor device with a current spreading layer
US9318597B2 (en) 2013-09-20 2016-04-19 Cree, Inc. Layout configurations for integrating schottky contacts into a power transistor device
US10600903B2 (en) 2013-09-20 2020-03-24 Cree, Inc. Semiconductor device including a power transistor device and bypass diode
DE102014203851B4 (de) * 2014-03-03 2021-11-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Schaltungsanordnung
DE102015204137A1 (de) * 2015-03-09 2016-09-15 Robert Bosch Gmbh Halbleitervorrichtung mit einer Trench-Schottky-Barrier-Schottky-Diode
US10388781B2 (en) 2016-05-20 2019-08-20 Alpha And Omega Semiconductor Incorporated Device structure having inter-digitated back to back MOSFETs
US10446545B2 (en) 2016-06-30 2019-10-15 Alpha And Omega Semiconductor Incorporated Bidirectional switch having back to back field effect transistors
CN106057913A (zh) * 2016-06-30 2016-10-26 南通康比电子有限公司 一种新型沟槽式势垒肖特基二极管及其生产工艺
US10103140B2 (en) 2016-10-14 2018-10-16 Alpha And Omega Semiconductor Incorporated Switch circuit with controllable phase node ringing
US10199492B2 (en) 2016-11-30 2019-02-05 Alpha And Omega Semiconductor Incorporated Folded channel trench MOSFET
JP2018101668A (ja) * 2016-12-19 2018-06-28 トヨタ自動車株式会社 半導体装置
WO2018140842A2 (en) * 2017-01-30 2018-08-02 Hongjian Wu Insulate gate hybrid mode transistor
TWI685106B (zh) * 2018-03-09 2020-02-11 全宇昕科技股份有限公司 高電壓蕭特基二極體
CN111129163B (zh) * 2019-12-05 2023-06-27 中国电子科技集团公司第十三研究所 肖特基二极管及其制备方法
CN113270471A (zh) * 2020-02-14 2021-08-17 苏州华太电子技术有限公司 Vdmosfet器件的终端结构及其制作方法
US20210351272A1 (en) * 2020-05-07 2021-11-11 Etron Technology, Inc. Transistor structure and related inverter
US11776994B2 (en) 2021-02-16 2023-10-03 Alpha And Omega Semiconductor International Lp SiC MOSFET with reduced channel length and high Vth
CN113644117A (zh) * 2021-08-11 2021-11-12 芜湖启迪半导体有限公司 具有新型深沟槽的碳化硅jbs器件元胞结构及其制备方法
CN115117149B (zh) * 2022-08-23 2022-11-29 深圳芯能半导体技术有限公司 一种基于湿法刻蚀工艺的快恢复二极管及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4754310A (en) * 1980-12-10 1988-06-28 U.S. Philips Corp. High voltage semiconductor device
US6426541B2 (en) * 2000-07-20 2002-07-30 Apd Semiconductor, Inc. Schottky diode having increased forward current with improved reverse bias characteristics and method of fabrication
US6998678B2 (en) * 2001-05-17 2006-02-14 Infineon Technologies Ag Semiconductor arrangement with a MOS-transistor and a parallel Schottky-diode

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204179A (ja) * 1995-01-26 1996-08-09 Fuji Electric Co Ltd 炭化ケイ素トレンチｍｏｓｆｅｔ
FR2807569B1 (fr) * 2000-04-10 2004-08-27 Centre Nat Rech Scient Perfectionnement apportes aux diodes schottky
US6593620B1 (en) * 2000-10-06 2003-07-15 General Semiconductor, Inc. Trench DMOS transistor with embedded trench schottky rectifier
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US6710403B2 (en) * 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
GB0118000D0 (en) * 2001-07-24 2001-09-19 Koninkl Philips Electronics Nv Manufacture of semiconductor devices with schottky barriers
DE10235198B4 (de) * 2001-08-02 2011-08-11 Fuji Electric Systems Co., Ltd. Leistungs-Halbleitergleichrichter mit ringförmigen Gräben
US7061066B2 (en) * 2001-10-17 2006-06-13 Fairchild Semiconductor Corporation Schottky diode using charge balance structure
TW554528B (en) * 2002-02-21 2003-09-21 Delta Electronics Inc Low forward voltage drop Schottky barrier diode and the manufacturing method thereof
US6784505B2 (en) * 2002-05-03 2004-08-31 Fairchild Semiconductor Corporation Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique
JP4221697B2 (ja) * 2002-06-17 2009-02-12 日本電気株式会社 半導体装置
US6855593B2 (en) * 2002-07-11 2005-02-15 International Rectifier Corporation Trench Schottky barrier diode
KR100459872B1 (ko) * 2003-05-07 2004-12-03 삼성전자주식회사 트렌치 게이트를 갖는 매몰 채널형 트랜지스터 및 그제조방법
US6987305B2 (en) * 2003-08-04 2006-01-17 International Rectifier Corporation Integrated FET and schottky device
US6998694B2 (en) * 2003-08-05 2006-02-14 Shye-Lin Wu High switching speed two mask Schottky diode with high field breakdown
US6977208B2 (en) * 2004-01-27 2005-12-20 International Rectifier Corporation Schottky with thick trench bottom and termination oxide and process for manufacture
JP2005229071A (ja) 2004-02-16 2005-08-25 Matsushita Electric Ind Co Ltd ショットキーバリアダイオード
US7078780B2 (en) * 2004-04-19 2006-07-18 Shye-Lin Wu Schottky barrier diode and method of making the same
FR2880193A1 (fr) * 2004-12-23 2006-06-30 St Microelectronics Sa Diode schottky a barriere verticale
US7737522B2 (en) * 2005-02-11 2010-06-15 Alpha & Omega Semiconductor, Ltd. Trench junction barrier controlled Schottky device with top and bottom doped regions for enhancing forward current in a vertical direction

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4754310A (en) * 1980-12-10 1988-06-28 U.S. Philips Corp. High voltage semiconductor device
US6426541B2 (en) * 2000-07-20 2002-07-30 Apd Semiconductor, Inc. Schottky diode having increased forward current with improved reverse bias characteristics and method of fabrication
US6998678B2 (en) * 2001-05-17 2006-02-14 Infineon Technologies Ag Semiconductor arrangement with a MOS-transistor and a parallel Schottky-diode

Also Published As

Publication number Publication date
CN101523583A (zh) 2009-09-02
US7737522B2 (en) 2010-06-15
WO2008039548A2 (en) 2008-04-03
US8445370B2 (en) 2013-05-21
WO2008039548A3 (en) 2008-06-19
TWI352432B (en) 2011-11-11
US20070034901A1 (en) 2007-02-15
US20100258897A1 (en) 2010-10-14
TW200818519A (en) 2008-04-16

Similar Documents

Publication Publication Date Title
CN101523583B (zh) 沟槽结势垒可控肖特基二极管
CN101517752B (zh) 具有浮岛的结势垒肖特基二极管
US8294235B2 (en) Edge termination with improved breakdown voltage
US8933506B2 (en) Diode structures with controlled injection efficiency for fast switching
CN101385147B (zh) 提高肖特基击穿电压(bv)而不影响集成的mosfet-肖特基器件布局
CN102884631B (zh) 用于高电压应用的具有改良的终端结构的沟槽dmos器件
US8872264B2 (en) Semiconductor device having a floating semiconductor zone
CN101800243B (zh) 双栅极结构沟槽型dmos晶体管制造方法
US6396090B1 (en) Trench MOS device and termination structure
US7655975B2 (en) Power trench transistor
US8471332B2 (en) Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout
US20190157384A1 (en) New dual-gate trench igbt with buried floating p-type shield
US8461001B2 (en) Methods for manufacturing trench MOSFET with implanted drift region
US9741851B2 (en) Trench junction barrier controlled Schottky
US20160181391A1 (en) Diode structures with controlled injection efficiency for fast switching
US20210020773A1 (en) Schottky diode integrated into superjunction power mosfets
EP1999792A2 (en) Shielded gate trench(sgt) mosfet cells implemented with a schottky source contact
EP1415334A1 (en) Manufacture of semiconductor devices with schottky barriers
CN110620152A (zh) 沟槽式金属氧化物半导体场效应管
CN101404283A (zh) 集成有肖特基二极管的平面mosfet及其布局方法
EP2650920B1 (en) Trenched semiconductor structure
US8159021B2 (en) Trench MOSFET with double epitaxial structure
CN209766429U (zh) 碳化硅mosfet器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20161028

Address after: 400700 Chongqing city Beibei district and high tech Industrial Park the road No. 5 of 407

Patentee after: Chongqing Wanguo Semiconductor Technology Co., Ltd.

Address before: British Bermuda, Hamilton

Patentee before: Alpha & Omega Semiconductor Inc.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20180213

Address after: The British West Indies Dakaiman Cayman Island KY1-1107 No. 122 Marie street, and the wind floor 709 mailbox

Patentee after: Nations Semiconductor (Cayman) Ltd.

Address before: 400700 Chongqing city Beibei district and high tech Industrial Park the road No. 5 of 407

Patentee before: Chongqing Wanguo Semiconductor Technology Co., Ltd.