TWI345553B - Silicon nitride film with stress control - Google Patents
Silicon nitride film with stress control Download PDFInfo
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- TWI345553B TWI345553B TW094122624A TW94122624A TWI345553B TW I345553 B TWI345553 B TW I345553B TW 094122624 A TW094122624 A TW 094122624A TW 94122624 A TW94122624 A TW 94122624A TW I345553 B TWI345553 B TW I345553B
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- layer
- substrate
- nitride
- etch stop
- tensile stress
- Prior art date
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- 229910052581 Si3N4 Inorganic materials 0.000 title 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title 1
- 150000004767 nitrides Chemical class 0.000 claims description 58
- 239000000758 substrate Substances 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 22
- 230000008021 deposition Effects 0.000 claims description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000003116 impacting effect Effects 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 239000010409 thin film Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 28
- 230000001939 inductive effect Effects 0.000 claims 14
- 125000006850 spacer group Chemical group 0.000 claims 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims 4
- 229910052707 ruthenium Inorganic materials 0.000 claims 4
- 230000035939 shock Effects 0.000 claims 3
- 239000013078 crystal Substances 0.000 claims 2
- 239000010408 film Substances 0.000 claims 2
- 238000010438 heat treatment Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000007789 gas Substances 0.000 claims 1
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 claims 1
- 239000000463 material Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Description
1345553 玖、發明說明: 【發明所屬之技術領域】 本發明之實施例係有關於形成一氮化物蝕刻终止層與 一多層氮化物兹刻停止堆疊層的方法,以在一半導體元件 中機械性地創造出一受控制的應力(拉伸或壓缩應力 (stress)) °
【先前技術】
現今積體電路包括形成於一半導體上的眾多電晶體、 電容、電阻或其他半導體元件。較小尺寸的元件係改善元 件性能與提升可靠度的關鍵。當元件尺寸缩減時,其技術 也相對更為複雜,因此需要各種方法以在每個元件世代替 換過程中維持預期的性能改進,而此主要與微電子元件之 主要半導體材料「矽(silicon,Si)」或「矽基材」有關。元 件性能的其一重要指標係載子遷移率(carrier mobility)。 在深次微米世代的元件中保有高載子遷移率是極為困難的 事情。一達成較佳載子遷移率的可能方法係稍微改變在半 導體製程中作為原料的該半導體材質。過去已知處於張力 (strain)下的矽能激發載子特性,且目前更對此特性作進一 步地研究。在該通道區域中的機械應力會明顯影響 MOS 元件的性能與可靠度(例如請參考文獻:Ito et al, “Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design,” NEC Corporation,IEDM 2000,San Francisco,CA)。並已知一氮 6 1345553 化物蝕刻终止層會造成該矽基材中的拉伸應力。因此,該 領域中的研究人員對於MOS元件製程中的高應力氮化物 蝕刻終止層有著高度的興趣。
可藉著形成一氮化物蝕刻终止層以在一 MOS元件之 通道中產生應力,而獲得拉伸應力’其中「產生應力」可 說明為在下層矽層中的應變(strain)。科學家已藉著在該通 道中引入應變來廣泛研究元件遷移率。其中一種技術係藉 著接觸氣化物钱刻终止層來作為一應力提供來源。為了透 過提高載子遷移率與速度來提升驅動電流的目的,故使用 較薄的氮化物層來達到更高更特定的應力。 【發明内容】 本發明之一態樣在於一包含一多層氮化物堆疊層的組 件’該多層氮化物堆疊層具有複數層氮化物蝕刻終止層, 且該些氣化物蝕刻終止層係相互形成於彼此頂面上每一 氮化物钱刻終止層係利用薄膜形成製程所形成。
本發明之另一態樣在於一種製造一多層氮化物堆疊層 的方法’該方法包括放置一基材至一單晶圓沉積室中並 在執行沉積步驟前一刻,先熱衝擊該基材。一第一氮化物 钱刻終止層係沉積於該基材上。一第二氮化物蝕刻终止層 係沉積於該第一氮化物姓刻终止層上。 本發明之另一態樣在於一種製造一氮化物蝕刻終止層 的方法’該方法包括放置一基材至一單晶圓沉積室中,並 7
Claims (1)
- Γ345553 色 拾、申請專利範圍: 1. 一種多層氮化物堆疊層,其包括: 數層氮化物蝕刻终止層,相互形成於彼此的頂面上, 該數層氮化物蝕刻終止層包括一第一氮化物蝕刻終止層與 一第二氮化物蝕刻终止層,每一氮化蝕刻終止層係使用一 薄膜形成製程所形成,其中形成該多層氮化物堆疊層包括 在沉積該第一氮化物蝕刻終止層之前一刻熱衝擊一基材。2.如申請專利範圍第1項所述之多層氮化物堆疊層, 其中該等氮化物蝕刻終止層之每一層的厚度實質相同於彼 此。 3.如申請專利範圍第1項所述之多層氮化物堆疊層, 其中該多層氮化物堆疊層形成於一基材上,且該多層氮化 物堆疊層引發一拉伸應力於該基材。4.如申請專利範圍第1項所述之多層氮化物堆疊層, 其中該多層氮化物堆疊層係一形成於一半導體元件上的共 形薄膜。 5 .如申請專利範圍第1項所述之多層氮化物堆疊層, 其中該多層氮化物堆疊層為一形成於一半導體元件上之共 形薄膜與一半導體元件之一間隙壁(spacer wall)的至少其 46 1345553中一者。 6. —種半導體元件,其包括: 一基材,其具有一源極區域與一汲極區域以及 於該源極區域與該汲極區域間的通道區域; 一閘極堆疊層,形成於該基材上;以及 一拉伸應力引發層,形成於該基材與該閘極 上,該拉伸應力引發層包含一氮化物堆疊層,該氮 疊層具有複數層相互形成於彼此的頂面上之氮化物 複數層氣化物層包括一第一氮化物層與一第二氮化 其中形成該拉伸應力引發層之步驟包括在沉積該第 物層之前一刻熱衝擊該基材。 7.如申請專利範圍第6項所述之半導體元件, 等氮化物層中之每一層的厚度實質相同於彼此。 8. 如申請專利範圍第6項所述之半導體元件, 氮化物堆疊層於該通道區域引發一拉伸應力。 9. 如申請專利範圍第8項所述之半導體元件, 拉伸應力約150-450百萬巴斯卡(mega Pascal)。 1 0 ·如申請專利範圍第6項所述之半導體元件 一形成 堆疊層 化物堆 層,該 物層, 一氮化 其中該 其中該 其中該 ,更包 47 1345553 括一間隙壁,位於該閘極堆疊層的每一側邊,其中每一間 隙壁係由氮化物所構成。 11.如申請專利範圍第6項所述之半導體元件,其中 每一間隙壁係由具有控制的低内應力之氮化物所構成。12.如申請專利範圍第6項所述之半導體元件,更包 括一間隙壁位於該閘極堆疊層的每一側邊,其中每一間隙 壁係由另一氮化物堆疊層所構成,該另一氮化物堆疊層具 有複數層相互形成於彼此的頂面上之氮化物層。 1 3 .如申請專利範圍第6項所述之半導體元件,其中 該氮化物堆疊層之總厚度範圍約介於200人至1 000A之間。14. 一種製造一半導體元件的方法,該方法包括: 提供一基材; 於該基材上形成一半導體元件; 形成一拉伸應力引發層於該基材上,該拉伸應力引發 層包含一氣化物堆疊層,該氮化物堆疊層具有複數層相互 形成於彼此的頂面上之氮化物層,該複數層氮化物層包括 一第一氮化物層與一第二氮化物層,其中形成該拉伸應力 引發層之步驟包括在沉積該第一氮化物層之前一刻熱衝擊 該基材。 48 1345553 15.如申請專利範圍第14項所述之方法,其中該半導 體元件具有一源極區域與一汲極區域以及一形成於該兩者 之間的閘極堆疊層,且其中該拉伸應力引發層係形成於該 源極區域、該汲極區域與該閘極堆疊層上。16.如申請專利範圍第15項所述之方法,其更包括: 在該基材上形成該拉伸應力引發層前,先形成一矽化 物層於該半導體元件上。 17.如申請專利範圍第15項所述之方法,其更包括: 於該源極區域、該汲極區域與該閘極堆疊層產生接觸。 18_如申請專利範圍第15項所述之方法,其更包括: 該拉伸應力引發層引導拉伸應力至該基材中的一通道19. 如_請專利範圍第15項所述之方法,其中該基材 係一含矽基材、一單晶矽基材、一矽鍺基材與一絕緣層上 覆矽基材中的其中一者。 20. 如申請專利範圍第15項所述之方法,其中該拉伸 應力引發層係將一範圍約介於150至450百萬巴斯卡之拉 49 1345553伸應力引入該基材中。 21.如申請專利範圍第15項所述之方法,其中 應力引發層係於一單晶圓沉積室中所形成。 22.如申請專利範圍第15項所述之方法,其中 材於一沉積室内經熱衝擊後,立即於該沉積室中形 伸應力引發層。 23. —種製造一半導體元件的方法,該方法包 放置一基材於一單晶圓沉積室中,並在執行沉 前一刻熱衝擊該基材;以及 沉積一第一氮化物蝕刻終止層於該基材上,該 化物蝕刻終止層會於該基材中引發一拉伸應力。 2 4.如令請專利範圍第2 3項所述之方法,其中 該基材之步驟包括使該基材之溫度維持在實質上低 要的沉積溫度,並且在執行該沉積步驟前一刻,以 的沉積溫度來熱衝擊該基材。 25.如申請專利範圍第23項所述之方法,其中 該基材之步驟包括:在該沉積步驟之前,使該基材 晶圓沉積室之一加熱器上方保持一段距離,並於該 該拉伸 在該基 成該拉 積步驟 第一氣 熱衝擊 於一想 該想要 熱衝擊 於該單 沉積步 50 1345553 驟前一刻,允許該基材接觸該加熱器,該加熱器係經設定, 以將該基材加熱至一想要的沉積溫度。 26. 如申請專利範圍第23項所述之方法,其中該基材 具有一源極區域與一汲極區域以及一形成於該兩者上的閘 極堆疊層,且其中該拉伸應力引發層係形成於該源極區 域、該汲極區域與該閘極堆疊層上。27. 如申請專利範圍第23項所述之方法,更包括: 在沉積該第一氮化物蝕刻終止層之前,先形成一矽化 物層於該源極區域、該汲極區域與該閘極堆疊層上。28.如申請專利範圍第23項所述之方法,更包括: 沉積一第二氮化物蝕刻終止層於該第一氮化物蝕刻終 止層上,該第二氮化物蝕刻終止層與該第一氮化物蝕刻終 止層係形成一氮化物堆疊層,且該氮化物堆疊層會於該基 材中引發該拉伸應力。 29.如申請專利範圍第28項所述之方法,其中沉積一 第二氮化物蝕刻終止層之步驟更包括: 將具有該第一氮化物蝕刻終止層沉積於其上的該基材 自該單晶圓沉積室中移除;以及 在沉積該第二氣化物钮刻終止層之前一刻,熱衝擊該 51 1345553基材。 30.如申請專利範圍第29項所述之方法,其中熱 該基材之步驟包括:使該基材之溫度維持在實質上低 想要沉積溫度,並在執行該沉積步驟前一刻,以該想 沉積溫度來熱衝擊該基材。 31.如申請專利範圍第29項所述之方法,其中熱 該基材之步驟包括:在該沉積步驟前,使該基材於該 圓沉積室之一加熱器上方保持一段距離,並於該沉積 前一刻,允許該基材接觸該加熱器,該加熱器係經設 以將該基材加熱至一想要的沉積溫度。 32.如申請專利範圍第29項所述之方法,其中該 具有一源極區域與一汲極區域以及一形成於該兩者上 極堆疊層,且其中該拉伸應力引發層係形成於該源 域、該汲極區域與該閘極堆疊層上。 33.如申請專利範圍第32項所述之方法,更包本 在沉積該第一氛化物姓刻終止層之.前,先形成一 物層於該源極區域、該汲極區域與該閘極堆疊層上。 衝擊 於一 要的 衝擊 單晶 步驟 定, 基材 的閘 極區 矽化 52
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KR100385857B1 (ko) * | 2000-12-27 | 2003-06-02 | 한국전자통신연구원 | SiGe MODFET 소자 제조방법 |
US6500772B2 (en) * | 2001-01-08 | 2002-12-31 | International Business Machines Corporation | Methods and materials for depositing films on semiconductor substrates |
JP4771607B2 (ja) * | 2001-03-30 | 2011-09-14 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
JP2003060201A (ja) * | 2001-08-13 | 2003-02-28 | Hitachi Ltd | 半導体装置の製造方法 |
US6534807B2 (en) * | 2001-08-13 | 2003-03-18 | International Business Machines Corporation | Local interconnect junction on insulator (JOI) structure |
JP2003060076A (ja) * | 2001-08-21 | 2003-02-28 | Nec Corp | 半導体装置及びその製造方法 |
US6660598B2 (en) * | 2002-02-26 | 2003-12-09 | International Business Machines Corporation | Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region |
KR100953332B1 (ko) * | 2002-12-31 | 2010-04-20 | 동부일렉트로닉스 주식회사 | 반도체 장치의 제조 방법 |
JP4653949B2 (ja) * | 2003-12-10 | 2011-03-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
KR100652791B1 (ko) * | 2003-12-18 | 2006-11-30 | 주식회사 하이닉스반도체 | 반도체소자 제조 방법 |
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- 2005-07-05 KR KR1020087027671A patent/KR101022898B1/ko not_active IP Right Cessation
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US20060009041A1 (en) | 2006-01-12 |
JP2008506262A (ja) | 2008-02-28 |
KR20080112370A (ko) | 2008-12-24 |
KR101022898B1 (ko) | 2011-03-16 |
WO2006014471A1 (en) | 2006-02-09 |
US7488690B2 (en) | 2009-02-10 |
CN1989622A (zh) | 2007-06-27 |
TW200604093A (en) | 2006-02-01 |
CN100536161C (zh) | 2009-09-02 |
KR20070029829A (ko) | 2007-03-14 |
KR100903891B1 (ko) | 2009-06-19 |
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