WO2013037166A1 - 石墨烯纳米带的制造方法、mosfet及其制造方法 - Google Patents

石墨烯纳米带的制造方法、mosfet及其制造方法 Download PDF

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WO2013037166A1
WO2013037166A1 PCT/CN2011/082418 CN2011082418W WO2013037166A1 WO 2013037166 A1 WO2013037166 A1 WO 2013037166A1 CN 2011082418 W CN2011082418 W CN 2011082418W WO 2013037166 A1 WO2013037166 A1 WO 2013037166A1
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layer
graphene
forming
mosfet
oxide protective
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French (fr)
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朱慧珑
梁擎擎
骆志炯
尹海洲
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中国科学院微电子研究所
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Priority to US13/510,390 priority Critical patent/US9087691B2/en
Publication of WO2013037166A1 publication Critical patent/WO2013037166A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the invention relates to a method for manufacturing graphene nanoribbons, metal oxide semiconductor field effect transistor
  • Graphene is a single-layer two-dimensional crystal in which carbon atoms are arranged in SP 2 orbital hybrids in accordance with a honeycomb crystal lattice.
  • Graphene is not limited to a single layer of graphite, but may contain two or more layers of graphite as long as it exhibits characteristics of a two-dimensional crystal.
  • the width of the graphene nano-ribbon is on the order of nanometers, because the size effect can obtain a finite band gap, thereby exhibiting the characteristics of the semiconductor.
  • a semiconductor device using graphene in which a semiconductor graphene is appropriately doped to form a channel region and a source/drain region formed using metal graphene is disclosed in U.S. Patent Application Publication No. US2010/0102292 A1 to the disclosure of U.S. Pat. And the gate.
  • the above known semiconductor device uses a single graphene nanoribbon to form a channel, and thus can only carry a limited channel on current.
  • known methods for fabricating graphene nanoribbons include pyroforming a graphene layer and a patterning step for the graphene layer, or a step of stripping and layer transferring from a thicker graphene layer to obtain a thickness And the width is a nanometer-scale graphene.
  • This method of manufacturing graphene nanoribbons is costly to produce, and process repeatability is poor due to difficulty in accurately controlling the dimensions in two dimensions of graphene nanoribbons. Summary of the invention
  • a method of fabricating a graphene nanoribbon comprising:
  • Graphene nanoribbons are grown on the side surface of the seed layer.
  • a method of fabricating a MOSFET comprising:
  • a MOSFET comprising: an insulating substrate; an oxide protective layer on the insulating substrate; at least one graphene nanoribbon embedded in the oxide protective layer, wherein the oxide protective layer a surface of the at least one graphene nanoribbon exposed on a side surface; a channel region formed in each of the at least one graphene nanoribbon; formed in each of the at least one graphene nanoribbon a source/drain region, wherein the channel region is between the source/drain regions; a gate dielectric layer on the at least one graphene nanoribbon; a gate conductor layer on the gate dielectric layer; and an oxide protective layer Source/drain contacts on the side surface in contact with the source/drain regions.
  • the thickness of the graphene nanoribbons can be controlled to be a single layer, two or more layers of graphite by controlling the growth conditions.
  • the width of the graphene nanoribbons depends on the thickness of the seed layer.
  • the method of the present invention utilizes the side surface of the metal layer, and it is possible to form a graphene nanoribbon of a desired width by controlling the thickness of the metal layer without using an additional patterning step or layer transfer step, thereby reducing the production cost.
  • the method of the present invention can precisely control the size of graphene nanoribbons in two dimensions (i.e., thickness and width).
  • DRAWINGS 1 to 3 schematically illustrate cross-sectional views of various steps of a method of fabricating a graphene nanoribbon according to the present invention
  • FIGS. 4 to 10 are schematic views showing a plan view and a cross-sectional view of respective steps of a method of fabricating a MOSFET according to the present invention, in which a cut-away position of a cross-sectional view is shown by a line A-A' in a plan view;
  • Fig. 11 schematically shows a perspective view of a MOSFET according to the present invention. detailed description
  • semiconductor structure refers to a general term for an entire semiconductor structure formed in various steps of fabricating a semiconductor device, including a semiconductor substrate and all layers or regions that have been formed on the semiconductor substrate.
  • an oxide base layer 101 is formed on the semiconductor substrate 100 by thermal oxidation or sputtering, on which seed layers 102-1, 102-2 and a growth inhibiting layer 103- are alternately stacked. 1, 103-2. Between the steps of forming the seed layers 102-1, 102-2 and the steps of forming the subsequent growth inhibiting layers 103-1, 103-2, the seed layers 102-1, 102-2 are thermally annealed for recrystallization or Promote grain growth.
  • the combination of the semiconductor substrate 100 and the oxide underlayer 101 may be replaced by an insulating substrate such as a glass substrate or a barium titanate substrate.
  • the seed layers 102-1, 102-2 are formed by a conventional deposition process, such as physical vapor deposition (PVD), including electron beam evaporation, molecular beam epitaxy, sputtering, or chemical vapor deposition (CVD), including atomic layer deposition ( ALD), metal organic chemical vapor deposition (M0CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), and the like.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • M0CVD metal organic chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • the foregoing conventional deposition process is not limited to the known art, and includes a deposition process developed in the future suitable for forming a target layer.
  • the seed layers 102-1, 102-2 are formed by electron beam evaporation, and the growth suppression layers 103-1, 103-2 are formed by CVD.
  • the seed layers 102-1, 102-2 are nucleation layers of graphene grown, the material of which may be selected from transition metals such as Ni, Co, Pt, Ir, Ru.
  • the thickness of the seed layers 102-1, 102-2 will determine the width of the grown graphene nanoribbons, for example about 5-20 nm.
  • the growth inhibiting layers 103-1, 103-2 suppress the growth of graphene thereon, and the material thereof may be, for example, a nitride, and the thickness of the growth inhibiting layers 103-1, 103-2 may be arbitrary.
  • the growth inhibiting layers 103-1, 103-2 cover the surfaces of the seed layers 102-1, 102-2 such that graphene grows only on the side surfaces of the seed layers 102-1, 102-2.
  • the seed layers 102-1, 102-2 and the growth inhibiting layers 103-1, 103-2 form a superlattice to obtain reduced crystal defects and uniform layer thickness.
  • the number of seed layers shown in the figure is two layers, a larger number of seed layers can be formed according to actual needs.
  • the number of seed layers stacked in the vertical direction is the same as the number of graphene nanoribbons to be stacked in the vertical direction to be formed. According to the design requirements of the MOSFET, the number of graphene channels stacked in the vertical direction can be determined, and the number of seed layers stacked in the vertical direction can be determined.
  • the stack of the seed layers 102-1, 102-2 and the growth inhibiting layers 103-1, 103-2 is patterned to form a plurality of stacks spaced apart from each other and extending in a direction perpendicular to the plane of the paper in the drawing.
  • Layer strips as shown in Figure 2.
  • Each of the laminated strips includes alternately stacked seed layers 102-1, 102-2 and growth inhibiting layers 103-1, 103-2, and at least the side surfaces of the seed layers 102-1, 102-2 are exposed.
  • the patterning may include the steps of: forming a patterned photoresist mask on the growth inhibiting layer 103-2 by a photolithography process including exposure and development; by anisotropic dry etching, such as ion milling Plasma etching, reactive ion etching, laser ablation, sequentially removing the growth inhibiting layer 103-2, the seed layer 102-2, the growth inhibiting layer 103-1, and the seed layer 102-1 from top to bottom, and the etching step is stopped in oxidation.
  • the top of the substrate 101; the photoresist mask is removed by dissolving or ashing in a solvent.
  • Thermal annealing is performed after patterning to repair damage of the side surfaces of the seed layers 102-1, 102-2.
  • Graphene nanoribbons 104 are grown thereon as shown in FIG.
  • the graphene nanoribbons selectively grow only on the exposed side surfaces of the seed layer.
  • An oxide protective layer 105 is formed over the entire semiconductor structure by the conventional deposition process described above, and the oxide protective layer 105 fills the opening between the laminated strips. Next, the growth at the top of the laminated strip is suppressed.
  • the layer 103-2 serves as a stop layer, and the oxide protective layer 105 is subjected to chemical mechanical planarization (CMP) as shown in FIG.
  • the graphene nanoribbons 104 are embedded in the oxide protective layer 105.
  • the oxide protective layer 105 provides mechanical support for the graphene nanoribbons 104 and acts as a protective layer for the graphene nanoribbons 104 in subsequent processing.
  • the oxide protective layer 105 has a complementary shape to the laminated strip shown in Fig. 2, i.e., still forms a strip shape extending in a direction perpendicular to the plane of the paper in the drawing.
  • the growth inhibiting layer 103-2, the seed layer 102-2, the growth inhibiting layer 103-1, and the seed layer 102-1 are sequentially removed from top to bottom, thereby completely removing the laminated strip, such as Figures 5a and 5b.
  • the patterning step may employ wet etching to selectively etch the growth inhibiting layer 103-2, the seed layer 102-2, and the growth inhibiting layer 103-1 with respect to the oxide protective layer 105 and the oxide underlayer 101.
  • the seed layer 102-1 thereby eliminating the need to form a photoresist mask, further simplifying the process.
  • the patterning step leaves the upright oxide protective layer 105 and the graphene nanoribbons 104 embedded therein, and the graphene nanoribbons 104 are exposed on the side surface of the oxide protective layer 105.
  • the graphene nanoribbons 104 are doped with a portion serving as a channel.
  • a method of doping graphene nanoribbons 104 is described in, for example, U.S. Patent Application Serial No. US 2010/0102292 A1.
  • a conformal gate dielectric layer 106 and a diffusion barrier layer 107, and a covered gate conductor layer 108 are formed on the entire surface of the semiconductor structure by the above-described conventional deposition process, as shown in Figs. 6a and 6b.
  • the gate dielectric layer 106 may be formed by ALD, and the diffusion barrier layer 107 and the gate conductor layer 108 may be formed by sputtering.
  • the gate dielectric layer 106 can be composed of an oxide, an oxynitride, a high K material, or a combination thereof.
  • the diffusion barrier layer 107 may be composed of a stable metal such as Ti, Pt, Au or a laminate thereof, and the gate conductor layer 108 may be composed of a metal layer, a doped polysilicon layer, or a laminate including a metal layer and a doped polysilicon layer.
  • the material of the gate dielectric layer 106 is A1 2 0 3
  • the material of the diffusion barrier layer is Ti/Pt
  • the material of the gate conductor layer 108 is polysilicon doped in situ.
  • the gate dielectric layer 106 contacts the graphene nanoribbon on the side surface of the oxide protective layer 105.
  • a diffusion barrier layer 107 is between the gate dielectric layer and the subsequently formed gate conductor layer 108. It should be noted that the diffusion barrier layer 107 is an optional layer for preventing diffusion of material of the gate conductor layer 108 into the graphene ribbon 104.
  • the gate conductor layer 108 fills the recess between the oxide protective layers 105, and an additional CMP is used to planarize the gate conductor layer 108 to obtain a planar surface of the semiconductor structure.
  • a photoresist mask 109 for defining a gate is formed on the surface of the semiconductor structure, as shown in FIG. 7a. And 7b.
  • the shape of the photoresist mask 109 is a strip extending in the lateral direction of the paper surface.
  • the exposed portion of the gate conductor layer 108 is removed by an anisotropic dry etching such as ion milling, plasma etching, reactive ion etching, laser ablation using a photoresist mask, and then etching is performed therethrough.
  • anisotropic dry etching such as ion milling, plasma etching, reactive ion etching, laser ablation using a photoresist mask, and then etching is performed therethrough.
  • the wet etching of the solution solution further removes the exposed portions of the diffusion barrier layer 107 and the gate dielectric layer 106, as shown in Figures 8a and 8b.
  • the gate conductor layer 108 forms a strip extending in the lateral direction of the paper surface in conformity with the photoresist mask 109, the direction in which the gate conductor layer 108 extends and the oxide protective layer 105 The extending direction is vertical, and the oxide protective layer 105 and the top surface of the oxide underlayer 101 are exposed at a portion where the photoresist mask 109 is not blocked, and the side surface of the oxide protective layer 105 is exposed and the graphene nanoparticle embedded therein Belt 104.
  • the photoresist mask 109 is removed by dissolving or ashing in a solvent.
  • a conformal nitride layer is formed over the entire surface of the semiconductor structure, and then reactive ion etching is performed, leaving only the nitride layer on the sidewalls of the gate conductor layer 108 to form sidewall spacers. 110, as shown in Figures 9a and 9b.
  • the graphene nanoribbons 104 are doped with portions serving as source/drain regions.
  • a method of doping graphene nanoribbons 104 is described in, for example, U.S. Patent Application Serial No. US 2010/0102292 A1.
  • a covered metal layer such as Ti is formed on the entire surface of the semiconductor structure by the above-described conventional deposition process.
  • the metal layer is filled with at least a groove between the oxide protective layers 105.
  • the metal layer is then etched back leaving only portions of the metal layer outside the recess between the oxide protective layers 105 to form source/drain contacts 111, as shown in Figures 10a and 10b.
  • the source/drain contact 111 is in contact with the graphene nanoribbons 104 embedded in the oxide protective layer 105 and exposed on the side surface of the oxide protective layer 105.
  • an interlayer dielectric layer may be further formed after the step of forming the source/drain contact 111, and conductive paths reaching the source/drain contact 111 and the gate conductor layer 108 are formed in the interlayer dielectric layer, thereby forming Complete MOSFET.
  • Fig. 16 schematically shows a perspective view of a MOSFET according to the present invention, in which an interlayer dielectric layer and a conductive via are not shown.
  • the strip 104 is embedded in the oxide protective layer 105, and a source is formed in each of the graphene nanoribbons 104/
  • the drain region and the channel between the source/drain regions, the source/drain contact 111 is in contact with the source/drain regions of the graphene nanoribbons 104 on the side surface of the oxide protective layer 105, and the gate conductor layer 108 is located in the graphite.
  • Above the channel of the olefinic nanoribbons 104, and the gate dielectric layer 106 is between the gate conductor layer

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Abstract

一种石墨烯纳米带（104）的制造方法，以及MOSFET及其制造方法。该MOSFET包括：绝缘衬底（101）；位于绝缘衬底（101）上的氧化物保护层（105）；嵌入氧化物保护层（105）中的至少一条石墨烯纳米带（104），在氧化物保护层（105）的侧表面上暴露所述至少一条石墨烯纳米带（104）的表面；在所述至少一条石墨烯纳米带（104）的每一个中形成的沟道区；在所述至少一条石墨烯纳米带的每一个中形成的源/漏区，其中沟道区位于源/漏区之间；位于所述至少一条石墨烯纳米带上的栅介质层（106）；位于栅介质层上的栅极导体层（108）；以及在氧化物保护层（105）的侧表面上与源漏区相接触的源漏接触（111）。该方法可以降低石墨烯纳米带和MOSFET的生产成本，并且可以改善MOSFET的性能。

Description

石墨烯纳米带的制造方法、 M0SFET及其制造方法 技术领域
本发明涉及一种石墨烯纳米带的制造方法、 金属氧化物半导体场效应晶体管
(M0SFET)及其制造方法， 具体地，涉及一种使用石墨烯（graphene )沟道的 M0SFET 及其制造方法。 背景技术
石墨烯是碳原子以 SP2轨道杂化按照蜂巢晶格 (honeycomb crystal lattice)排 列形成的单层二维晶体。 石墨烯不限于单层石墨， 而是可以包含两层或更多层的石 墨， 只要其表现出二维晶体的特性即可。
近年对使用石墨烯的半导体器件进行了研究。 石墨烯纳米带 （graphene nano-ribbon) 的宽度是纳米量级， 因为尺寸效应可以获得有限的带隙， 从而表现出 半导体的特性。
Hidefumi Hiura等人的美国专利申请 No. US2010/0102292A1 公开了一种使用 石墨烯的半导体器件， 其中对半导体石墨烯进行适当的掺杂以形成沟道区， 并利用 金属石墨烯形成源 /漏区和栅极。
然而， 上述已知的半导体器件使用单条的石墨烯纳米带形成沟道， 因而只能承 载有限的沟道导通电流。
而且， 已知的用于制造石墨烯纳米带的方法包括热解形成石墨烯层及对石墨烯 层的图案化步骤， 或者包括从较厚的石墨烯层剥离及层转移的步骤， 以获得厚度和 宽度均是纳米量级的石墨烯。 这种制造石墨烯纳米带的方法生产成本高， 并且由于 难以准确控制石墨烯纳米带两个维度上的尺寸， 工艺可重复性差。 发明内容
本发明的目的是提供一种新的石墨烯纳米带的制造方法以及包含石墨烯纳米带 的 M0SFET, 该 M0SFET具有改进的性能和降低的生产成本。
根据本发明的一方面， 提供一种制造石墨烯纳米带的方法， 包括：
在绝缘衬底上形成包括籽层和生长抑制层的叠层；
对叠层进行图案化以形成至少一个叠层条带， 所述至少一个叠层条带暴露籽层 的侧表面； 以及
在籽层的侧表面上生长石墨烯纳米带。
根据本发明的另一方面， 提供一种制造 M0SFET的方法， 包括：
按照上述的方法制造石墨烯纳米带；
在所述至少一个叠层条带之间形成氧化物保护层， 使得石墨烯纳米带嵌入氧化 物保护层中；
去除叠层条带以形成凹槽， 并且在氧化物保护层的侧表面上暴露石墨烯纳米带 的表面；
在石墨烯纳米带上形成堆叠的栅介质层和栅极导体层；
在栅极导体层的两侧形成侧墙；
在部分石墨烯纳米带中形成源 /漏区； 以及
利用金属层填充氧化物保护层之间的凹槽， 以形成与源 /漏区接触的源 /漏接触。 根据本发明的又一方面， 提供一种 M0SFET, 包括： 绝缘衬底； 位于绝缘衬底上 的氧化物保护层； 嵌入氧化物保护层中的至少一条石墨烯纳米带， 其中在氧化物保 护层的侧表面上暴露所述至少一条石墨烯纳米带的表面； 在所述至少一条石墨烯纳 米带的每一个中形成的沟道区；在所述至少一条石墨烯纳米带的每一个中形成的源 / 漏区，其中沟道区位于源 /漏区之间；位于所述至少一条石墨烯纳米带上的栅介质层； 位于栅介质层上的栅极导体层； 以及在氧化物保护层的侧表面上与源 /漏区相接触的 源 /漏接触。
在本发明的方法中， 通过控制生长条件， 石墨烯纳米带的厚度可以控制为单层、 两层或更多层石墨。 另一方面， 石墨烯纳米带的宽度取决于籽层的厚度。 本发明的 方法利用金属层的侧表面， 不必采用额外的图案化步骤或层转移步骤， 就可以通过 控制金属层的厚度而形成期望宽度的石墨烯纳米带， 从而降低了生产成本。
本发明的方法可以精确地控制石墨烯纳米带在两个维度 （即厚度和宽度） 上的 尺寸。
在本发明的 M0SFET中， 不仅包括上述的有益效果， 而且由于一个 M0SFET可以 包括多条石墨烯纳米带， 因此可以通过设置多条石墨烯沟道来提高沟道导通电流， 从而改善器件的性能。 附图说明 图 1至 3示意性地示出了根据本发明的制造石墨烯纳米带方法的各个步骤的截 面图；
图 4至 10示意地示出了根据本发明的制造 M0SFET的方法的各个步骤的俯视图 和截面图， 其中在俯视图中以线 A-A' 示出了截面图的截取位置；
图 11示意性地示出了根据本发明的 M0SFET的透视图。 具体实施方式
以下将参照附图更详细地描述本发明。 在各个附图中， 相同的元件采用类似的 附图标记来表示。 为了清楚起见， 附图中的各个部分没有按比例绘制。
在下文中描述了本发明的许多特定的细节， 例如器件的结构、 材料、 尺寸、 处 理工艺和技术， 以便更清楚地理解本发明。 但正如本领域的技术人员能够理解的那 样， 可以不按照这些特定的细节来实现本发明。 除非在下文中特别指出， 半导体器 件中的各个部分可以由本领域的技术人员公知的材料构成。
在本申请中， 术语 "半导体结构"指在制造半导体器件的各个步骤中形成的整 个半导体结构的统称，包括半导体衬底和在半导体衬底上已经形成的所有层或区域。
根据本发明的优选实施例， 按照图 1至 3的顺序执行制造石墨烯纳米带的以下 步骤。
参见图 1，在半导体衬底 100上采用热氧化或溅射形成氧化物底层（base layer) 101， 在其上交替堆叠籽层 102-1、 102-2和生长抑制层 （blocking layer) 103-1、 103-2。 在形成籽层 102-1、 102-2的步骤和形成后续的生长抑制层 103-1、 103-2的 步骤之间， 对籽层 102-1、 102-2进行热退火以进行再结晶或促进晶粒生长。
半导体衬底 100和氧化物底层 101的组合可以由绝缘衬底代替，例如玻璃衬底、 钛酸锶衬底。
采用常规的沉积工艺形成籽层 102-1、 102-2， 如物理气相沉积 （PVD)， 包括电 子束蒸发、分子束外延、溅射，或者化学气相沉积（CVD)等，包括原子层沉积（ALD)、 金属有机化学气相沉积 （M0CVD)、 等离子增强化学气相沉积 （PECVD)、 低压化学气 相沉积（LPCVD)等。 前述常规的沉积工艺不限于已知的技术， 还包括未来开发的适 合于形成目标层的沉积工艺。
优选地， 采用电子束蒸发形成籽层 102-1、 102-2， 采用 CVD 形成生长抑制层 103—1、 103—2。 籽层 102-1、 102-2是生长石墨烯的形核层， 其材料可以选自过渡金属， 如 Ni、 Co、 Pt、 Ir、 Ru。 籽层 102-1、 102-2的厚度将决定生长的石墨烯纳米带的宽度， 例 如约为 5-20nm。 生长抑制层 103-1、 103-2抑制石墨烯在其上的生长， 其材料例如 可以是氮化物， 生长抑制层 103-1、 103-2的厚度可以是任意的。生长抑制层 103-1、 103-2覆盖籽层 102-1、 102-2的表面， 使得石墨烯仅仅在籽层 102-1、 102-2的侧 表面上生长。
优选地， 籽层 102-1、 102-2和生长抑制层 103-1、 103-2形成超晶格， 以获得 减少的晶体缺陷和均匀的层厚度。
尽管在图中示出的籽层的数量为两层， 但可以根据实际需要形成更多数量的籽 层。 在垂直方向上堆叠的籽层的数量与将形成的在垂直方向上堆叠的石墨烯纳米带 的数量相同。根据 M0SFET的设计要求， 可以确定在垂直方向上堆叠的石墨烯沟道的 数量， 进而可以确定在垂直方向上堆叠的籽层的数量。
然后， 对籽层 102-1、 102-2和生长抑制层 103-1、 103-2的叠层进行图案化， 形成多个彼此隔开并且沿着垂直于图中纸面的方向延伸的叠层条带， 如图 2所示。 每一个叠层条带包括交替堆叠的籽层 102-1、 102-2和生长抑制层 103-1、 103-2， 并且至少暴露籽层 102-1、 102-2的侧表面。
该图案化可以包括以下步骤： 通过包含曝光和显影的光刻工艺， 在生长抑制层 103-2上形成含有图案的光抗蚀剂掩模； 通过各向异性的干法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧蚀， 从上至下依次去除生长抑制层 103-2、 籽 层 102-2、 生长抑制层 103-1、 籽层 102-1， 该蚀刻步骤停止在氧化物底层 101的顶 部； 通过在溶剂中溶解或灰化去除光抗蚀剂掩模。
在图案化之后进行热退火以修复籽层 102-1、 102-2的侧表面的损伤。
然后，例如在 900-1000°C的温度下， 向反应室中提供高度稀释的碳氢化合物流， 并保持反应室压强为环境气压， 采用 CVD在籽层 102-1、 102-2的侧表面上生长石墨 烯纳米带 104， 如图 3所示。
石墨烯纳米带仅仅在籽层的暴露的侧表面上选择性地生长。
在按照图 1至 3所示的步骤形成石墨烯纳米带之后，根据本发明的优选实施例， 按照图 4至 10的顺序执行制造 M0SFET的以下步骤。
通过上述常规的沉积工艺， 在整个半导体结构上形成氧化物保护层 105， 该氧 化物保护层 105填充了叠层条带之间的开口。 接着， 以位于叠层条带顶部的生长抑 制层 103-2作为停止层， 对氧化物保护层 105进行化学机械平面化 （CMP)， 如图 4 所示。
石墨烯纳米带 104嵌入在氧化物保护层 105中。 氧化物保护层 105为石墨烯纳 米带 104提供了机械支撑， 并且在随后的处理中作为石墨烯纳米带 104的保护层。 氧化物保护层 105与在图 2所示的叠层条带是互补的形状， 也即仍然形成沿着垂直 于图中纸面的方向延伸的条带形状。
然后， 采用上述的图案化步骤， 从上至下依次去除生长抑制层 103-2、 籽层 102-2、 生长抑制层 103-1、 籽层 102-1， 从而完全去除叠层条带， 如图 5a和 5b所 示。
代替地， 该图案化步骤可以采用湿法刻蚀， 相对于氧化物保护层 105和氧化物 底层 101， 选择性地蚀刻生长抑制层 103-2、 籽层 102-2、 生长抑制层 103-1、 籽层 102-1， 从而不必形成光抗蚀剂掩模， 进一步简化工艺。
该图案化步骤留下直立的氧化物保护层 105及嵌入其中的石墨烯纳米带 104， 并且石墨烯纳米带 104在氧化物保护层 105的侧表面上暴露。 优选地， 在去除叠层 条带的步骤之后， 对石墨烯纳米带 104将用作沟道的部分进行掺杂。 例如， 在美国 专利申请 No. US2010/0102292A1中描述了对石墨烯纳米带 104掺杂的方法。
然后， 采用上述常规的沉积工艺在半导体结构的整个表面上形成共形的栅介质 层 106和扩散阻挡层 107， 以及覆盖的栅极导体层 108，如图 6a和 6b所示。优选地， 可以采用 ALD形成栅介质层 106， 采用溅射形成扩散阻挡层 107和栅极导体层 108。
栅介质层 106可以由氧化物、 氧氮化物、 高 K材料或其组合组成。 扩散阻挡层 107可以由稳定的金属例如 Ti、 Pt、 Au或其叠层组成， 栅极导体层 108可以由金属 层、 掺杂多晶硅层、 或包括金属层和掺杂多晶硅层的叠层组成。 优选地， 栅介质层 106的材料是 A1203， 扩散阻挡层的材料是 Ti/Pt， 栅极导体层 108的材料是原位掺 杂的多晶硅。
栅介质层 106在氧化物保护层 105的侧表面上接触石墨烯纳米带。 扩散阻挡层 107位于栅介质层和随后形成的栅极导体层 108之间。 应当注意， 扩散阻挡层 107 是可选的层， 用于阻止栅极导体层 108的材料扩散进入石墨烯条带 104中。 栅极导 体层 108填充了氧化物保护层 105之间的凹槽，采用额外的 CMP平整栅极导体层 108 以获得半导体结构的平整表面。
然后， 在半导体结构的表面上形成用于限定栅极的光抗蚀剂掩模 109， 如图 7a 和 7b所示。 光抗蚀剂掩模 109形状是沿着纸面的横向方向延伸的条带。
然后， 采用光抗蚀剂掩模， 通过各向异性的干法蚀刻， 如离子铣蚀刻、 等离子 蚀刻、 反应离子蚀刻、 激光烧蚀， 去除栅极导体层 108的暴露部分， 然后通过其中 使用蚀刻剂溶液的湿法蚀刻， 进一步去除扩散阻挡层 107、 栅介质层 106 的暴露部 分， 如图 8a和 8b所示。
在两次蚀刻之后， 栅极导体层 108形成了与光抗蚀剂掩模 109—致的沿着纸面 的横向方向延伸的条带， 栅极导体层 108的延伸方向与氧化物保护层 105的延伸方 向垂直， 并且在光抗蚀剂掩模 109未遮挡的部分暴露氧化物保护层 105和氧化物底 层 101的顶部表面， 以及暴露氧化物保护层 105的侧表面和嵌入其中的石墨烯纳米 带 104。
然后， 通过在溶剂中溶解或灰化去除光抗蚀剂掩模 109。 通过上述常规的沉积 工艺， 在半导体结构的整个表面上形成共形的氮化物层， 并接着进行反应离子蚀刻， 仅仅留下位于栅极导体层 108的侧壁上的氮化物层以形成侧墙 110， 如图 9a和 9b 所示。
优选地， 在形成侧墙 110之后， 对石墨烯纳米带 104将用作源 /漏区的部分进行 掺杂。 例如， 在美国专利申请 No. US2010/0102292A1中描述了对石墨烯纳米带 104 掺杂的方法。
然后， 通过上述常规的沉积工艺， 在半导体结构的整个表面上形成覆盖的金属 层， 如 Ti。 金属层至少填充了氧化物保护层 105之间的凹槽。 接着对金属层进行回 蚀刻，仅仅留下金属层位于氧化物保护层 105之间的凹槽以外的部分以形成源 /漏接 触 111， 如图 10a和 10b所示。
源 /漏接触 111与嵌入氧化物保护层 105中并在氧化物保护层 105的侧表面暴露 的石墨烯纳米带 104接触。
尽管未示出， 但在形成源 /漏接触 111 的步骤之后可以进一步形成层间电介质 层， 并在层间电介质层中形成到达源 /漏接触 111和栅极导体层 108的导电通道， 从 而形成完整的 M0SFET。
图 16示意性地示出了根据本发明的 M0SFET的透视图， 其中未示出层间电介质 层和导电通道。本发明的 M0SFET包括在垂直方向上堆叠以及在横向方向上排列的多 条石墨烯纳米带 104 (在图中示出了 2 X 12=24条石墨烯沟道）， 所述多条石墨烯纳 米带 104嵌入氧化物保护层 105中， 并且在每一条石墨烯纳米带 104中形成了源 / 漏区和位于源 /漏区之间的沟道， 源 /漏接触 111在氧化物保护层 105的侧表面上与 石墨烯纳米带 104的源 /漏区相接触，栅极导体层 108位于石墨烯纳米带 104的沟道 上方， 并且栅介质层 106位于栅极导体层 108和石墨烯纳米带 104之间。
以上描述只是为了示例说明和描述本发明， 而非意图穷举和限制本发明。 因此， 本发明不局限于所描述的实施例。 对于本领域的技术人员明显可知的变型或更改， 均在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种制造石墨烯纳米带的方法， 包括：
在绝缘衬底上形成包括籽层和生长抑制层的叠层；
对叠层进行图案化以形成至少一个叠层条带， 所述至少一个叠层条带暴露籽层 的侧表面； 以及
在籽层的侧表面上生长石墨烯纳米带。
2、根据权利要求 1所述的方法， 其中所述石墨烯纳米带的宽度对应于所述籽层 的厚度。
3、 根据权利要求 2所述的方法， 其中所述籽层的厚度为 5-20nm。
4、 根据权利要求 1所述的方法， 其中所述石墨烯纳米带的厚度为单层、 两层或 更多层石墨。
5、根据权利要求 1所述的方法， 其中所述叠层包括在垂直方向上交替堆叠的至 少一个籽层和至少一个生长抑制层。
6、 根据权利要求 1所述的方法， 其中所述籽层由选自 Ni、 Co、 Pt、 Ir、 Ru的 一种材料组成。
7、 根据权利要求 1所述的方法， 其中所述生长抑制层由氮化物组成。
8、根据权利要求 1所述的方法， 其中形成包括籽层和生长抑制层的叠层的步骤 包括生长籽层和生长抑制层的超晶格。
9、 一种制造 M0SFET的方法， 包括：
按照根据权利要求 1-8任一项所述的方法制造石墨烯纳米带；
在所述至少一个叠层条带之间形成氧化物保护层， 使得石墨烯纳米带嵌入氧化 物保护层中；
去除叠层条带以形成凹槽， 并且在氧化物保护层的侧表面上暴露石墨烯纳米带 的表面；
在石墨烯纳米带上形成堆叠的栅介质层和栅极导体层；
在栅极导体层的两侧形成侧墙；
在部分石墨烯纳米带中形成源 /漏区； 以及
利用金属层填充氧化物保护层之间的凹槽， 以形成与源 /漏区接触的源 /漏接触。
10、根据权利要求 9所述的方法， 其中在部分石墨烯纳米带中形成源 /漏区的步 骤包括对石墨烯纳米带的所述部分进行掺杂。
11、 根据权利要求 9所述的方法， 在去除叠层条带的步骤和形成堆叠的栅介质 层和栅极导体层的步骤之间， 还包括对石墨烯纳米带的另一部分进行掺杂以形成沟 道区， 其中， 沟道区位于源 /漏区之间。
12、 根据权利要求 9所述的方法， 其中形成堆叠的栅介质层和栅极导体层的步 骤包括：
形成栅介质层；
形成栅极导体层；
采用光抗蚀剂掩模， 蚀刻栅极导体层的一部分； 以及
采用所述光抗蚀剂掩模， 蚀刻栅介质层的一部分，
其中， 蚀刻后的栅极导体层沿着与石墨烯纳米带延伸的方向垂直的方向延伸， 并且在蚀刻后的栅极导体层的外侧暴露氧化物保护层的侧表面和嵌入其中的石墨烯 纳米带。
13、根据要权利要求 12所述的方法， 在形成栅介质层的步骤和形成栅极导体层 的步骤之间， 还包括形成扩散阻挡层。
14、 一种 M0SFET, 包括：
绝缘衬底；
位于绝缘衬底上的氧化物保护层；
嵌入氧化物保护层中的至少一条石墨烯纳米带， 其中在氧化物保护层的侧表面 上暴露所述至少一条石墨烯纳米带的表面；
在所述至少一条石墨烯纳米带的每一个中形成的沟道区；
在所述至少一条石墨烯纳米带的每一个中形成的源 /漏区， 其中沟道区位于源 / 漏区之间；
位于所述至少一条石墨烯纳米带上的栅介质层；
位于栅介质层上的栅极导体层； 以及
在氧化物保护层的侧表面上与源 /漏区相接触的源 /漏接触。
15、 根据权利要求 14所述的 M0SFET, 其中所述至少一条石墨烯纳米带包括在 垂直方向上堆叠的多条石墨烯纳米带。
16、 根据权利要求 14或 15所述的 M0SFET, 其中所述至少一条石墨烯纳米带包 括在横向方向上排列的多条石墨烯纳米带。
17、 根据权利要求 14所述的 MOSFET, 其中所述至少一条石墨烯纳米带的宽度 为 5- 20nm。
18、 根据权利要求 14所述的 MOSFET, 其中所述至少一条石墨烯纳米带的厚度 为单层、 两层或更多层石墨。
19、 根据权利要求 14所述的 MOSFET, 其中栅极导体层沿着与所述至少一条石 墨烯纳米带延伸的方向垂直的方向延伸。
20、 根据权利要求 14所述的 MOSFET, 还包括位于栅介质层和栅极导体层之间 的扩散阻挡层。
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