TWI343058B - Data bus inversion apparatus, systems, and methods - Google Patents

Data bus inversion apparatus, systems, and methods Download PDF

Info

Publication number
TWI343058B
TWI343058B TW098101701A TW98101701A TWI343058B TW I343058 B TWI343058 B TW I343058B TW 098101701 A TW098101701 A TW 098101701A TW 98101701 A TW98101701 A TW 98101701A TW I343058 B TWI343058 B TW I343058B
Authority
TW
Taiwan
Prior art keywords
data bits
dbi
algorithm
minimum
bit
Prior art date
Application number
TW098101701A
Other languages
English (en)
Other versions
TW200939241A (en
Inventor
Timothy Hollis
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of TW200939241A publication Critical patent/TW200939241A/zh
Application granted granted Critical
Publication of TWI343058B publication Critical patent/TWI343058B/zh

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00Conversion of the form of the representation of individual digits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Error Detection And Correction (AREA)

Description

、^'之孩等循環期間,根據一最 該第二子集中之該等資料位元。轉變以法而編碼 數目之^之方法’其中傳輪—f料位元群組包括在-%内,將一數目之位元自一 一動態隨機絲』至 輸-數目n M)益件或自一 DRAM器件傳 之位兀至一控制及傳輸器件。 8.如請求項1之方法,進一步包含: ==分地基於由該第—DBI演算法或該第二DBI演算 之在該循環令傳輸之該等資料位元之一狀態, ^對該複數個循環中之每_者產生—具有—值之DBI位 在接“中接收於該等頻道上傳輸之該資料位元群 組之母—子集及該DBI位元;及 =部分地基於該㈣位元之一狀態而反轉或不反轉 接收自該等頻道之該等資料位元。 9. 一種DBI方法,其包含: 在複數個循環内,於平行頻道上傳輸一資料位元群 組’該=#料位元群組之—子㈣在該複數個循環中之-個別循環中於該等平行頻道上傳輸; 根據-最小轉變演算法而編碼待在複數個該等循環期 間傳輸之該資料位元群組之複數個該等子集;及 根據-最小零演算法或一最小一演算法而編碼待在該 等循裒中之選定循環期間傳輪之該資料位元群組之該等 子集中之選定子集。 137704-1010206.doc 1〇.如請求項9之方法,其中: i最小轉變演算法而編碼在複數個該等循環期間 傳輸之該資料位元群组之複數個該等子集包括針對每 一子集: 在2循環卜第-數目或更多之該等資料位元與在 -先前循環中傳輸之對應資料位元相比具有一不同二 進位狀態時,反轉該等資料位元;及 :該循環中少於該第一數目之該等資料位元與在該 先前循環中傳輸之對應資料位元相比具有一不同二進 位狀態時’不反轉該等資料位元; /㈣該最小零演算法或該最小一演算法而編碼 循環中之選定循環期間傳輸之該資料位料組之 集中之選定子集包括’針對每一選定子集中 位元: τ貝科 在根據該最小零演算法而反轉時,於一第三數目或 更多之該等資料位元為二進位零時,反轉該選定子集 中之該等資料位元,且於少於該第二數目之該等資料 位兀為二進位零時,不反轉該等資料位元;或 在根據該最小-演算法而反轉時,於一第三數目 更多之該等資料位元為二進位一時,反轉該選定子集 中之該等資料位元,且於少於該第三數目之該等資料 位兀為二進位一時,不反轉該等資料位元。 11·如请求項10之方法,直中: 該第-數目之該等資料位元為該等資料位元之一半; 137704-1010206.doc -4- 1343058 該第二數目之該等資料 該第三數目之該等資料位元為 ^2.如請求項9之方法 ’料位兀之十 一演I、根據該最小零演算法或該最小 次算法1編韻㈣等 該資料位元群組之料子隼中之=^仏期間傳輸之 ㈣循環—循環;之中:二, 法或該最小-演算法而編碼該等資料=該最小零演算 13.如請求項9之方法,其中: 根據該最小轉變、、宫曾、、t 間傳輸之㈣祖、、碼待在複數個該等循環期 等演算法或該最小—演算法而編碼待在該 =中之選定循環期間傳輸之該資科位元群組之該等 選定子集包括在每N個循環期間,根據該最小 令次异法或該最小-演算法而編 14.如請求項9之方法,進一步包含: 心 至少部分地基於由該最小轉變演算法或該最小零演算 ^該最小-演算法所判定之在該循環t傳輸之該等資 ,4位π之-狀態,針對該複數個循環中之每—者而產生 一具有—值之DBI位元; 在-與該等平行頻道分開之頻道上傳輸該聰位元; -在一接收器中純於該等平行頻道上傳輪之該資料位 凡群組之每一子集及該DBI位元;及 137704-10l0206.doc
UJO 至少部分地基於該DBI位元之一狀態而反轉或不反轉 在該接收器處自該等平行頻道接收之該等資料位元以 復原該資料位元群組。 15. —種DBI裝置,其包含: 平行輸人其用以接收待在平行頻道上傳輸之平行原 始資料位元; 一 DBI電路 據複數個DBI演算法中 資料位元;及 其耦接至該等平行輸入,且經組態以根 之一選定演算法而編瑪該等原始 控制模組,其用於決定該DBI電路應實施該複數個 DBI凟算法中之何者,且用於指示將該經決定之d刖演算 法經由一控制信號傳送至該〇趴電路。 16. 如咐长項15之裝置’其中該DBI電路經組態以根據一最 小轉變演算法、-最小零演算法及/或一最小一演算法而 編碼該等原始資料位元。 17. 如凊求項15之裝置,其中該DBI電路包括: 一第一模組,其經組態以在該等平行頻道上傳輸該等 原始資料位元之前,根據該等DBI演算法中之一者而決 定是否反轉該等原始資料位元;及 一第二模組,其經組態以回應於該第一模組之該決定 而反轉或不反轉該等原始資料位元,且將經反轉或未經 反轉之該等資料位元耦接至該等平行頻道。 18.如請求項17之裝置,其中該第一模組經組態以回應於該 第一模組之該決定而產生一 DBI位元,以指示在該等平 13 7704-101〇206_ doc 19. 仃頻道上傳輪之該等資料位元之一狀態,且在該等平行 頻道中之-者上傳輸該DBI位元。 如請求項17之裝置,其中: 、第模組經耦接以接收該等原始資料位元,且經耦 接乂自該第-模組接收-控制信號,該第二模組經組態 、據來自4多數偵測電路之該控制信號而將該等原始 " 元耦接至該等平行頻道或反轉該等原始資料位 一 將該等經反轉資料位元耦接至該等平行頻道; 且其中該第一模組包括: 次互斥OR邏輯閘,其具有—經輕接以接收該等原始 貝料位το之第_輸人及—輕接至該等平行頻道以接收 在一先前循環中於該等平行頻道上傳輸之資料位元之 ""輸入以比較該等原始資料位元與在該先前循環 中傳輸之4等資料位兀以產生輸出位元,該等輸出位 元指示在該等平行頻道上傳輸該等原始f料位元時將 發生之一數目之信號轉變;及 ,多工器電路,其具有一經耦接以接收該等原始資 料位元之第一輸入、一經耦接以接收該互斥〇r邏輯閘 之該等輸出位元之第二輸人及—經輕接以接收一控制 信號之控制輸入,該多工器經組態以: 在該控制信號選擇一最小零演算法或一最小一演 算法時,將該等原始資料位元耦接至—多數偵測電 路;及 在該控制信號選擇該最小轉變演算法時,將該互 137704-1010206.doc 斥OR邏輯閘之該等輸出位元耦接至該多數偵測電 路;且 該多數偵測電路經組態以偵測該等原始資料位元或該 互斥OR邏輯閘之該等輸出位元中之多數二進位一或二進 位零,且基於該所偵測之多數二進位一或二進位零而產 生輕接至該第二模組之該控制信號。 20. 一種DBI系統,其包含: 多個頻道; 處理器,其耦接至該等頻道以自該等頻道接收資料 位元或將該等資料位元傳輸至該等頻道; 一圮憶體組,其耦接至該等頻道以供應待在該等頻道 上傳輸之該等資料位元,或自該等頻道接收該等資料位 元; DBI模組’其耦接至該等頻道且經組態以根據複數 個DBI决算法中之一選定一者而將該等資料位元編碼成 經編碼貢料位元,且將該等經編碼資料位元傳輸至該等 頻道上;及
一控制模組’其用於決定該DBI模組應實施複數個DBI 廣算法中之何者’且用於指示將該經決定之DBI演算法 傳送至該DBI模組。 21. 如明求項20之系統,其中該DBI模組經組態以根據一最 小轉變演算法、-最小零演算法及/或-最小-演算法而 編碼該等資料位元。 22. 如研求項20之系統,其中該DBI模組包括: 137704-1010206.doc $模組’其經組態以根據該等DBI演算法中之-者而決U否反轉該等f料位元,且產生—指示在該等 頻C上所傳輸之該等經編碍資料位元之—狀態的〇則位 元,該DBI位元係在該等頻道上傳輸;及 第一模組,其經組態以回應於該第一模組之該決定 而反轉或不反轉該等資料位元。 23_如印求項20之系統,其中該DBI模組係在該處理器或該 δ己憶體組中’或在該處理器及該記憶體組兩者中。
137704-1010206.doc
TW098101701A 2008-01-16 2009-01-16 Data bus inversion apparatus, systems, and methods TWI343058B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/015,311 US7616133B2 (en) 2008-01-16 2008-01-16 Data bus inversion apparatus, systems, and methods

Publications (2)

Publication Number Publication Date
TW200939241A TW200939241A (en) 2009-09-16
TWI343058B true TWI343058B (en) 2011-06-01

Family

ID=40851672

Family Applications (2)

Application Number Title Priority Date Filing Date
TW099125177A TWI490880B (zh) 2008-01-16 2009-01-16 資料匯流排反轉裝置、系統及方法
TW098101701A TWI343058B (en) 2008-01-16 2009-01-16 Data bus inversion apparatus, systems, and methods

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW099125177A TWI490880B (zh) 2008-01-16 2009-01-16 資料匯流排反轉裝置、系統及方法

Country Status (6)

Country Link
US (4) US7616133B2 (zh)
EP (1) EP2248031B1 (zh)
KR (1) KR101125975B1 (zh)
CN (1) CN101911034B (zh)
TW (2) TWI490880B (zh)
WO (1) WO2009091577A2 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI627539B (zh) * 2016-01-22 2018-06-21 美光科技公司 用於編碼及解碼多階層通信架構之信號線之設備及方法
US10283187B2 (en) 2017-07-19 2019-05-07 Micron Technology, Inc. Apparatuses and methods for providing additional drive to multilevel signals representing data
US10679692B2 (en) 2018-05-25 2020-06-09 Winbond Electronics Corp. Memory apparatus and majority detector thereof

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7616133B2 (en) * 2008-01-16 2009-11-10 Micron Technology, Inc. Data bus inversion apparatus, systems, and methods
US8606982B2 (en) * 2008-03-10 2013-12-10 Qimonda Ag Derivative logical output
FR2928757B1 (fr) * 2008-03-14 2014-06-20 Centre Nat Rech Scient Procede et dispositif de codage, systeme electronique et support d'enregistrement associes
JP5588976B2 (ja) * 2008-06-20 2014-09-10 ラムバス・インコーポレーテッド 周波数応答バス符号化
US7899961B2 (en) * 2008-09-02 2011-03-01 Qimonda Ag Multi-mode bus inversion method and apparatus
FR2949633B1 (fr) * 2009-08-27 2011-10-21 St Microelectronics Rousset Procede et dispositif de contremesure pour proteger des donnees circulant dans un composant electronique
EP2526492B1 (en) * 2010-01-20 2016-01-06 Rambus Inc. Multiple word data bus inversion
US8879654B2 (en) * 2010-03-10 2014-11-04 Micron Technology, Inc. Communication interface with configurable encoding based on channel termination
US8260992B2 (en) * 2010-04-12 2012-09-04 Advanced Micro Devices, Inc. Reducing simultaneous switching outputs using data bus inversion signaling
KR101145317B1 (ko) * 2010-04-29 2012-05-14 에스케이하이닉스 주식회사 데이터 전송회로 및 데이터 전송방법, 데이터 송/수신 시스템
US9112536B2 (en) * 2011-01-31 2015-08-18 Everspin Technologies, Inc. Method of reading and writing to a spin torque magnetic random access memory with error correcting code
US8405529B2 (en) * 2011-03-11 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Using bus inversion to reduce simultaneous signal switching
KR20120110798A (ko) * 2011-03-30 2012-10-10 에스케이하이닉스 주식회사 데이터 전송회로 및 데이터 송/수신 시스템
US8543891B2 (en) * 2011-09-21 2013-09-24 Apple Inc. Power-optimized decoding of linear codes
US8924740B2 (en) * 2011-12-08 2014-12-30 Apple Inc. Encryption key transmission with power analysis attack resistance
US8726139B2 (en) * 2011-12-14 2014-05-13 Advanced Micro Devices, Inc. Unified data masking, data poisoning, and data bus inversion signaling
US8909840B2 (en) 2011-12-19 2014-12-09 Advanced Micro Devices, Inc. Data bus inversion coding
US8854236B2 (en) 2012-05-18 2014-10-07 Micron Technology, Inc. Methods and apparatuses for low-power multi-level encoded signals
US8729923B2 (en) 2012-08-29 2014-05-20 Sandisk Technologies Inc. Majority vote circuit
US9245625B2 (en) * 2012-09-26 2016-01-26 Broadcom Corporation Low power signaling for data transfer
US8963575B2 (en) 2012-09-26 2015-02-24 Sandisk Technologies Inc. Analog majority vote circuit
US9529749B2 (en) * 2013-03-15 2016-12-27 Qualcomm Incorporated Data bus inversion (DBI) encoding based on the speed of operation
TWI614607B (zh) * 2013-03-15 2018-02-11 積佳半導體股份有限公司 用於使用資料匯流排反相的記憶體操作之記憶體裝置與方法
TWI609371B (zh) * 2013-03-15 2017-12-21 積佳半導體股份有限公司 涉及群組成10位元之資料信號的動態隨機存取記憶體(dram)裝置及其操作方法
US8941434B1 (en) * 2013-07-12 2015-01-27 Samsung Display Co., Ltd. Bus encoding scheme based on non-uniform distribution of power delivery network components among I/O circuits
US9270417B2 (en) * 2013-11-21 2016-02-23 Qualcomm Incorporated Devices and methods for facilitating data inversion to limit both instantaneous current and signal transitions
US9252802B2 (en) 2014-02-07 2016-02-02 Qualcomm Incorporated Encoding for partitioned data bus
KR20150099928A (ko) * 2014-02-24 2015-09-02 삼성전자주식회사 반도체 메모리 장치 및 메모리 시스템
KR102154165B1 (ko) * 2014-03-31 2020-09-09 에스케이하이닉스 주식회사 데이터 처리 장치 및 데이터 처리 시스템
JP6200370B2 (ja) * 2014-04-23 2017-09-20 ルネサスエレクトロニクス株式会社 データバス駆動回路、それを備えた半導体装置及び半導体記憶装置
US9405721B2 (en) * 2014-06-06 2016-08-02 Micron Technology, Inc. Apparatuses and methods for performing a databus inversion operation
US9244875B1 (en) * 2014-07-18 2016-01-26 Qualcomm Incorporated Systems and methods for transition-minimized data bus inversion
US9665527B2 (en) 2014-12-09 2017-05-30 Intel Corporation Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines
US20160173134A1 (en) * 2014-12-15 2016-06-16 Intel Corporation Enhanced Data Bus Invert Encoding for OR Chained Buses
US9792246B2 (en) * 2014-12-27 2017-10-17 Intel Corporation Lower-power scrambling with improved signal integrity
GB2536309B (en) * 2015-03-09 2017-08-02 Cirrus Logic Int Semiconductor Ltd Low power bidirectional bus
KR20160117088A (ko) 2015-03-31 2016-10-10 에스케이하이닉스 주식회사 반도체장치
US9984035B2 (en) 2015-08-27 2018-05-29 Qualcomm Incorporated Efficient encoding and decoding architecture for high-rate data transfer through a parallel bus
KR102467526B1 (ko) 2015-10-16 2022-11-17 삼성디스플레이 주식회사 표시 장치
US9922686B2 (en) 2016-05-19 2018-03-20 Micron Technology, Inc. Apparatuses and methods for performing intra-module databus inversion operations
US10127100B2 (en) 2016-06-03 2018-11-13 International Business Machines Corporation Correcting a data storage error caused by a broken conductor using bit inversion
KR102608844B1 (ko) * 2016-06-28 2023-12-05 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그의 동작 방법
US10373657B2 (en) 2016-08-10 2019-08-06 Micron Technology, Inc. Semiconductor layered device with data bus
KR20180057028A (ko) * 2016-11-21 2018-05-30 에스케이하이닉스 주식회사 데이터 반전 회로
KR20180087496A (ko) * 2017-01-23 2018-08-02 에스케이하이닉스 주식회사 메모리 시스템
US10146719B2 (en) * 2017-03-24 2018-12-04 Micron Technology, Inc. Semiconductor layered device with data bus
US10853300B2 (en) * 2017-03-31 2020-12-01 Intel Corporation Low latency statistical data bus inversion for energy reduction
US10290289B2 (en) 2017-04-01 2019-05-14 Intel Corporation Adaptive multibit bus for energy optimization
US10540304B2 (en) 2017-04-28 2020-01-21 Advanced Micro Devices, Inc. Power-oriented bus encoding for data transmission
JP6431583B2 (ja) * 2017-08-25 2018-11-28 ルネサスエレクトロニクス株式会社 モジュール、及び、システム
CN110224786B (zh) * 2018-03-01 2022-05-13 京东方科技集团股份有限公司 数据传输方法、装置、系统及显示装置
US10664432B2 (en) 2018-05-23 2020-05-26 Micron Technology, Inc. Semiconductor layered device with data bus inversion
KR102605637B1 (ko) * 2018-07-27 2023-11-24 에스케이하이닉스 주식회사 반도체 장치 및 데이터 처리 시스템
US10964702B2 (en) 2018-10-17 2021-03-30 Micron Technology, Inc. Semiconductor device with first-in-first-out circuit
US10963168B2 (en) * 2019-01-15 2021-03-30 Micron Technology, Inc. Memory system and operations of the same
CN112217755B (zh) * 2019-07-11 2023-11-03 默升科技集团有限公司 用于增强的纠错的并行信道偏斜
TWI740609B (zh) * 2020-08-18 2021-09-21 世界先進積體電路股份有限公司 存取方法及記憶體
US20210004347A1 (en) * 2020-09-23 2021-01-07 Intel Corporation Approximate data bus inversion technique for latency sensitive applications
US11289136B1 (en) 2020-10-27 2022-03-29 Vanguard International Semiconductor Corporation Memory device and access method
KR20220086904A (ko) * 2020-12-17 2022-06-24 삼성전자주식회사 데이터 전송 방법 및 데이터 전송 장치
US11804992B2 (en) 2021-04-08 2023-10-31 Micron Technology, Inc. Asymetric decision feedback equalization

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6823303B1 (en) * 1998-08-24 2004-11-23 Conexant Systems, Inc. Speech encoder using voice activity detection in coding noise
US6584526B1 (en) * 2000-09-21 2003-06-24 Intel Corporation Inserting bus inversion scheme in bus path without increased access latency
JP2002108522A (ja) * 2000-09-26 2002-04-12 Internatl Business Mach Corp <Ibm> データ転送装置、表示装置、データ送出装置、データ受取装置、データの転送方法
TW507128B (en) * 2001-07-12 2002-10-21 Via Tech Inc Data memory controller supporting the data bus invert
JP3696812B2 (ja) * 2001-07-19 2005-09-21 富士通株式会社 入出力インタフェースおよび半導体集積回路
DE10145722A1 (de) * 2001-09-17 2003-04-24 Infineon Technologies Ag Konzept zur sicheren Datenkommunikation zwischen elektronischen Bausteinen
US20040068594A1 (en) * 2002-10-08 2004-04-08 Anthony Asaro Method and apparatus for data bus inversion
WO2004052015A1 (ja) * 2002-11-29 2004-06-17 Sony Corporation 符号化装置およびその方法
JP2004362262A (ja) * 2003-06-04 2004-12-24 Renesas Technology Corp 半導体集積回路
US7411840B2 (en) 2004-03-02 2008-08-12 Via Technologies, Inc. Sense mechanism for microprocessor bus inversion
US20050289435A1 (en) * 2004-06-29 2005-12-29 Mulla Dean A Fast approximate DINV calculation in parallel with coupled ECC generation or correction
DE102005013322B3 (de) * 2005-03-22 2006-10-05 Infineon Technologies Ag Schaltung zur Erzeugung eines Datenbitinvertierungsflags (DBI)
JP4495034B2 (ja) * 2005-06-01 2010-06-30 パナソニック株式会社 可変長符号化方式および可変長符号化装置
US7869525B2 (en) * 2005-08-01 2011-01-11 Ati Technologies, Inc. Dynamic bus inversion method and system
KR100643498B1 (ko) 2005-11-21 2006-11-10 삼성전자주식회사 반도체 메모리에서의 데이터 버스 반전 회로 및 데이터버스 반전 방법
KR100877680B1 (ko) * 2006-04-04 2009-01-09 삼성전자주식회사 반도체 장치 사이의 단일형 병렬데이터 인터페이스 방법,기록매체 및 반도체 장치
KR100837802B1 (ko) * 2006-09-13 2008-06-13 주식회사 하이닉스반도체 데이터 입출력 오류 검출 기능을 갖는 반도체 메모리 장치
US7925844B2 (en) * 2007-11-29 2011-04-12 Micron Technology, Inc. Memory register encoding systems and methods
US7522073B1 (en) * 2007-11-30 2009-04-21 Qimonda North America Corp. Self-adapted bus inversion
US7616133B2 (en) 2008-01-16 2009-11-10 Micron Technology, Inc. Data bus inversion apparatus, systems, and methods

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI627539B (zh) * 2016-01-22 2018-06-21 美光科技公司 用於編碼及解碼多階層通信架構之信號線之設備及方法
US10365833B2 (en) 2016-01-22 2019-07-30 Micron Technology, Inc. Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures
US11106367B2 (en) 2016-01-22 2021-08-31 Micron Technology, Inc. Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures
US11809715B2 (en) 2016-01-22 2023-11-07 Micron Technology, Inc. Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures
US10283187B2 (en) 2017-07-19 2019-05-07 Micron Technology, Inc. Apparatuses and methods for providing additional drive to multilevel signals representing data
US10861531B2 (en) 2017-07-19 2020-12-08 Micron Technology, Inc. Apparatuses and methods for providing additional drive to multilevel signals representing data
US10679692B2 (en) 2018-05-25 2020-06-09 Winbond Electronics Corp. Memory apparatus and majority detector thereof

Also Published As

Publication number Publication date
US7616133B2 (en) 2009-11-10
KR101125975B1 (ko) 2012-03-20
TW200939241A (en) 2009-09-16
EP2248031A2 (en) 2010-11-10
US20100026533A1 (en) 2010-02-04
KR20100105685A (ko) 2010-09-29
US20120056762A1 (en) 2012-03-08
WO2009091577A2 (en) 2009-07-23
EP2248031B1 (en) 2018-02-28
US9048856B2 (en) 2015-06-02
CN101911034B (zh) 2013-11-06
US8094045B2 (en) 2012-01-10
US20090182918A1 (en) 2009-07-16
EP2248031A4 (en) 2016-04-20
TW201042655A (en) 2010-12-01
TWI490880B (zh) 2015-07-01
WO2009091577A3 (en) 2009-09-11
US8766828B2 (en) 2014-07-01
US20140313062A1 (en) 2014-10-23
CN101911034A (zh) 2010-12-08

Similar Documents

Publication Publication Date Title
TWI343058B (en) Data bus inversion apparatus, systems, and methods
TWI311252B (en) Methods and apparatuses to effect a variable-width link
CN107040261B (zh) 调整延伸极化码的码长度的方法及装置
TWI528376B (zh) 用於低功率多重位準編碼訊號之方法及裝置
TWI311016B (en) Method and system for transmiting n-bit video data over a serial link
US8581755B2 (en) Multiple word data bus inversion
US20080268800A1 (en) Hybrid parallel/serial bus interface
JP2007282235A5 (zh)
US7475273B2 (en) Hybrid parallel/serial bus interface
US9672910B2 (en) Memory architecture for storing data in a plurality of memory chips
KR20110111108A (ko) 반도체 장치 및 이의 복호 방법
TW200810372A (en) Transmitting/receiving methods and systems for DC balance encoded data including simultaneous switching noise reducing preambles
KR970068648A (ko) 가변 길이 해독기 및 클럭 사이클마다 2개의 코드를 해독하는 방법(Variable length decoder and method for decoding two codes per clock cysle)
JP4956295B2 (ja) 半導体記憶装置
US9515675B2 (en) Interface circuit operating to recover error of transmitted data
JP2009009289A5 (zh)
JP4603282B2 (ja) メモリインターフェースシステム
US7170431B2 (en) Data transmitting circuit and method based on differential value data encoding
KR100809961B1 (ko) 데이터 처리장치 및 데이터 처리방법
US20090310657A1 (en) Method for Low Power Communication Encoding
JP5698255B2 (ja) 直交ベクトルを用いたデータ交換装置
WO2024066284A1 (zh) 一种与源址无关的分布式状态监测方法
EP4082136A1 (en) Apparatus and method for transmitting a bit in addition to a plurality of payload data symbols of a communication pro-tocol, and apparatus and method for decoding a data signal
JPWO2021049024A1 (ja) 受信装置および通信システム
Kumar et al. SERIAL LINKS BASED EMBEDDED TRANSITION INVERSION CODING WITH LOW SWITCHING ACTIVITY

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees