TWI339414B - Discriminative soi with oxide holes underneath dc source/drain - Google Patents

Discriminative soi with oxide holes underneath dc source/drain Download PDF

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Publication number
TWI339414B
TWI339414B TW094100107A TW94100107A TWI339414B TW I339414 B TWI339414 B TW I339414B TW 094100107 A TW094100107 A TW 094100107A TW 94100107 A TW94100107 A TW 94100107A TW I339414 B TWI339414 B TW I339414B
Authority
TW
Taiwan
Prior art keywords
layer
soi
region
substrate
germanium
Prior art date
Application number
TW094100107A
Other languages
English (en)
Chinese (zh)
Other versions
TW200524047A (en
Inventor
Robert C Wong
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200524047A publication Critical patent/TW200524047A/zh
Application granted granted Critical
Publication of TWI339414B publication Critical patent/TWI339414B/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6758Thin-film transistors [TFT] characterised by the insulating substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • H10D62/116Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW094100107A 2004-01-08 2005-01-03 Discriminative soi with oxide holes underneath dc source/drain TWI339414B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/754,320 US6958516B2 (en) 2004-01-08 2004-01-08 Discriminative SOI with oxide holes underneath DC source/drain

Publications (2)

Publication Number Publication Date
TW200524047A TW200524047A (en) 2005-07-16
TWI339414B true TWI339414B (en) 2011-03-21

Family

ID=34739363

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094100107A TWI339414B (en) 2004-01-08 2005-01-03 Discriminative soi with oxide holes underneath dc source/drain

Country Status (8)

Country Link
US (1) US6958516B2 (enExample)
EP (1) EP1706905A1 (enExample)
JP (1) JP5527922B2 (enExample)
KR (1) KR100956716B1 (enExample)
CN (1) CN1906762A (enExample)
IL (1) IL176686A (enExample)
TW (1) TWI339414B (enExample)
WO (1) WO2005069373A1 (enExample)

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US7659172B2 (en) * 2005-11-18 2010-02-09 International Business Machines Corporation Structure and method for reducing miller capacitance in field effect transistors
JP4867396B2 (ja) * 2006-03-01 2012-02-01 セイコーエプソン株式会社 半導体装置及びその製造方法
US7482656B2 (en) * 2006-06-01 2009-01-27 International Business Machines Corporation Method and structure to form self-aligned selective-SOI
US7795910B1 (en) 2007-08-21 2010-09-14 Marvell International Ltd. Field-programmable gate array using charge-based nonvolatile memory
US8921190B2 (en) 2008-04-08 2014-12-30 International Business Machines Corporation Field effect transistor and method of manufacture
US7989893B2 (en) * 2008-08-28 2011-08-02 International Business Machines Corporation SOI body contact using E-DRAM technology
CN102064097B (zh) * 2009-11-17 2012-11-07 中国科学院上海微系统与信息技术研究所 一种混晶材料的制备方法及用该材料制备的半导体器件
CN101924138B (zh) * 2010-06-25 2013-02-06 中国科学院上海微系统与信息技术研究所 防止浮体及自加热效应的mos器件结构及其制备方法
CN101986435B (zh) * 2010-06-25 2012-12-19 中国科学院上海微系统与信息技术研究所 防止浮体及自加热效应的mos器件结构的制造方法
PT2446792E (pt) 2010-10-29 2015-02-18 Gruppo Cimbali Spa Peça de extremidade substituível para uma boca de descarga de vapor de uma máquina de café
CN102214684B (zh) * 2011-06-03 2012-10-10 清华大学 一种具有悬空源漏的半导体结构及其形成方法
US9892910B2 (en) * 2015-05-15 2018-02-13 International Business Machines Corporation Method and structure for forming a dense array of single crystalline semiconductor nanocrystals
US9722057B2 (en) * 2015-06-23 2017-08-01 Global Foundries Inc. Bipolar junction transistors with a buried dielectric region in the active device region

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US4683637A (en) * 1986-02-07 1987-08-04 Motorola, Inc. Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing
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US5382818A (en) * 1993-12-08 1995-01-17 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode
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JP2002208696A (ja) * 2001-01-11 2002-07-26 Seiko Epson Corp 半導体装置及びその製造方法
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Also Published As

Publication number Publication date
US20050151193A1 (en) 2005-07-14
TW200524047A (en) 2005-07-16
JP2007519239A (ja) 2007-07-12
IL176686A0 (en) 2006-10-31
CN1906762A (zh) 2007-01-31
KR20060123434A (ko) 2006-12-01
IL176686A (en) 2010-12-30
WO2005069373A1 (en) 2005-07-28
US6958516B2 (en) 2005-10-25
KR100956716B1 (ko) 2010-05-06
EP1706905A1 (en) 2006-10-04
JP5527922B2 (ja) 2014-06-25

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