JP2007519239A - 直流ノード拡散領域の下に埋め込み酸化物を有さず、酸化物ホールを有する差別化soi構造 - Google Patents
直流ノード拡散領域の下に埋め込み酸化物を有さず、酸化物ホールを有する差別化soi構造 Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 93
- 239000000463 material Substances 0.000 claims abstract description 23
- 239000012212 insulator Substances 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims description 36
- 239000000654 additive Substances 0.000 claims description 18
- 230000000996 additive effect Effects 0.000 claims description 18
- 239000004020 conductor Substances 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 8
- 229910003811 SiGeC Inorganic materials 0.000 claims description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 229910003465 moissanite Inorganic materials 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 27
- 238000000034 method Methods 0.000 description 23
- 230000008569 process Effects 0.000 description 19
- 230000000694 effects Effects 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
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- 238000013461 design Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
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- 230000015556 catabolic process Effects 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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Abstract
Description
本体接触部領域を介して下地のSi含有基板と接触する複数のSOIデバイスが上に配置された上部Si含有層を備えるシリコン・オン・インシュレータ(SOI)基板材料と、
前記SOIデバイスの一つに隣接するDCノード拡散領域と
を含み、前記DCノード拡散領域は、前記Si含有基板と接触する。すなわち、DCノード拡散領域は、下地の埋め込み酸化物領域を備えない。
Claims (24)
- 本体接触部領域を介して下地のSi含有基板と接触する複数のシリコン・オン・インシュレータ(SOI)デバイスが上に配置された上部Si含有層を備えるSOI基板材料と、前記SOIデバイスの一つに隣接し、前記Si含有基板と接触するDCノード拡散領域と
を含むシリコン・オン・インシュレータ(SOI)構造。 - 前記複数のSOIデバイスは、金属酸化物半導体電界効果トランジスタ(MOSFET)を含む、請求項1に記載の選択的SOI構造。
- 前記複数のSOIデバイスは、前記SOI基板材料の上部Si含有層の上に配置されたデバイス構成部品を備える、請求項1に記載の選択的SOI構造。
- 前記複数のSOIデバイスは、前記上部Si含有層中に配置された活性ソース/ドレイン領域を備える、請求項3に記載の選択的SOI構造。
- 前記活性ソース/ドレイン領域は、埋め込み酸化物区域の上に配置される、請求項4に記載の選択的SOI構造。
- 前記埋め込み酸化物区域は、トレンチ分離領域に隣接して配置される水平エッチングされた区域である、請求項5に記載の選択的SOI構造。
- 前記DCノード拡散領域は、ソース電圧を受けることができる第一の領域、基準電圧を受けることができる第二の領域、第三の接地領域または前記第一、第二および第三の領域の少なくとも二つを含む任意の組み合わせを備える、請求項1に記載の選択的SOI構造。
- 前記DCノード拡散領域は、下に酸化物を備えずにバルクSi中に配置される、請求項1に記載の選択的SOI構造。
- 前記MOSFETは、ゲート誘電体およびゲート導電体を備える、請求項2に記載の選択的SOI構造。
- 前記SOI基板は、前記DCノード拡散領域を形成させるための差別化領域を有する加法SOI基板である、請求項1に記載の選択的SOI構造。
- 前記SOI基板はSi含有材料で構成される、請求項1に記載の選択的SOI構造。
- 前記Si含有材料は、Si、SiGe、SiC、SiGeC、Si/Si、Si/SiCおよびSi/SiGeCからなる群から選ばれる、請求項11に記載の選択的SOI構造。
- 前記上部Si含有層は、約50から約200nmの厚さを有する、請求項3に記載の選択的SOI構造。
- 少なくとも一つの選択的シリコン・オン・インシュレータ(SOI)構造を含む集積回路であって、前記少なくとも一つのSOI構造は、本体接触部領域を介して下地のSi含有基板と接触する複数のSOIデバイスが上に配置された上部Si含有層を備えるシリコン・オン・インシュレータ(SOI)基板材料と、前記SOIデバイスの一つに隣接し、前記Si含有基板と接触するDCノード拡散領域とを備える集積回路。
- SOI基板、前記SOI基板中のDCノード拡散領域、および前記SOI基板中の埋め込み酸化物材料を含む半導体基板であって、前記DCノード拡散領域は、前記SOI基板の下地のSi含有基板と接触する半導体基板。
- 前記SOI基板は、上部Si含有層を含む、請求項15に記載の半導体基板。
- 前記上部Si含有層および前記下地のSi含有基板は、Si、SiGe、SiC、SiGeC、Si/Si、Si/SiCおよびSi/SiGeCからなる群から選ばれるシリコン半導体材料で構成される、請求項16に記載の半導体基板。
- 前記上部Si含有層は、約50から約200nmの厚さを有する、請求項16に記載の半導体基板。
- 前記埋め込み酸化物材料は結晶性である、請求項15に記載の半導体基板。
- 前記埋め込み酸化物材料は非結晶性である、請求項15に記載の半導体基板。
- 前記埋め込み酸化物材料は、約30から約100nmの厚さを有する、請求項15に記載の半導体基板。
- 前記埋め込み酸化物材料と接触する少なくとも一つのトレンチ分離領域をさらに含む、請求項15に記載の半導体基板。
- 前記DCノード拡散領域は、ソース電圧を受けることができる第一の領域、基準電圧を受けることができる第二の領域、第三の接地領域または前記第一、第二および第三の領域の少なくとも二つを含む任意の組み合わせを備える、請求項15に記載の半導体基板。
- 前記DCノード拡散領域は、下に酸化物を備えずにバルクSi中に配置される、請求項15に記載の半導体基板。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/754,320 | 2004-01-08 | ||
US10/754,320 US6958516B2 (en) | 2004-01-08 | 2004-01-08 | Discriminative SOI with oxide holes underneath DC source/drain |
PCT/EP2005/050039 WO2005069373A1 (en) | 2004-01-08 | 2005-01-06 | Discriminative soi with oxide holes underneath dc source/drain |
Publications (3)
Publication Number | Publication Date |
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JP2007519239A true JP2007519239A (ja) | 2007-07-12 |
JP2007519239A5 JP2007519239A5 (ja) | 2007-11-22 |
JP5527922B2 JP5527922B2 (ja) | 2014-06-25 |
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JP2006548301A Expired - Fee Related JP5527922B2 (ja) | 2004-01-08 | 2005-01-06 | 直流ノード拡散領域の下に埋め込み酸化物を有さず、酸化物ホールを有する差別化soi構造 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6958516B2 (ja) |
EP (1) | EP1706905A1 (ja) |
JP (1) | JP5527922B2 (ja) |
KR (1) | KR100956716B1 (ja) |
CN (1) | CN1906762A (ja) |
IL (1) | IL176686A (ja) |
TW (1) | TWI339414B (ja) |
WO (1) | WO2005069373A1 (ja) |
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US7659172B2 (en) * | 2005-11-18 | 2010-02-09 | International Business Machines Corporation | Structure and method for reducing miller capacitance in field effect transistors |
JP4867396B2 (ja) * | 2006-03-01 | 2012-02-01 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
US7482656B2 (en) * | 2006-06-01 | 2009-01-27 | International Business Machines Corporation | Method and structure to form self-aligned selective-SOI |
US7795910B1 (en) | 2007-08-21 | 2010-09-14 | Marvell International Ltd. | Field-programmable gate array using charge-based nonvolatile memory |
US8921190B2 (en) * | 2008-04-08 | 2014-12-30 | International Business Machines Corporation | Field effect transistor and method of manufacture |
US7989893B2 (en) * | 2008-08-28 | 2011-08-02 | International Business Machines Corporation | SOI body contact using E-DRAM technology |
CN102064097B (zh) * | 2009-11-17 | 2012-11-07 | 中国科学院上海微系统与信息技术研究所 | 一种混晶材料的制备方法及用该材料制备的半导体器件 |
CN101986435B (zh) * | 2010-06-25 | 2012-12-19 | 中国科学院上海微系统与信息技术研究所 | 防止浮体及自加热效应的mos器件结构的制造方法 |
CN101924138B (zh) * | 2010-06-25 | 2013-02-06 | 中国科学院上海微系统与信息技术研究所 | 防止浮体及自加热效应的mos器件结构及其制备方法 |
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CN102214684B (zh) * | 2011-06-03 | 2012-10-10 | 清华大学 | 一种具有悬空源漏的半导体结构及其形成方法 |
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KR100304713B1 (ko) | 1999-10-12 | 2001-11-02 | 윤종용 | 부분적인 soi 구조를 갖는 반도체소자 및 그 제조방법 |
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2004
- 2004-01-08 US US10/754,320 patent/US6958516B2/en not_active Expired - Lifetime
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2005
- 2005-01-03 TW TW094100107A patent/TWI339414B/zh not_active IP Right Cessation
- 2005-01-06 EP EP05701449A patent/EP1706905A1/en not_active Withdrawn
- 2005-01-06 WO PCT/EP2005/050039 patent/WO2005069373A1/en active Application Filing
- 2005-01-06 JP JP2006548301A patent/JP5527922B2/ja not_active Expired - Fee Related
- 2005-01-06 KR KR1020067013487A patent/KR100956716B1/ko not_active IP Right Cessation
- 2005-01-06 CN CNA2005800015468A patent/CN1906762A/zh active Pending
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Also Published As
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US20050151193A1 (en) | 2005-07-14 |
KR20060123434A (ko) | 2006-12-01 |
TWI339414B (en) | 2011-03-21 |
JP5527922B2 (ja) | 2014-06-25 |
IL176686A0 (en) | 2006-10-31 |
EP1706905A1 (en) | 2006-10-04 |
US6958516B2 (en) | 2005-10-25 |
CN1906762A (zh) | 2007-01-31 |
TW200524047A (en) | 2005-07-16 |
IL176686A (en) | 2010-12-30 |
WO2005069373A1 (en) | 2005-07-28 |
KR100956716B1 (ko) | 2010-05-06 |
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