JP5527922B2 - 直流ノード拡散領域の下に埋め込み酸化物を有さず、酸化物ホールを有する差別化soi構造 - Google Patents

直流ノード拡散領域の下に埋め込み酸化物を有さず、酸化物ホールを有する差別化soi構造 Download PDF

Info

Publication number
JP5527922B2
JP5527922B2 JP2006548301A JP2006548301A JP5527922B2 JP 5527922 B2 JP5527922 B2 JP 5527922B2 JP 2006548301 A JP2006548301 A JP 2006548301A JP 2006548301 A JP2006548301 A JP 2006548301A JP 5527922 B2 JP5527922 B2 JP 5527922B2
Authority
JP
Japan
Prior art keywords
region
soi
oxide
underlying
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006548301A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007519239A (ja
JP2007519239A5 (enExample
Inventor
ウォン、ロバート
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JP2007519239A publication Critical patent/JP2007519239A/ja
Publication of JP2007519239A5 publication Critical patent/JP2007519239A5/ja
Application granted granted Critical
Publication of JP5527922B2 publication Critical patent/JP5527922B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6758Thin-film transistors [TFT] characterised by the insulating substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • H10D62/116Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2006548301A 2004-01-08 2005-01-06 直流ノード拡散領域の下に埋め込み酸化物を有さず、酸化物ホールを有する差別化soi構造 Expired - Fee Related JP5527922B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/754,320 US6958516B2 (en) 2004-01-08 2004-01-08 Discriminative SOI with oxide holes underneath DC source/drain
US10/754,320 2004-01-08
PCT/EP2005/050039 WO2005069373A1 (en) 2004-01-08 2005-01-06 Discriminative soi with oxide holes underneath dc source/drain

Publications (3)

Publication Number Publication Date
JP2007519239A JP2007519239A (ja) 2007-07-12
JP2007519239A5 JP2007519239A5 (enExample) 2007-11-22
JP5527922B2 true JP5527922B2 (ja) 2014-06-25

Family

ID=34739363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006548301A Expired - Fee Related JP5527922B2 (ja) 2004-01-08 2005-01-06 直流ノード拡散領域の下に埋め込み酸化物を有さず、酸化物ホールを有する差別化soi構造

Country Status (8)

Country Link
US (1) US6958516B2 (enExample)
EP (1) EP1706905A1 (enExample)
JP (1) JP5527922B2 (enExample)
KR (1) KR100956716B1 (enExample)
CN (1) CN1906762A (enExample)
IL (1) IL176686A (enExample)
TW (1) TWI339414B (enExample)
WO (1) WO2005069373A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7160788B2 (en) * 2004-08-23 2007-01-09 Micron Technology, Inc. Methods of forming integrated circuits
US7202513B1 (en) 2005-09-29 2007-04-10 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US7659172B2 (en) * 2005-11-18 2010-02-09 International Business Machines Corporation Structure and method for reducing miller capacitance in field effect transistors
JP4867396B2 (ja) * 2006-03-01 2012-02-01 セイコーエプソン株式会社 半導体装置及びその製造方法
US7482656B2 (en) * 2006-06-01 2009-01-27 International Business Machines Corporation Method and structure to form self-aligned selective-SOI
US7795910B1 (en) 2007-08-21 2010-09-14 Marvell International Ltd. Field-programmable gate array using charge-based nonvolatile memory
US8921190B2 (en) 2008-04-08 2014-12-30 International Business Machines Corporation Field effect transistor and method of manufacture
US7989893B2 (en) * 2008-08-28 2011-08-02 International Business Machines Corporation SOI body contact using E-DRAM technology
CN102064097B (zh) * 2009-11-17 2012-11-07 中国科学院上海微系统与信息技术研究所 一种混晶材料的制备方法及用该材料制备的半导体器件
CN101924138B (zh) * 2010-06-25 2013-02-06 中国科学院上海微系统与信息技术研究所 防止浮体及自加热效应的mos器件结构及其制备方法
CN101986435B (zh) * 2010-06-25 2012-12-19 中国科学院上海微系统与信息技术研究所 防止浮体及自加热效应的mos器件结构的制造方法
PT2446792E (pt) 2010-10-29 2015-02-18 Gruppo Cimbali Spa Peça de extremidade substituível para uma boca de descarga de vapor de uma máquina de café
CN102214684B (zh) * 2011-06-03 2012-10-10 清华大学 一种具有悬空源漏的半导体结构及其形成方法
US9892910B2 (en) * 2015-05-15 2018-02-13 International Business Machines Corporation Method and structure for forming a dense array of single crystalline semiconductor nanocrystals
US9722057B2 (en) * 2015-06-23 2017-08-01 Global Foundries Inc. Bipolar junction transistors with a buried dielectric region in the active device region

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8006339A (nl) * 1979-11-21 1981-06-16 Hitachi Ltd Halfgeleiderinrichting en werkwijze voor de vervaar- diging daarvan.
JPS577161A (en) * 1980-06-16 1982-01-14 Toshiba Corp Mos semiconductor device
JPS59119723A (ja) * 1982-12-27 1984-07-11 Toshiba Corp 半導体装置の製造方法
JPS61265859A (ja) * 1985-05-20 1986-11-25 Toshiba Corp 相補型mos半導体装置
US4683637A (en) * 1986-02-07 1987-08-04 Motorola, Inc. Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing
US4810664A (en) * 1986-08-14 1989-03-07 Hewlett-Packard Company Method for making patterned implanted buried oxide transistors and structures
JPH0794721A (ja) * 1993-09-24 1995-04-07 Nippon Steel Corp 半導体装置及びその製造方法
US5382818A (en) * 1993-12-08 1995-01-17 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode
US5841126A (en) * 1994-01-28 1998-11-24 California Institute Of Technology CMOS active pixel sensor type imaging system on a chip
US5489792A (en) * 1994-04-07 1996-02-06 Regents Of The University Of California Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
US5583368A (en) 1994-08-11 1996-12-10 International Business Machines Corporation Stacked devices
US5481126A (en) 1994-09-27 1996-01-02 Purdue Research Foundation Semiconductor-on-insulator electronic devices having trench isolated monocrystalline active regions
DE4441901C2 (de) * 1994-11-24 1998-07-02 Siemens Ag MOSFET auf SOI-Substrat und Verfahren zu dessen Herstellung
JPH08316335A (ja) * 1995-05-18 1996-11-29 Sony Corp 半導体装置およびその製造方法
US5712173A (en) 1996-01-24 1998-01-27 Advanced Micro Devices, Inc. Method of making semiconductor device with self-aligned insulator
US5873364A (en) * 1996-02-22 1999-02-23 Kopelowicz; Alberto Latex prophylactics
KR100226794B1 (ko) * 1996-06-10 1999-10-15 김영환 모스펫 제조방법
KR100281109B1 (ko) * 1997-12-15 2001-03-02 김영환 에스오아이(soi)소자및그의제조방법
US6214653B1 (en) * 1999-06-04 2001-04-10 International Business Machines Corporation Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate
US6333532B1 (en) * 1999-07-16 2001-12-25 International Business Machines Corporation Patterned SOI regions in semiconductor chips
KR100304713B1 (ko) 1999-10-12 2001-11-02 윤종용 부분적인 soi 구조를 갖는 반도체소자 및 그 제조방법
US6376286B1 (en) 1999-10-20 2002-04-23 Advanced Micro Devices, Inc. Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer
US6429099B1 (en) * 2000-01-05 2002-08-06 International Business Machines Corporation Implementing contacts for bodies of semiconductor-on-insulator transistors
US6287901B1 (en) 2000-01-05 2001-09-11 International Business Machines Corporation Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors
KR100356577B1 (ko) 2000-03-30 2002-10-18 삼성전자 주식회사 에스오아이 기판과 그 제조방법 및 이를 이용한에스오아이 엠오에스에프이티
JP2002208696A (ja) * 2001-01-11 2002-07-26 Seiko Epson Corp 半導体装置及びその製造方法
JP4352616B2 (ja) 2001-02-05 2009-10-28 株式会社デンソー 半導体力学量センサとその製造方法
US6531375B1 (en) * 2001-09-18 2003-03-11 International Business Machines Corporation Method of forming a body contact using BOX modification
US6936522B2 (en) 2003-06-26 2005-08-30 International Business Machines Corporation Selective silicon-on-insulator isolation structure and method

Also Published As

Publication number Publication date
US20050151193A1 (en) 2005-07-14
TW200524047A (en) 2005-07-16
JP2007519239A (ja) 2007-07-12
TWI339414B (en) 2011-03-21
IL176686A0 (en) 2006-10-31
CN1906762A (zh) 2007-01-31
KR20060123434A (ko) 2006-12-01
IL176686A (en) 2010-12-30
WO2005069373A1 (en) 2005-07-28
US6958516B2 (en) 2005-10-25
KR100956716B1 (ko) 2010-05-06
EP1706905A1 (en) 2006-10-04

Similar Documents

Publication Publication Date Title
US6677645B2 (en) Body contact MOSFET
US7060553B2 (en) Formation of capacitor having a Fin structure
US5166084A (en) Process for fabricating a silicon on insulator field effect transistor
KR100562539B1 (ko) 벌크 씨모스 구조와 양립 가능한 에스오아이 구조
CN101026157B (zh) 半导体器件及其制作方法
CN102804376B (zh) 充电保护装置
JP3965064B2 (ja) ボディ・コンタクトを有する集積回路の形成方法
JP5527922B2 (ja) 直流ノード拡散領域の下に埋め込み酸化物を有さず、酸化物ホールを有する差別化soi構造
KR20010096517A (ko) 반도체 장치, 그 제조 방법 및 더미 영역의 배치 방법
US9286425B2 (en) Method, structure and design structure for customizing history effects of SOI circuits
KR19990088443A (ko) Soi반도체장치및그제조방법
US6469350B1 (en) Active well schemes for SOI technology
JP4340831B2 (ja) Soi素子の基板構造及びその製造方法
US7566934B2 (en) Semiconductor device to suppress leak current at an end of an isolation film
EP0989613B1 (en) SOI transistor with body contact and method of forming same
US8963211B2 (en) Method, structure and design structure for customizing history effects of SOI circuits
CN117712119A (zh) 触发器可控硅整流器
KR100226784B1 (ko) 반도체 소자의 제조방법
JP3632565B2 (ja) 半導体装置の製造方法
US6440832B1 (en) Hybrid MOS and schottky gate technology
WO2002025701A2 (en) Body-tied silicon on insulator semiconductor device structure and method therefor
KR100505400B1 (ko) 에스 오 아이 기판에 형성되는 반도체 디바이스 및 그 제조방법
JPH11317517A (ja) 半導体装置およびその製造方法
JP2008211155A (ja) 半導体集積回路及び製造方法
KR20000066450A (ko) 정전기 보호용 트랜지스터 및 그의 제조 방법

Legal Events

Date Code Title Description
A529 Written submission of copy of amendment under article 34 pct

Free format text: JAPANESE INTERMEDIATE CODE: A529

Effective date: 20070615

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071001

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071001

A072 Dismissal of procedure [no reply to invitation to correct request for examination]

Free format text: JAPANESE INTERMEDIATE CODE: A072

Effective date: 20071023

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110629

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110705

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110809

RD12 Notification of acceptance of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7432

Effective date: 20110809

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20110810

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120207

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120423

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120605

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120913

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20120925

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20121019

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131028

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131121

RD14 Notification of resignation of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7434

Effective date: 20140329

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140415

R150 Certificate of patent or registration of utility model

Ref document number: 5527922

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees