TWI314775B - A film and chip packaging process using the same - Google Patents

A film and chip packaging process using the same Download PDF

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Publication number
TWI314775B
TWI314775B TW095141502A TW95141502A TWI314775B TW I314775 B TWI314775 B TW I314775B TW 095141502 A TW095141502 A TW 095141502A TW 95141502 A TW95141502 A TW 95141502A TW I314775 B TWI314775 B TW I314775B
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TW
Taiwan
Prior art keywords
wafer
film
resin layer
substrate
patent application
Prior art date
Application number
TW095141502A
Other languages
English (en)
Other versions
TW200822304A (en
Inventor
Yuehming Tung
Kuo Yang Sun
Chia Ming Yang
Hungtai Mai
Hui Chi Liu
Original Assignee
Orient Semiconductor Elect Ltd
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Publication date
Application filed by Orient Semiconductor Elect Ltd filed Critical Orient Semiconductor Elect Ltd
Priority to TW095141502A priority Critical patent/TWI314775B/zh
Priority to KR1020070008871A priority patent/KR100841450B1/ko
Priority to US11/979,792 priority patent/US20080113472A1/en
Priority to JP2007291699A priority patent/JP2008124472A/ja
Publication of TW200822304A publication Critical patent/TW200822304A/zh
Application granted granted Critical
Publication of TWI314775B publication Critical patent/TWI314775B/zh

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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Dicing (AREA)
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1314775 • · ‘ · ’ 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種膠膜，特別是關於一種晶片封裝製程中 所使用之膠膜。 【先前技術】 習用之晶片堆疊之封裝構造中，如第1圖所示，該封裝構 造包含一基板10、一下層晶片20、—虚設晶片（dummy die)3〇 鲁及一上層晶片4〇。該下層晶片20係藉由一黏膠22固定該基 板1 〇上’且該下層晶片20之上表面的兩侧邊緣設有複數個 鋁接墊24,其係藉由複數條第一銲線26電性連接於該基板 之複數偏接塾12。§亥虛設晶片30係藉由一黏膠32固定於 該下層晶片20上，並界定該第一銲線26所需的空間，例如 約5mils以上之尚度。該上層晶片係藉由一黏膠42固定 於該虛設晶片30上，且該上層晶片40之上表面48設有複數 個鋁接墊44，其係藉由複數條第二銲線46電性連接於該基 _板1 0之該複數個接塾12，如此兩晶片20、40係堆疊於該基 板10上。然而，此封裝構造之成本較高及封裝之製程時間較 長。再者’該虛設晶片與該黏膠之膨脹係數係不匹配，因此 於封膠處理後該虛設晶片與該黏膠之結合界面的結構應力會 增加’進而產生晶片裂開（die erack)並降低封裝之良率。該封 裝之良率一般約為介於30%與40%之間。 另一種晶片堆疊之封裝構造中，如第2圖所示，該封裝構 造包含一基板110、一第—晶片12〇、—非導電膠13〇、一第 二晶片140及複數個支撐球132。該第一晶片12〇具有相對 5 1314775 * * 1 之上表面及下表面’該下表面係固定於該基板上。該非 導電膠130係配置於該第一晶片12〇之上表面上。該第二晶 片140具有相對之上表面及下表面，其中該下表面係藉由該 非導電膠130固定於該第一晶片120之上表面上，該複數支 樓球132係配置於該非導電膠130中，並支撐該第二晶片 140 〇雖然此種封裝構造藉由增加非導電膠與晶片間之黏著面 積，以減少於封膠處理後之結構應力集中，因而可避免晶片 裂開，並利用複數支撐球界定銲線所需的空間。然而，該非 魯導電膠130需於每一次進行黏晶（die attach)時塗佈，不但增 加封裝之製程時間，且由於非導電膠130為液態，因而每^ 塗佈之出膠量不易控制，仍然容易造成該第二晶片14〇於黏 著時出現傾斜的現象。 此外’另一種習知之晶片堆疊之封裝製程，如中華民國專 利第1240392號之「多晶片同尺寸堆疊之封裝製程」，其係在 —晶圓之背面形成一半固化樹脂，再將該晶圓切割成複數個 第一晶片，以其中一具有半固化樹脂之第一晶片黏接至一基 馨板或一第二晶片之主動面，複數個銲線係電性連接該第一晶 片與該基板；在第一晶片對第二晶片之堆疊黏合時’在兩晶 片間之該半固化樹脂係受熱熔融而包附該些銲線，使得在一 封裝厚度内可堆疊更多同尺寸之晶片。雖然利用該半固化樹 脂可避免於每次黏晶時塗佈以縮短製程時間，但由於該半固 化樹脂於加熱後形成熔融態，當黏晶之應力過大時，會有無 法維持該第一晶片與該基板或第三晶片Fb1之高度得問題，而 使得該第一晶接觸到銲線因而降低製程良率。 基於上述原因，其確實仍有必要進一步改良上述晶片堆疊 6 1314775 « 之封裝構造，以解決上述習知技術中之問題。 【發明内容】 本發明目的之一在描 # ^ ^ . k供一種膠膜及使用該膠膜之晶片封 =製程，其可増加膠膜與晶片間之黏著面積，以減少於封膠 處理後之應力集中’而具有避免晶片裂開之功效。 本發明另—目的在提供—種膠膜及使用該膠膜之晶片封 裝衣程，其係藉由於一膠膜中配置複數圓弧彈性體以支撐， 晶片，用以界定銲線或元件所需之空間。 ，發明再一目的在提供一種勝膜及使用該膠膜之晶片封 •程，其係藉由於晶圓上黏附—膠膜，而避免於每次黏晶 時塗佈黏膠，俾以縮短製程時間。 本表月再目的在提供—種膠膜及使用該膠膜之晶片封 裝製程’由於膠膜具有固定體積及高度，因而於黏晶時<避 免高度不易控制之問題，俾以增加製程良率。 ，為達上述目的’本發明之膠膜，其主要包含一可移除之基 材、-樹脂層及複數圓弧彈性體。該樹脂層為一半固化樹脂， 其於-第-溫度以上為具黏性之半熔融狀態，其於一第二溫 度以下為不具黏性之固態，該樹脂層黏設於該基材上；該等 圓弧彈性體配置於該樹脂層中。 本發明另提供-種晶片封裝製程，其利用一膠膜作為一晶 片黏著材料’該膠膜係由一半固化樹脂層結合一基材所形 成’且於該樹脂層中配置有複數圓孤彈性體，該晶片封 程包含下列步驟.·提供-半導體晶圓.，其具有—主動面及__ 1314775 背面丄該主動面之内形成有複數個接塾；形成該膠膜於該晶 圓之背面；切割該晶圓以形成複數晶片，其中，該等晶片之 背面黏附有該膠膜；去除該等晶片中之—第一晶片背面之膠 膜之基材，及將位於該第__晶片背面之樹脂層黏^於一承載 體上；因此，藉由該等圓弧彈性體使該第一晶片與該承載體 間界定出一預設空間。 【實施方式】 為了讓本發明之上述和其他目的、特徵、和優點能更明 3下文特舉本發明實施例，並配合所附圖示，作詳細說明 •睛參照第3a圖所示，其揭示本發明第一實施例之膠臈 \ ^ 3可移除之基材32、一樹脂層34以及複數 圓弧彈14體36配置於該樹脂層34巾。該膠膜3係用於一半 導體晶片封裝_兹φ 从_ & 作為一晶片之黏接材料。該基材32之 =施例可為—BT基板（BTsubstrate)或一膠帶（tape);當其為 | 、.基板時，其可利用—環氧樹脂（epoxy)與該樹脂層34結 其為-膠帶時’可為-紫外線照射膠帶（uvtape)或藍 帶（e^e)，且具有可撓性。該基材32上結合混有該圓 弧彈性體36之樹脂層34。為了能夠適用於晶片之封裝製程 該基材32須至少能承受攝氏85度之高溫。 5玄f脂層34之-種實施例可為-半固化樹脂，例如由ί| t j P〇Xy resin)及酚樹脂（phenol resin)混合而成之拣 二、較：於常溫時〔例如攝氏“度以下〕為固態且不具象 而於阿溫時〔例如攝氏.85度以上〕時為半溶融態且具肩 1314775 • h 黏性；該圓弧彈性體36較佳為耐熱材質所製，例如橡膠，其 包含兩種不同直徑之圓球體，其分別爲小尺寸圓球體361以 及大尺寸圓球體362，該小尺寸圓球體361係用以間隔該大 尺寸圓球體362，且其數目較佳係小於全部圓弧彈性體數目 之20°/。；該大尺寸圓球體362係用以於半導體晶片之封裝製 程中’界定一銲線或一被動元件之高度，因而其直徑較佳係 至少為3至8miis〔 imii=25 4微米〕。於本實施例中，該樹 脂層34之厚度須大於該大尺寸圓球體362之直徑，且較佳係 大於4至1〇微米（micr〇 meter)，以使得當該樹脂層μ受熱 而形成半熔融態時，允許該等圓弧彈性體36在該樹脂層Μ 中重新均勻的排列。該樹脂層34與該等圓弧彈性體36較佳 係以非導電材料所製成。 請參照第3b圖所示，其揭示本發明第二實施例之膠膜 3必須說明的是於本實施例令，與第一實施例相同之元件 係以相同之符號表示。本實施例與第一實施例之差異在於， 該圓狐彈性體36除包含小尺寸圓球體361以及大尺寸圓球體 3 62之外，另包含複數橢球體363，其長軸較佳係相等於該大 尺寸圓球體362之直徑，其功用之詳細說明將於以下之段落 _描述，該樹腊層34之厚度須大於該大尺寸圓球體362之直 輕，且較佳係大於4至1〇微米（micr〇meter)。於本實施例中， 該等該圓弧彈性體36同樣為耐熱材質所製，例如橡膠，且該 樹腊層34與該等圓弧彈性體36同樣係以非導電材料所製成。 請參照第3c圖所示’其揭示本發明第三實施例之谬膜 3 ’於本實施例中，與第—實施例相同之元件係以相同之符 號表示。本實施例與第-及第二實施例之差異在於，該圓弧 9 1314775. 彈性體36係為同尺+ 勹丨』尺寸之圓球體〔例如第— 大尺寸圓球體362〕，A 及第一實％例之 定㈣赤，由包 、R樣用以於一晶片封裝製程中，界 疋一鋅線或一被動元件古 m二 5 β .丨间度，因而其直徑較佳係至少為3 至8mils。於本實施你丨由 κ 、中，該树脂層34之厚度同樣須大於該 圓弧彈性體3 6之直溽，β # /+〆， 較佳係大於4至1〇微米。本實施 例之該等圓弧彈性體36較佳 革貫 翏佳為耐熱材質所製，例如橡膠，且 該樹脂層34與該等圓弧彈性 坪f玍體；3 6係以非導電材料所製成。 请參照第4、第5 a 5 s f iv β /： -r 至5f以及6a至6b圖所示，其揭示利 用本發明各實施例之該等膠膜 矛膠膜3、3或3於—晶片封裝製程 之流程圖及其示意圖’其中，係利用本發明各實施例之穋膜 3、3’或3’’作為晶片黏接材料，該晶片封裝製程包含下列步 驟：提供-半導體晶圓，其具有一主動面及一背面，該主動 面上形成有複數接墊〔步驟2〇1〕；形成一膠膜於該晶圓之 背面〔步驟202〕；切割該晶圓，以形成複數晶片，其中該 等晶片之背面黏附有該膠膜〔步驟2〇3〕；去除該等晶片中 之一第一晶片背面之膠膜之基材〔步驟2〇4〕；將位於該第 籲一晶片背面之樹脂層黏設於一承載體上〔步驟2〇5〕，因此， 藉由該等圓弧彈性體使該第一晶片與該承載體間界定出一預 設空間；電性連接該晶片及承載體〔步驟206〕；及以一封 膠體進行密封〔步驟207〕^此外，必須說明的是，於以下 各圖之說明中，相同之元件間係以相同之標號表示。 請參照第4及5 a圖所示，於本發明之晶片封裝製程中， 第一步為提供一半導體晶圓（wafer)42，其具有一主動面42a 及一背面42b，該主動面42a上具有複數接塾421〔步鄉 201〕。將該晶圓42之主動面42a放置於一晶圓承載台44 1314775 I η 上，並利用一晶圓研磨工具90研磨該晶圓42之背面， 以將該晶圓之厚度研磨至一預定厚度，此預定厚度通常是 1 mil以上。 請參照第4及5b圖所示，當該晶圓42研磨至上述預定厚 度後，接著將本發明各實施例之該膠膜3’黏設於該晶圓42 之背面〔步驟202〕。必須注意的是，於第53至紂圖之說明 中，係以本發明第二實施例之該模材3,來進行說明，而使用 本發明其他實施例之模材3或3，，所進行之封裝製程與此類 鲁似，於本文中不再詳加敘述。如前所述，由於該膠膜3，於常 溫〔攝氏45度以下〕時為固態’必須將其放置於—固化爐 (curing oven)加熱至高溫〔例如攝氏85度以上〕時才呈現熔 融態並具有黏性’因而欲將該膠膜3,黏附於該晶圓42上時， 須先經過加熱處理，但為避免該膠膜3,反應過度，於此加熱 過程中僅加熱报短之時間，其時間長短取決於使該膠膜3，呈 現半·熔融態並能夠黏附於該晶圓42之時間，例如2秒。 睛參照第4及5c圖所示，接著以一切割刀92(dieing blad〇 切割該晶圓42，以形成複數晶片，並假設其中之一晶片為第 —晶片422,因而該等晶片〔包含該第一晶片422〕之背面皆 黏附有該膠膜3’，且每一晶片之主動面皆具有複數接墊42ι 〔步驟203〕。其中，該等晶片之實施例可為動態隨機存取 °己隱體（DRAM)、靜態隨機存取記憶體（sraM)、快閃記憶體 (Flash)、雙倍資料記憶體（DDR)或Rambus記憶體等之記憶晶 片、微處理器、邏輯晶片或射頻晶片等等。 請參照第4及5d圖所示，在將該第一晶片422設置於一 1314775 * 售 承載件之前，須先將該膠膜3’之基材32移除〔步驟204 ]; 若該基材32為一紫外光照射膠帶，則必須將該基材32照射 紫外光UV後方可去除，但若該基材32為藍膠帶（biue tape) 或BT基板，則可直接移除。接著利用一自動化選取及安放 裂置94將該第一晶片422放置於一預定之承載體52。 請參照第5e圖所示，接著將該第一晶片422經由 3’設置於一承載體52上〔步驟205〕，於本發明之各實施例 中，該承載體52可為一基板、一導線架或一晶片〔第二晶 片〕，且欲使該第一晶片422背面之樹脂層3 4黏附於該承載 體52上時，亦必須經過一高溫之短時間加熱，例如加熱至攝 氏85度以上且經過2秒，則該第一晶片422可預黏於該承載 體52上。當該承載體52為一基板時，較佳使用本發明第二 實施例之膠膜3,做為該第一晶片422之黏著材料，亦即該等 圓弧彈性體包含複數小尺寸圓球M 361、大尺寸圓球體如 及橢球體363,該等大尺寸圓球體362及橢球體363藉由該 小尺寸圓球體361間隔後，當樹脂層34欲黏附於該承載體 52上時，由於該樹脂層34經加熱形成半融熔態，該等大尺 寸圓球體362及橢球體363則可在其中自由移動以輕易的避 開該承载體52上之元件522,例如被動元件，並可藉由該大 尺寸圓球體362界定出該等元件522所需之高度，若該橢球 體363剛好位於該等元件522之上方時，由於該擴球體⑹ 表面呈圓弧狀，其亦可藉由轉動方向，如第&圖所示，而使 得該第-晶片422能夠水平的設置於該承載體52上。因此， 即使黏晶時之應力過大’也可經由該等大尺寸圓球體加唯 持黏晶之平整度。接著便可利用複數第—銲線⑶電性連接 12 1314775 礒第一晶片422之接墊421及該承載體S2〔步驟2〇6〕。 請參照第5f圖所示，最後再以一封勝體6〇密封該第一晶 2 422及該第-銲線524，並放置固化爐〔未綠示〕中加熱 一段較長時間，例如攝氏85度以上且時間持續㈣秒，此時 預魏於該承載體52之樹脂層34經過此—步驟後則完全反 應’以使該承倾52舆樹脂層34完全黏合，並完成本發明 之晶片封裝製程〔步驟207〕。 請參照第6a圖所示，當該承載體52為—晶片〔第二晶 片〕時，該第二晶片上通常設置有複數第二銲線s26且其2 置於-基板或導線架上，此時可選擇使用本發明第—實施例 之膠膜3做為該第—晶片422之黏著材料，亦即該等圓孤彈 性體包含複數小尺寸圓球體361及大尺寸圓球體362，該等 大尺寸圓球體362藉由該小尺寸圓球體361間隔後，當樹脂 層34欲黏附於該承載體52上時，由於該樹脂層34經二熱^ 成半融熔態，該等大尺寸圓球體362則可在其中移動以輕易 的避開該承載體52上之第二銲線526，且可藉由該大尺寸圓 球體362界定出該第二銲線526所需之高度。因此，即使黏 晶時之應力過大，也可經由該等大尺寸圓球體362維持黏晶 之平整度。接著便可利用複數第一銲線524電性連接該第Z 晶片422之接藝421及該基板或導線架〔步驟〕。此外 當該承載體52為一晶片時，仍可使用本發明第二實施例之膠 膜3’及第三實施例膠膜3’’作為該第一晶片422之黏著材料。 請參照第6b圖所示，最後同樣以一封膠體6〇密封該第一 晶片422、第一銲線524，承載体52及第二銲線526，並放 13 1314775 上：t爐令[未繪示〕加熱一段較長時間，例如攝氏85 3%持續120秒，此時預黏於該承載體52之樹脂層 34二：步驟後則完全反應，以使該承載體52舆樹脂層 凡王黏〇，並完成本發明之晶片封裝製程〔步驟2〇7〕。 曰κ "^因帛1圖所示之習用晶片堆疊之封裝構造具有 曰曰片裂開及製程時間較長之問題，而第2圖所示之構造因具 ，黏膠之出膠量不易控制，如此會造成黏晶時出現傾斜之問 s才較於第1及2圖之習用晶片堆疊之封裝構造，本發明 各實施例之膠膜(如第3a_3c圖所示)藉由於該等膠媒中配置 彈性體’並支撐一晶片，可用以界定銲線或元件所 需的工間，並可縮短封裝之製程時間。 雖然本發明已以前述趟接眘 j 4較佳實施例揭不，然其並非用以限定 發明，任何熟習此技藝者，在不脫離本發明之精神和範圍 =，當可作各種之更動與修改。因此本發明之保護範圍當視 後附之申請專利範圍所界定者為準。 14 1314775 【圖式簡單說明】 第1圖：習用之晶片堆疊之封裝構造。 第2圖：另一習用之晶片堆疊之封裝構造。 第3a圖·本發明第一實施例之膠膜之示意圖。 第3b圖：本發明第二實施例之膠膜之示惫圖。 第3c圖·本發明第三實施例之膠膜之示意圖。
第4圖：利用本發明實施例 圖0 之膠膜之晶片封 程之流程 第5a〜5f圖：利用本發 截面示意圖， 明實施例之膠膜之晶片封震製程 其中該承載體為一基板。 之 第6 a〜6b圖：利用士 另一承發明實施例之膠膜之晶片封裝製程之 截面示意圖，其中該承載體為一晶片。 【圖號說明】 10基板 20下層晶片 24鋁接墊 3 0虛設晶片 42黏膠 46第二銲線 Π0基板. 12接墊 22黏膠 26第一銲線 40上層晶片 44鋁接墊 4 8上表面 120第一晶片 15 1314775 130非導電膠 140第二晶片 32基材 36圓弧彈性體 3 62大尺寸圓球體 42晶圓 42b背面 422第一晶片 52承載體 524第一銲線 60封膠體 90晶圓研磨工具 94選取及安放裝置 132支撐球 3 ' 3’、3’’ 膠膜 34樹脂層 361小尺寸圓球體 363橢球體 42a主動面 421接墊 44晶圓承載台 522元件 526第二銲線 UV紫外光 92切割刀 201〜207步驟
16

Claims (1)

1314775 * r 十、申請專利範圍： 1、 一種膠膜，其包含： 一可移除之基材； 一樹脂層’黏設於該基材上，該樹脂層為一半固化樹脂， 於—第一溫度以上為具黏性之半熔融狀態，且該樹脂層於 一第二溫度以下為不具黏性之固態；及 _ 複數圓弧彈性體，配置於該樹脂層中。 2、 依申睛專利範圍第1項之膠膜，其中該基材為BT基板。 3、 依申請專利範圍第1項之膠膜，其中該基材具可撓性。 4、 依申請專利範圍第3項之膠膜，其中該基材為紫外線照射 膠 (UV tape)或藍膠帶（biue tape)。 5、 依申請專利範圍1項之膠膜，其中該第一溫度為攝氏85 度。 依申請專利範圍第1項之膠膜，其中該第二溫度為攝氏 • 45 度。 7、 依申請專利範圍第1項之膠膜’其中該圓弧彈性體包含兩 種不同直徑之圓球體’其分別為大尺寸圓球體以及小尺寸 圓球體。 8、 依申請專利範圍第7項之膠膜，其中該小尺寸圓球體用以 間隔該大尺寸圓球體。 9、 依申請專利範圍7項之膠膜，其中該樹脂層界定一厚度， 且該樹脂層之厚度大於該大尺寸圓球體之直徑。 17 1314775 10、 依申請專利範圍第9項之膠膜，其中該樹脂層之厚度 大於該大尺寸圓球體之直徑4至丨〇微米。 11、 依申請專利範圍帛7項之膠膜，其中該小尺寸圓球體 之數目小於全部圓孤彈性體數目之2〇%。 12、 依申請專利範圍第1項之膠膜，其中該圓弧彈性體包 含兩種不同直徑之圓球體及複數橢球體，該不同直徑之圓 球體分別為大尺寸圓球體以及小尺寸圓球體。 13 '依申請專利範圍第12項之膠膜，其中該等橢球體之長 軸長度等於該大尺寸圓球體之直徑。 14、 依申請專利範圍第13項之膠膜，其中該樹脂層界定一 厚度’其中該樹脂層之厚度大於該大尺寸圓球體之直徑。 15、 依申請專利範圍第14項之膠膜，其中該樹脂層之厚度 大於該大尺寸圓球體之直徑4至1〇微米。 16 '依申請專利範圍第12項之膠膜’其中該小尺寸圓球體 用以間隔該大尺寸圓球體及該橢球體。 17、依申請專利範圍第12項之膠膜，其中該小尺寸圓球體 之數目小於全部圓弧彈性體數目之20%。 18 依申請專利範圍第1項之勝膜，其中該圓弧彈性體為 耐熱材質所製。 19、依申請專利範圍第18項之膠膜，其中該圓弧彈性體為 橡膠所製。 2 0 依申請專利範圍第1項之膠膜，其中該圓弧彈性體及 樹脂層為非導電材料。 . 18 1314775 , ♦ 21、 依申請專利範圍第1項之膠膜，其中該基材至少可承 受85度攝氏溫度。 22、 依申請專利範圍第1項之膠膜，其中該圓弧彈性體為 相同尺寸之圓球體。 23、 依申請專利範圍第22項之膠膜，其中該樹脂層界定一 厚度，其中該樹脂層之厚度大於該圓球體之直徑4至1〇 微米。 籲24、 一種晶片封裝製程’其利用一膠膜作為一晶片黏著材 料’該膠膜係由一樹脂層結合一基材所形成，該樹脂層為 一半固化樹脂’於一第一溫度以上為具黏性之半熔融狀 態’另於一第二溫度以下為不具黏性之固態，且於該樹脂 層中配置有複數圓弧彈性體，該晶片封裝製程包含下列步 驟： 提供一半導體晶圓，具有一主動面及一背面，該主動 面之内形成有複數個接墊； φ 形成該膠膜於該晶圓之背面； 切割該晶圓形成複數晶片，其中該等晶片之背面黏附 有該膠膜； 去除該等晶片中之一第一晶片背面之膠膜之基材；及 將位於該第一晶片背面之樹脂層黏設於一承載體上； 因此，藉由該等圓弧彈性體使該第一晶片與該承载體 間界定出一預設空間。 25、依申靖專利範圍第24項之晶片封裝製程，其中於提供 19 1314775 二半導體晶圓之步驟中，該半導體晶圓預純研磨至 定厚度。 %、依專鄉心24項之^„録，其中於去除 該等晶片背面之膠膜之基材步驟卜若該膠膜為紫外光昭 射躁帶，則去除該基材之前另包含下列步驟： 於該基材。 π糸外尤 〜依申ff專利㈣第24項之晶片封裝餘，其中 28 該晶圓之背面步驟，另包下列步驟:加熱該膠膜 第-溫度以上’以使該膠臈黏設於該晶圓之背面。 體為一基板、一導線架或一第二晶片 ::=·利範圍第24項之晶片封裝製程，其中該承載 29、依申請專利範圍第24項之晶另封 該第一晶Η# -i, 衣裏程其令於黏韻 弟日日片於一承载體步驟之 上相斗_ 力a含下列步驟： 加熱該膠膜至一第—溫度以上。 I依申請專利範圚第”或 該第一溫度為攝氏85度。 < 阳片封裝製程，其中 31、 依申請專利範圍第 時間為2秒。 、之晶片封裝製程，其中該加熱 32、 依申請專利範圍第24 彈性體包含兩種不 項之晶片封裝製程，其中該圓弧 體以及小尺寸圓埭體。餐之圓球體’其分別為大尺寸圓球 33、依申請專利範園第& 於該第-晶月背 項之晶片封裝製程，其中於將位 樹脂層黏設於-承載體上之步驟 20 1314775 * < 中，忒承載體為一第二晶片且該第二晶片上設有複數第二 接墊及第二銲線，該大尺寸圓球體具有—預設直徑，以界 定該第二銲線所需之空間。 34、依申請專利範圍第33項之晶片封裝製程，另包含下列 步驟： 以複數第一銲線電性連接該第一晶片及該基板；及 以一封膠體密封該第一晶片、第一銲線、第二晶片及第 | 二銲線。 35、 依中請專利範圍第24項之晶月封裝製程，其中該圓弧 彈性體包含兩種不同直徑之圓球體及複數橢球體，該不同 直t之圓球體分別為大尺寸圓球體以及小尺寸圓球體，且 該等橢球體之長軸長度等於該大尺寸gj球體之直程。 36、 依申請專利範圍第35項之晶片封裝製程，#中於將位 於該第一晶片背面之樹脂層黏設於一承載體上之步驟 中，該承載體為一基板且該基板上設有複數個被動元件， ，該大尺寸圓球體具有一預設直徑，用以界定該等被動元件 所需之空間。 37、 依申請專利範圍第36項之晶片封裳製程，g包含下列 步驟： 以複數第一銲線電性連接該晶片及該基板；及 以一封膠體密封該第一晶片及該第一銲線。 21
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI341576B (en) * 2007-01-24 2011-05-01 Chipmos Technologies Inc Chip package reducing wiring layers on substrate and its carrier
JP5838881B2 (ja) * 2012-03-27 2016-01-06 富士通株式会社 光射出部材の実装方法及び実装装置
CN111987066B (zh) * 2020-08-25 2022-08-12 维沃移动通信有限公司 芯片封装模组及电子设备
CN115050653B (zh) * 2022-08-16 2022-12-30 宁波芯健半导体有限公司 Soi芯片的晶圆级封装方法、系统及存储介质

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3800192A (en) * 1970-08-11 1974-03-26 O Schaerli Semiconductor circuit element with pressure contact means
US5232962A (en) * 1991-10-09 1993-08-03 Quantum Materials, Inc. Adhesive bonding composition with bond line limiting spacer system
US5291061A (en) * 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
US5323060A (en) * 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
US5721452A (en) * 1995-08-16 1998-02-24 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
MY118036A (en) * 1996-01-22 2004-08-30 Lintec Corp Wafer dicing/bonding sheet and process for producing semiconductor device
KR19990033105A (ko) * 1997-10-23 1999-05-15 윤종용 반도체 패키지용 접착 테이프
JP3325000B2 (ja) * 1999-05-28 2002-09-17 ソニーケミカル株式会社 半導体素子の実装方法
JP3578110B2 (ja) * 2000-06-15 2004-10-20 セイコーエプソン株式会社 電気光学装置および電子機器
TW445610B (en) * 2000-06-16 2001-07-11 Siliconware Precision Industries Co Ltd Stacked-die packaging structure
US6333562B1 (en) * 2000-07-13 2001-12-25 Advanced Semiconductor Engineering, Inc. Multichip module having stacked chip arrangement
JP2002157959A (ja) * 2000-09-08 2002-05-31 Canon Inc スペーサの製造法およびこのスペーサを用いた画像形成装置の製造方法
JP4651799B2 (ja) * 2000-10-18 2011-03-16 日東電工株式会社 エネルギー線硬化型熱剥離性粘着シート、及びこれを用いた切断片の製造方法
TW459363B (en) * 2000-11-22 2001-10-11 Kingpak Tech Inc Integrated circuit stacking structure and the manufacturing method thereof
US20020098620A1 (en) * 2001-01-24 2002-07-25 Yi-Chuan Ding Chip scale package and manufacturing method thereof
US7074481B2 (en) * 2001-09-17 2006-07-11 Dow Corning Corporation Adhesives for semiconductor applications efficient processes for producing such devices and the devices per se produced by the efficient processes
US6847105B2 (en) * 2001-09-21 2005-01-25 Micron Technology, Inc. Bumping technology in stacked die configurations
US6731011B2 (en) * 2002-02-19 2004-05-04 Matrix Semiconductor, Inc. Memory module having interconnected and stacked integrated circuits
US20030160311A1 (en) * 2002-02-28 2003-08-28 Aminuddin Ismail Stacked die semiconductor device
KR20030075860A (ko) * 2002-03-21 2003-09-26 삼성전자주식회사 반도체 칩 적층 구조 및 적층 방법
JP3925389B2 (ja) * 2002-10-25 2007-06-06 松下電器産業株式会社 半導体装置組立用の樹脂接着材
JP3729266B2 (ja) * 2003-02-24 2005-12-21 セイコーエプソン株式会社 半導体装置の製造方法
JP2005012048A (ja) * 2003-06-20 2005-01-13 Shin Etsu Chem Co Ltd 半導体素子積層用接着基板及びその製造方法、並びに半導体デバイス
JP2006237483A (ja) * 2005-02-28 2006-09-07 Sumitomo Bakelite Co Ltd ダイシングシート機能付きダイアタッチフィルム及びそれを用いた半導体装置の製造方法及び半導体装置。
JP4976284B2 (ja) * 2005-03-30 2012-07-18 新日鐵化学株式会社 半導体装置の製造方法及び半導体装置
JP2007134390A (ja) * 2005-11-08 2007-05-31 Disco Abrasive Syst Ltd ウエーハの加工方法

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US20080113472A1 (en) 2008-05-15

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