1264125 九、發明說明： 【發明所屬之技術領域】 於 本發明係關於一種 一種具散熱片之晶 【先前技術】 曰日片封裝方式及結構，詳言之，係關 片封裝結構及其封裝方法。1264125 IX. Description of the invention: [Technical field of the invention] The present invention relates to a crystal with a heat sink [Prior Art] The package and structure of the Japanese wafer, in detail, the package structure and the packaging method thereof .
參考圖1A，其顯示習知具散熱片之晶片封裝結構之示意 圖'亥封衣結則包括-基板單元1〇1、一晶片^、複數條 導㈣、封膠材料13及-散^單元。該基板單元m 具-第-表面102。該晶片"具有一第一表面⑴及一第二 表面112’該第二表面112係相對於該第一表面⑴。該晶片 η之第，表面"2係貼附於該基板單幻〇1之該第一表面 02上。亥日日片！丄之§亥第—表面⑴係以該等導線η與該基 板单7L1G1之該第—表面1G2電性連接。該封膠材料Η用以 注入於該基板MUM及該散熱片單元⑽之間，形成該封 裝積體電路元件卜該散熱片單元14〇係為一平板結構，其 具有一第一表面142。該散熱片單元14〇之該第一表面142 八有複數個凹八141，該凹穴丨4丨係用以加強與封膠材料i 3 之附著力。 參考圖1B至1E，其顯示習知之晶片封裝方法示意圖。參 考圖1B，首先，提供一基板1〇，該基板1〇具有複數個晶片 11，每一晶片11具有一第一表面lu及一第二表面112，該 第二表面112係相對於該第—表面lu。該晶片丨丨之第二表 面112係貼附於該基板10之一第一表面1〇〇上。該晶片丨丨之 該第一表面111係以複數條導線12與該基板1〇之該第一表 100806.doc 1264125 面100電性連接。 耑埶片口田口 - , ^ 〆月又热方14中界定複數個 月文熱片早凡140(如虛線所示）， 構，具有—第#面14， Μ政熱片14係為一平板結 有複數1二之㈣—表面⑷具 模！:Γ’將該基板10及該散—模具中。該 :16’而該散熱片14係以真空吸附之方式置於上模二 注入一封膠材料13於該模且中 ^ 片14。 、/、中以包封該基板10及該散熱 爹考圖1E，待包封該基板1G及該散熱片 趙:8冷:結合後’將該封裝㈣自該模具，取出= 細衣體18以形成複數個如圖1A所示之封裝結構卜 上述習=附加散熱片之晶片封裝方式及結構之缺點如 第：片下之封膠材料13容易因結合不良而脫落。 该曰曰片10與該封膠材料13之黏著力不足。第 品之良率不高。 疋弟一，產 因提供—種創新且具有進步性之具散熱片之 曰曰片封衣方式及結構，以解決上述問題。 【發明内容】 構。該封裝結構包括具有一基板單元、一―,，—一 熱片單元及封膠材料。該基”成 有-第-表面，該曰“笛… 片具 曰曰片之弟一表面係以複數條導線與該基 本發明之一目的在於提供一種具散熱片之晶片封裳結 散 虛擬晶片 100806.doc 1264125 板單，電性連接。該虛擬晶片係設置於該晶片之上。該散 熱片：几設置於該虛擬晶片之上。該封膠材料用以封包該 基板單元、該虛擬晶片及該散熱片。 本發明之另—目的在於提供—種具散熱片之晶片封裝方 :其^括.⑷提供-基板，該基板甲界^複數個基板單元， 板具有複數個晶片’該等晶片設置於該基板之一第一 表面二’母一晶片具有-第-表面，該晶片之第一表面係 丄亥“片之上’·⑷設置-網狀散熱片於該等虚 ::片之上’該散熱片中界定複數個散熱片單元暮該 基板、該等虛擬晶片及該散熱片置於 膠材料於該模具中，以Μ — I、中，⑷注入封 / ^ 十衣體，及（f)切割該封裝體 以形成複數個封裝結構，每一 一卢糍曰Η . 母封衣、、“冓具有-基板單元、 虛擬日日片、一散熱片單元及封膠材料。 料Π 散熱片之晶片封褒方式及結構，使封膠材 枓牙過该放熱片之網格與該虛擬晶片結合，以加 擬晶片與該封膠材料 A虛 料…， 之黏者力，避免散熱片上下之封膠材 枓、、、“不良而脫落，藉以提升產品可靠产。 【實施方式】 又 參考圖2AH本㈣具散“ 意圖。該封裝結構2包括—基板單元2〇ι、— :^構^ 條導線22、一虛擬晶μ π 日日片21、设數 基板單元一第Γ 一放熱片單元251及封膠24。該 211及―2。該晶片21具有一第一表面 、2，該第二表面212係相對於該第一表面 100806.doc 1264125 ^ x a曰片""1之第一表面2 1 2係貼附於該基板單元20 1之該 第表面2〇2上。該晶片21之該第一表面211係以該等導線 22與該基板單元201之該第一表面2〇2電性連接。 、X虛擬曰曰片设置於該晶片21之上。該虛擬晶片u係用 、支撐4放熱片單元251及隔離該等導線22及該散熱片單 :251。該散熱片單元251係為—網狀結構，設置於該虛擬 阳2 23之上。該封膠材料24用以封包該基板單元201、該虛 擬晶片23及該散熱片單元251，形成該封裝結構二。 立參考圖2B至2F，為本發明具散熱片之晶片封裝方法之示 意圖。參相2B，首先，提供—基㈣，該基板2()中界定 稷數個基板單元20卜該基板2〇具有複數個晶片2卜該等晶 片21係5又置於該基板20之一第一表面200上。每一晶片21 具有一第一表面211。該晶片21之該第一表面2U係以複數 條導線22與該基板2〇之該第一表面2〇〇電性連接。 多考圖2C，設置複數個虛擬晶片23於相對應之該等晶片 21之上。參考圖2〇，提供一散熱片25，該散熱片中界定 複數個散熱片單元251(如虛線所示），該散熱片邱置於該 等虛擬晶片23上方。該散熱片25係為一導熱性之金屬材質 (例如銅或㈤之㈣結構。該散熱片25之網格％可讓該封膠 ㈣24通過，以加強該等虛擬晶片23與該封膠材料μ之點 者力。該等虛擬晶片23係用以支撐該散熱片25及隔離該等 導線22及該散熱片25。 茶考圖2E，將該基板20、該等虛擬晶片23及該散熱片25 置於-核具27中。注人封膝材料24於該模具”中。該封膠 I00806.doc 1264125 材料24係穿過該散熱片25之網格26(參考圖2d)與該等虛擬 晶片23結合’藉以封包該基板2〇、該等虛擬晶⑶及該散 熱片25。 參考圖2F，將包封該基板20、該等虛擬晶片23及該散埶 片25之封裝體28自該模具27中取出，切割該封裝體28以； 成複數個如圖2A所示之封裝結構2。 夕 利用本發明具散熱片之晶片封裝方式及結構，使封膠材 心穿過該散熱片25之網格26與該該等虛擬晶片…士 a， 以加強該等虛擬晶片23與該封膠材料24之黏著力，避：散 熱上下之封膠材料24結合不良而脫落，藉以提升產二 可罪度。 惟上返貰施例僅為說明本發明之原理及其功效，而非用 於限制本發明。因此，習於此技術之人士可在不違背本發 =之精神對上述實施例進行修改及變化。本發明之權利範 圍應如後述之申請專利範圍所列。 【圖式簡單說明】 圖1A顯示習用之封裝結構之示意圖； = 顯示習用之具散熱片之晶片封裝方法示意圖； 圖2A顯不本發明封裝結構之示意圖；及 圖^顯示本發明具散熱片之晶片封裝方法 【主要元件符號說明】 2 10 習知封裝結構 本發明封裝結構 基板 I00806.doc 1264125Referring to Fig. 1A, there is shown a schematic diagram of a conventional wafer package structure having a heat sink. The package of the package includes a substrate unit 1, a wafer, a plurality of conductors, a sealing material 13, and a dispersion unit. The substrate unit m has a - surface-surface 102. The wafer has a first surface (1) and a second surface 112' which is opposite the first surface (1). The surface, surface "2 of the wafer η is attached to the first surface 02 of the substrate. Hairi Japanese film! The surface (1) is electrically connected to the first surface 1G2 of the substrate sheet 7L1G1 by the wires η. The encapsulant Η is implanted between the substrate MUM and the heat sink unit (10) to form the package integrated circuit component. The heat sink unit 14 is a flat plate structure having a first surface 142. The first surface 142 of the fin unit 14 has a plurality of concave s 141 for reinforcing the adhesion with the sealing material i 3 . Referring to Figures 1B through 1E, there are shown schematic diagrams of conventional wafer packaging methods. Referring to FIG. 1B, first, a substrate 1 is provided. The substrate 1 has a plurality of wafers 11. Each wafer 11 has a first surface lu and a second surface 112. The second surface 112 is opposite to the first surface. Surface lu. The second surface 112 of the wafer is attached to one of the first surfaces 1 of the substrate 10. The first surface 111 of the wafer is electrically connected to the first surface 100806.doc 1264125 of the substrate 1 by a plurality of wires 12.耑埶片口田口 - , ^ 〆月又热方14 defines a plurality of months of hot films early 140 (as indicated by the dotted line), structure, with - #面14, Μ政热片14系为一平面结There are plurals (2) - surface (4) with mold! : Γ 'This substrate 10 and the dispersion mold. The heat sink 14 is placed in the upper mold 2 by vacuum adsorption, and a glue material 13 is injected into the mold and the film 14 is placed. And /, to encapsulate the substrate 10 and the heat dissipation reference FIG. 1E, to be encapsulated the substrate 1G and the heat sink Zhao: 8 cold: after the combination 'the package (four) from the mold, take out = fine body 18 In order to form a plurality of package structures as shown in FIG. 1A, the chip packaging method and structure of the above-mentioned conventional heat sink are disadvantageous, such as: the sealing material 13 under the sheet is easily peeled off due to poor bonding. The adhesion of the bake piece 10 to the sealant material 13 is insufficient. The yield of the first product is not high.疋弟一, produced by the innovative and progressive heat sink sealing method and structure to solve the above problems. SUMMARY OF THE INVENTION The package structure comprises a substrate unit, a -, a heat sheet unit and a sealant material. The base is formed with a - surface, the cymbal of the cymbal. The surface of the cymbal has a plurality of wires and one of the basic inventions is to provide a wafer with a heat sink. 100806.doc 1264125 Board, electrical connection. The dummy chip is disposed on the wafer. The heat sink: is disposed on the virtual wafer. The encapsulant is used to encapsulate the substrate unit, the dummy wafer and the heat sink. Another object of the present invention is to provide a chip package with a heat sink: (4) providing a substrate, the substrate is bounded by a plurality of substrate units, and the board has a plurality of wafers, and the wafers are disposed on the substrate One of the first surface two' mother-wafer has a -first surface, and the first surface of the wafer is "on the top of the chip" (4) is set - the mesh heat sink is on the virtual:: above the chip Defining a plurality of heat sink units in the sheet, the substrate, the dummy wafers and the heat sink are placed in the mold, and the (I), medium, (4) injection seal / ^ clothing, and (f) cutting The package is formed into a plurality of package structures, each of which is a casket, a "female has a substrate unit, a virtual day sheet, a heat sink unit, and a sealant material. The chip sealing method and structure of the heat sink, so that the sealing material is bonded to the virtual wafer by the mesh of the heat releasing sheet, so as to add the adhesive force of the wafer and the sealing material A, Avoid the sealing material on the upper and lower sides of the heat sink, and “poor and fall off, so as to improve the reliable production of the product. [Embodiment] Referring again to Figure 2AH, the (4) has the intention. The package structure 2 includes a substrate unit 2〇1, a structure, a wire 22, a dummy crystal π solar cell 21, a substrate unit, a second heat release unit 251, and a sealant 24. The 211 and ―2. The wafer 21 has a first surface 2, and the second surface 212 is attached to the substrate unit with respect to the first surface 100806.doc 1264125^xa1<1' 20 1 of the surface 2〇2. The first surface 211 of the wafer 21 is electrically connected to the first surface 2〇2 of the substrate unit 201 by the wires 22. The X dummy cymbal is disposed on the wafer 21. The dummy wafer u is used to support the heat release sheet unit 251 and to isolate the wires 22 and the heat sink sheet 251. The fin unit 251 is a mesh structure and is disposed above the dummy 213. The encapsulant 24 is used to encapsulate the substrate unit 201, the dummy wafer 23 and the heat sink unit 251 to form the package structure 2. 2B to 2F are schematic views of a wafer packaging method with a heat sink according to the present invention. The phase 2B, firstly, provides a base (four), the substrate 2 () defines a plurality of substrate units 20, the substrate 2 has a plurality of wafers 2, and the wafers 21 are placed on the substrate 20 A surface 200. Each wafer 21 has a first surface 211. The first surface 2U of the wafer 21 is electrically connected to the first surface 2 of the substrate 2 by a plurality of wires 22. Referring to Figure 2C, a plurality of dummy wafers 23 are disposed on the corresponding wafers 21. Referring to Figure 2A, a heat sink 25 is provided in which a plurality of heat sink units 251 (shown in phantom) are defined, the heat sinks being placed over the dummy wafers 23. The heat sink 25 is made of a thermally conductive metal material (for example, copper or (f) (four) structure. The grid % of the heat sink 25 allows the sealant (four) 24 to pass through to strengthen the dummy wafer 23 and the sealant material μ. The virtual chips 23 are used to support the heat sink 25 and isolate the wires 22 and the heat sink 25. The substrate 20, the dummy chips 23 and the heat sink 25 are shown in FIG. Placed in the fixture 27. The mandrel material 24 is in the mold. The sealant I00806.doc 1264125 material 24 is passed through the grid 26 of the heat sink 25 (refer to Figure 2d) and the virtual wafers 23 in combination with 'encapsulating the substrate 2, the dummy crystals (3) and the heat sink 25. Referring to FIG. 2F, the package 20 encapsulating the substrate 20, the dummy wafers 23 and the heat sink 25 are from the mold The package body 28 is taken out, and the package body 28 is cut into a plurality of package structures 2 as shown in FIG. 2A. The wafer package method and structure of the heat sink according to the present invention are used to pass the sealant core through the heat sink 25 Grid 26 and the virtual wafers ... to enhance the adhesion of the dummy wafers 23 to the encapsulant 24 Focusing on avoiding: the sealing material 24 on the upper and lower sides of the heat dissipating is combined with the bad combination, so as to increase the viability of the second production. However, the above embodiment is merely illustrative of the principle and function of the present invention, and is not intended to limit the present invention. The above embodiments may be modified and changed without departing from the spirit of the present invention. The scope of the present invention should be as described in the scope of the patent application described below. [Simplified Schematic] FIG. FIG. 2A is a schematic view showing a package structure of a conventional heat sink; FIG. 2A is a schematic view showing a package structure of the present invention; and FIG. 2 is a view showing a wafer package method with a heat sink according to the present invention. 10 conventional package structure of the present invention package structure substrate I00806.doc 1264125
11 晶片 12 導線 13 封膠材料 14 散熱片 16 上模具 17 下模具 18 封裝體 20 基板 21 晶片 22 導線 23 虛擬晶片 24 封膠材料 25 散熱片 26 網格 27 模具 28 封裝體 100 第一表面 101 基板單元 102 第一表面 111 第一表面 112 第二表面 140 散熱片單元 141 凹穴 142 第一表面 100806.doc -10 1264125 200 第一表面 201 基板單元 211 第一表面 212 第二表面 251 散熱片單元 100806.doc - 11 -11 wafer 12 wire 13 sealing material 14 heat sink 16 upper mold 17 lower mold 18 package 20 substrate 21 wafer 22 wire 23 virtual wafer 24 sealing material 25 heat sink 26 grid 27 mold 28 package 100 first surface 101 substrate Unit 102 First surface 111 First surface 112 Second surface 140 Heat sink unit 141 Pocket 142 First surface 100806.doc -10 1264125 200 First surface 201 Substrate unit 211 First surface 212 Second surface 251 Heat sink unit 100806 .doc - 11 -