TW200423337A - Chip package structure - Google Patents

Abstract

A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is flip chip bonding to and electrically connects the carrier or other chips, and there is a flip chip bonding gap between the chip and the carrier or other chips. The heat sink is disposed over the top chip and the area of heat sink is bigger than chip. The encapsulating material layer is filled with the flip chip bonding gap, and covers the carrier and the heat sink. The part of surface of heat sink that far away the chip is exposed. The encapsulating material layer is composed of single encapsulating material. Otherwise, the gap between the chip and the heat sink is between 0.03mm to 0.2mm for example. The thermal conductivity of encapsulating material layer is more than 1.2 W/m.K for example. Selectively, there is a plurality of stand off components disposed on the heat sink.

Description

200423337 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a chip package structure (Chip s t r u c t u r e) ', and particularly to a chip package structure with excellent heat dissipation. [Previous Technology] In today's information-oriented society, the market for portable electric devices is rapidly expanding. Chip packaging technology also needs to be developed in line with the trend of digitalization, networking, regional connectivity, and user-friendly use of electronic devices. In order to meet the above requirements, it is necessary to strengthen the various requirements of high-speed processing, multifunctionalization, integration, miniaturization, and low cost of electronic components. Therefore, the chip packaging technology is also moving toward miniaturization and high cost. Densified development. Among them, the Flip Chip bonding (F / C bonding) technology uses bumps and Carriers for bonding, which greatly shortens the wiring length compared to the conventional wire bonding method. It helps to improve the signal transmission speed between the chip and the carrier board, so it has gradually become the mainstream of high-density packaging. However, an important issue that comes with high-density packaging technology is how to solve the heat dissipation problem of a chip packaging structure with a high degree of accumulation. FIG. 1 is a cross-sectional view of a conventional chip packaging structure using a wire connection type. Referring to FIG. 1, the wafer 20 has an active surface 22, and a plurality of solder pads (not shown) are further disposed on the active surface 22. The wafer 20 is arranged on the carrier plate 30 with the active surface 22 facing upward. A plurality of contacts (not shown) are arranged on the surface of the carrier board 30. Both ends of the plurality of wires 24 are respectively connected to the pads of the chip 20 and the contacts of the carrier board 30, and are electrically connected to the chip. 20 and carrier 30.

706 200423337 Description of the invention (2) Moreover, the surface of the carrier board 3 〇 away from the wafer 20 is further provided with a plurality of arrayed solder balls 32 (Solder bal 1) 32, that is, the chip packaging structure 10 uses a ball grid.

Array packaging (BGA P a c k a g l n g), so that the chip packaging structure can be electrically connected to a printed circuit board (PCB) (not shown) in the future. In addition, a packaging material layer 34 is disposed on the carrier board 30 and covers the wafer 20 disk wires 24 to provide protection. However, this chip package structure has two disadvantages: poor performance. FIG. 2 is a cross-sectional view of a chip package structure using a conventional flip-chip bonding technology. Referring to FIG. 2, the wafer 50 has an active surface 52, and a plurality of solder pads (not shown) are further disposed on the active surface 52. A plurality of contacts (not shown) are arranged on the surface of the carrier board 80. The plurality of bumps 60 are arranged on the pads on the active surface 52, and the bumps 60 are electrically connected to the wafer 50 and the carrier board 80 through the pads of the wafer 50 and the contacts of the carrier board 80. The surface far from the chip 50 is further provided with a plurality of arrayed solder balls 60. In order to protect the chip 50 from being damaged by moisture, at the same time, the protrusion connecting the chip 50 and the carrier plate 80 is protected. Block 60, so that the service is in front;… r cu r, a > Yiyi is particularly damaged by Shear force, so it is more formed-between the seal 50 and the carrier plate 80. 0 formation Encapsulation material? Increase the thin film phenomenon, the lower viscosity liquid encapsulation material ^ 2 is the use of flip-chip bonding between hairs, and then the 2 f sheet 50 and the carrier board described The chip package structure 40 is more modified than the first. The connected chip package structure 10 has a thinner trend of the conventional wire-to-chip package structure with better maps. However, the θ milk can be 'and the thickness also conforms to the same.' Flip-Chip

11844twf.ptd Page 9 200423337 V. Description of the invention (3) The time required for the joint f is longer. The joint production f is based on the size of the natural capillary phenomenon gap in the packaging material. 1 will affect Fengxiang = flow = i ㈣ The incomplete penetration results in voids, which in turn affects the reliability of the package. Λ chip 50 is directly exposed to the outside world. Therefore, when the characteristics of the chip are on the surface of the chip 50, or when the chip is broken by 1, it is to improve This shortcoming has produced another conventional chip seal, and the company has shown that another known method is to use flip chip "" (12 on 72 more 4 plus: the top mold layer to failure. In order to ensure that the film 50 It is not affected by the capacity when marking and moving;% is :: == 心 广 一), with low =

A clever seal? The smart package structure 42 is improved, and the 3B ::: = ίίΠί Patent "3 9 2 6 9 8" is covered with the chip 50 and the S board 80 and filled with the package. The packaging material layer 74 is used to cover the gap. Therefore, it is possible to avoid the occurrence of the "plane" crystal, and the J disadvantage of the carrier plate 80. However, this design is still 11844twf.ptd Page 10 200423337 V. Description of the invention (4) There is no heat dissipation due to the wafer 44 [Summary of the Invention] Therefore, the bonding of the wafer to the wafer is based on a carrier board. Among them, bumps. The chip and the area of the electrical connection are larger than between 50 ′ and 50 ′, and have a good disadvantage. ] In the objective structure of the present invention, at the same time, the purpose is provided, and the at least one crystal wafer has a series of active watches to the carrier board. The area of the loose chip covers the heat sink and the 0 packaging material layer 7 4 which causes the chip package structure to provide ~ a good electrical structure and a type of crystalline thermal sheet, and the active board is placed on the crystal layer system and the package is in use with a polar chip The packaging invention proposes that the sheet and a scattered active surface face toward the heat carrier sheet. Packaging material Carrier board, the best heat sink for chip packaging performance, the package structure of a piece of metal on the surface of the wafer is bonded to the chip, and filled with the crystalline material layer structure, suitable for crystal bonding technology. Structure, the main material layer is provided with a plurality of carrier plates, and the heat sink sheet and the carrier plate are provided by a single piece. In addition, the chip package of this embodiment is composed of 1 ^ i # arQ + ^ 4, nicknames such as It further includes a plurality of stand-off components and a thermal conducting adhesive layer. The thickness holder is, for example, disposed on the heat sink, and the height of the thickness holder is the thickness of the packaging material layer above the thermal pad. The thermally conductive adhesive layer is, for example, disposed between the wafer and the heat sink. Based on the above objectives, the present invention further proposes a chip packaging structure, which is mainly composed of a carrier board, a chip set, a heat sink and a packaging material layer. The chip set is disposed on the carrier board and is electrically connected to the carrier board. The wafer group is mainly composed of multiple wafers, and at least one of them is a wafer cover.

11844twf.ptd

200423337 V. Description of the invention (5) The crystal is bonded on a carrier board or other wafers, and a flip-chip bonding gap is maintained. The heat sink is arranged on the chipset, and the area of the heat sink is larger than the area of the chipset. The packaging material layer is filled in the flip-chip bonding gap and covers the heat sink and the carrier board. The packaging material layer is formed of a single packaging material. In addition, the chip packaging structure of this embodiment further includes, for example, a plurality of thickness retaining members and a thermally conductive adhesive layer. The thickness holder is, for example, disposed on the heat sink, and the height of the thickness holder is equal to the thickness of the packaging material layer above the heat sink. The thermally conductive adhesive layer is, for example, disposed between the uppermost wafer of the chipset and the heat sink. In addition, the wafer set of this embodiment is mainly composed of a first wafer and a second wafer, for example. The first chip has a first active surface, and the first chip is disposed on the carrier board with the first active surface facing away from the carrier board. The second wafer has a second active surface, and a plurality of bumps are disposed on the second active surface. The second chip is flip-chip bonded to the first chip with the second active surface facing the first chip, and is electrically connected to the first chip. The bumps maintain the flip-chip bonding gap. In addition, the chipset further includes a plurality of wires, for example. The two ends of each wire are electrically connected to the first chip and the carrier board, respectively. In addition, the chip set of this embodiment may be mainly composed of a first chip, a second chip, and a third chip. The first wafer has a first active surface, and a plurality of first bumps are disposed on the first active surface. The first chip is flip-chip bonded to the carrier with the first active surface facing the carrier, and is electrically connected to the carrier. The second wafer has a second active surface, and the second wafer is disposed on the first wafer with the second active surface facing away from the first wafer.

11844twf.ptd Page 12 200423337 V. Description of the Invention (6) The second wafer of Shiji has one active surface, three active surfaces, and a second bump. The third chip is bonded to the second chip with the third active surface facing the second chip, and is electrically connected to the second chip: the first bump and the second bump maintain a flip-chip bonding gap. One day after another. In addition, the chipset further includes a plurality of wires, for example. The two ends are electrically connected to the second chip and the carrier, respectively. In the two embodiments of the chip packaging structure described above, the negative of the packaging material # is, for example, a resin. The material of the heat sink is, for example, κ). For example, the material includes multiple arrays:: ball and J f bedding: sheet. The solder ball is, for example, placed on a carrier board without a vulture. Eight mounting base dJJ It is electrically connected to the carrier board. For example, the carrier board is a chip: compared with the chip package structure proposed by Fit Invention, the chip package structure has a larger area of heat sink, so it can provide operational reliability. The political and thermal approach to further improve the chip packaging structure is to make the present invention easier to understand. The following descriptions and other objects, features, and advantages can be more clearly described as follows. Preferred embodiments and the accompanying drawings DETAILED DESCRIPTION [Embodiment] FIG. 4 shows the south of the pepper chip package structure. The first preferred embodiment according to the present invention is mainly a surface view of the handle. Please refer to FIG. 4, the chip Package structure: 100 ants, at least one chip 150, one heat sink 14 and one

7 彳 丨 Page 13 200423337 V. Description of the invention (7) The packaging material layer is composed of 170. Among them, the carrier board 180 is an packaging substrate such as an organic substrate, a ceramic substrate, a flexible substrate, or a flip chip quad flat non-leaded packaging (F / C QFN packaging). ), Etc. Lead frames used in packaging processes. The upper and lower surfaces of the carrier board i8〇 have, for example, a plurality of contacts (not shown). The wafer 150 has an active surface 152 and the wafer 150 is bonded to the upper surface of the carrier plate 180 with the active surface 152 facing the carrier plate 180. For example, a plurality of solder pads (not shown) are arranged on the active surface of the wafer 150, and a plurality of bumps 160 are disposed on the solder pads on the active surface of the wafer 522. The two 150 series are electrically connected to the carrier board 18 through the bump 16 on the solder pad. That is, the chip packaging structure of this embodiment includes at least one crystal 弋 〇 # '/, which means that the chip 150 is bonded to the carrier board using a flip-chip bonding technology / ηηΛ' except for the chip 150. In addition, in this embodiment, I can also be installed. On the carrier board 18 of the structure 100, other chips or other components (components), such as passive components such as resistors and capacitors, are arranged. The heat sink 140 is arranged on the wafer 150, and the loose sheet 14 () is fine, and the heat sink 140 is not limited to a single shape = 捋 η 私 私 男 λ, + dog is limited to body shape, but also can be made by multiple independent Ling ϊ use. This design is beneficial to the large-area chip packaging structure of the wafer 150 and the carrier board 180. Furthermore, the material of the packaging material layer material layer 170 is, for example, the packaging material layer 710 is filled in between and covers the heat sink. 14〇 and the carrier board 18〇. 1 70 is formed from a single packaging material. Encapsulation

11844twf.ptd 200423337 V. Description of the invention (8) The resin is a packaging material on a thermally conductive sheet 140 with a coefficient of, for example, greater than I, early last name, //, sealing material layer 丨 70, preferably Kelvin temperature. In addition, it is preferable that the thickness of the heat sink is 0.1 mm. For example, the thickness of the heat sink is 0.3 mm or less. The wafer 150 is much larger and is a metal. In the present invention, the area is relatively small. The heat sink 14 of titanium material produced by the sheet 150 is mainly used to make the crystal best. Generally, for example, a large diffusion is enabled, and therefore, the one with a good thermal conductivity is plated with gold. In addition, ^ '3 plate , Aluminum plate, iron plate, nickel plate or the pressure on the surface, so the sheet 140 must be able to withstand the strength that is different when forming the packaging process, and it is not easy to bend. The surface of the 140 interface is, for example, subjected to surface chemical treatment or surface roughening. In addition, in order to have a proper bonding between the heat sink i 4 〇 and the wafer J 5 〇, column 1 is further provided with a thermally conductive adhesive layer i 4 5 for heat dissipation. Between the sheet J 4 〇 and the chip i 5 〇 (as shown in the enlarged part of FIG. 4). The thermally conductive adhesive layer 145 is generally made of a material with high thermal conductivity such as stone paste, silver paste, and solder paste. In addition, 'chip package Structure 100, for example, further includes a plurality of arrays The array of solder balls 190 and at least one passive component 195. Among them, the solder balls 190 are, for example, arranged at the contacts on the lower surface of the carrier board 180. The solder balls 190 provide a chip package structure 〇0 For example, for the purpose of electrical connection with a printed circuit board. The passive component 195 is, for example, disposed on the upper surface of the carrier board and is electrically connected to the carrier board.

11844twf.ptd

200423337

5. Description of the invention (9) Connection. It is worth noting that the present invention is different from the conventional structure in FIG. 3A. In the wafer packaging structure 100 of the present invention, each part of the Uchiwa chip packaging layer is formed at one time, so it can be avoided in the sealing of the divided molding. Interface peeling occurred on the packaging material. Interface of x Material FIGS. 5 and 6 are cross-sectional views of a chip package structure according to an embodiment of the present invention. In the chip package structure according to the second preferred embodiment of the present invention, it is mainly the first piece proposed by Gengjin. The rest is the same as that of the first preferred embodiment, and is not the same here. Referring to FIGS. 5 and 6, the chip package structure 2000 will be described. Please make a total of 280, a chipset 250, a heat sink 2440 and a package ^^ a carrier board. Among them, the chip group 2 50 is mainly composed of a plurality of wafers. Θ 270 At least one wafer is bonded to the carrier board 2 by using flip-chip bonding technology. Therefore, there is at least one flip-chip contact ^ eight crystal in the chip group 250. The flip-chip bonding gap 2 5 6 is formed by using a flip-chip bonding wafer = two = 2 = 6. The heat sink 240 is disposed on the chipset 250. The convexity of the package: the shape # is filled in the flip-chip bonding gap 256, and covers the carrier board and the scattered sheet 2 0 on 0 *, and the thermal conductivity of the packaging material layer 2 7 0 is, for example, greater than 12 t / m- Kelvin temperature is preferred. In order to make the heat sink 2 4 0 and the wafer 2 5 0 and appropriately follow, for example, a thermally conductive adhesive layer 245 is further disposed between the heat sink ^ "and the uppermost wafer of the wafer 2 50. The thermally conductive adhesive layer 2 4 5 _ Generally, materials with good thermal conductivity such as stone paste, silver paste, solder paste, etc. are used. Please refer to FIG. 5, the chip set 2 5 of the preferred embodiment is mainly for example

11844twf.ptd Page 16 200423337 V. Description of the Invention (ίο) It consists of a first wafer 250a and a second wafer 250b. Among them, the arrangement relationship of each element is as follows. The first wafer 250a has a first active surface 252a 'and the first wafer 250a is disposed on the carrier plate 280 with the first active surface 252a facing upward. The second wafer 250b has a second active surface 252b, and a plurality of bumps 260 are disposed on the second active surface 252b. The second wafer 2 50 b is flip-chip bonded to the first wafer 250 a with the second active surface 2 5 2 b facing the first wafer 250 a, and is electrically connected to the first wafer 250a. The bump 2 6 0 maintains the flip-chip bonding gap 2 5 6. In addition, the chipset 250 includes, for example, a plurality of wires 2 54b. For example, a plurality of contacts (not shown) are arranged on the surface of the carrier plate 2 80. For example, a plurality of first active surfaces 252a of the first chip 250a and a second active surface 252b of the second chip 250b are disposed. Pad (not shown). The bump 2 60 of the second wafer 2 5 0 b maintains the flip-chip bonding gap 2 5 6 between the first wafer 2 50 a and the second wafer 2 5 0 b. In other words, the second wafer 250b is bonded to the first active surface 252a of the first wafer 250a by a flip-chip bonding technique. The two ends of each of the wires 2 54b are, for example, electrically connected to the contacts of the solder pad of the first chip 250a and the carrier plate 2800 respectively. Referring to FIG. 6, the chip set 250 of the preferred embodiment is composed of a first chip 250a, a second chip 250b, and a third chip 250c, for example. The chipset 2 5 0 further includes, for example, a plurality of wires 2 5 4 b. Among them, the arrangement relationship of each element is as follows. The first wafer 250a is disposed on the carrier board 2800, and the first wafer 250a has a first active surface 252a, and a plurality of first bumps 260a are disposed on the first active surface 252a. The first wafer 250a is bonded to the carrier plate 280 with the first active surface 252a facing the carrier plate 2 80.

11844twf.ptd Page 17 200423337 V. Description of the invention (ll) It is electrically connected to the carrier board 280. The second wafer 250b has a second active surface 252b, and the second active surface 252b faces away from the first wafer 250a. In addition, a plurality of wires 254b are connected between the pads on the second active surface 252b of the second chip 250b and the contacts of the carrier board 280 to electrically connect the second chip 250b and the carrier board 280. The third wafer 250c has a third active surface 252c, and a plurality of second bumps 260b are disposed on the third active surface 252c. The third wafer 250c is flip-chip bonded to the second wafer 250b with the third active surface 252c facing the second wafer 250b, and is electrically connected to the second wafer 250b. The first bump 2 6 0 a and the second bump 2 6 Ob maintain the flip-chip bonding gap 2 5 6. In other words, the third wafer 250c is bonded to the second active surface 252b of the first wafer 250b by flip-chip bonding technology, and the first wafer 250a is bonded to the surface of the carrier plate 2OB by flip-chip bonding technology. In the second preferred embodiment proposed in the present invention, the number of wafers is mainly increased compared with the first preferred embodiment, and at the same time, it is not limited that all wafers are bonded to the carrier board by flip-chip bonding technology. The most important feature of the present invention is that the chip package structure includes at least one chip, and the chip is bonded to a carrier board or other chips by using a bonding technology. Moreover, there is a heat sink above the chip. There is an encapsulation material layer in the heat dissipation plate, the carrier plate, and the flip-chip bonding gap. The encapsulation material layer is formed with the same encapsulation material at any one time, as long as it meets any of the above-mentioned main features, it should fall into the scope of protection. Zanyue Figure 7A is not a cross-sectional view of the package structure after the chip packaging process is completed according to the preferred embodiment of the present invention. = The drawing shows a chip package structure according to a preferred embodiment of the present invention.

200423337 V. Description of Invention (12) Structure ’

Referring to FIG. 7A and FIG. 7B together, A α I = cross-sectional view after cutting. The packaging process of the example is required to form the packaging material. In this preferred embodiment, cutting is performed to form a 'xi er line' such as a line along the cutting line L. Each chip packaging structure is 100 to xi y The package says structure 1 00. Although it is shown in Fig. 7A, Feng Sang 2: Yue = 〇. In addition, 1 70, that is, the time required to cut the material layer in the cutting line. In order to shorten the performance, in addition, in the 封装 ψ chip package structure according to the present invention, for example, there are two more preferred embodiments. It is shown in accordance with the present disclosure, with some seals. ^ The cross-sectional view of the package structure plus the thickness holder please \ = package structure 1 0 2 is mainly more than that shown in Figure 4: Figure 8, s Add multiple thickness holders 142. Among them, the package structure 10 is further increased on the heat sink 140, and the thickness is maintained at 5 pieces of plant protection 142, such as the packaging material layer m above the configuration sheet 140, and the thickness of the cattle: for example, the thickness is equal to the heat dissipation ^^ ^ ^ ^ ^ Thickness Depending on the material type _…, the film can be thinner. Its = 14:?. 05mm ’instead, it is easy to be deformed due to the heat sink fin. The thickness of the heat sink 142 is mainly to stabilize the heat sink 142.

200423337 V. Description of the invention (13) Thick Λν has no special influence on the area size, material or method. Π: Pressure causes damage to the chip packaging structure 102. The reliability of the two-chip packaging structure 102. As for the thickness ^ ί ^ ^ 140 ^ ^ Λ Λ and 4ί ;: The shim is 14 ° for centralized processing and cutting processing. The three-dimensional r 咅 a mB diagram is shown as the shape of the chip package structure shown in FIG. At s: ", the thickness retaining member" 2 is, for example, a spherical diagram, and there is a common place around the structure ig2. Please refer to p. Said Λ 四 Λ. The shape or arrangement of the thickness retaining member 14 2 is not limited by the thickness of the packaging material layer 170 on the surface of the structure 102, and is not limited to the 9A because of the deformation of the heat sink 140 during packaging. Figure and Figure 93. I can change it and show: The design of the piece i ί The holder 142 is not limited to being applied to the 'Hip 00 on the film' shown in Fig. 4, but it can also be applied to, for example, Figs. 5 and 6. The chip package is mounted / installed, and the structure 200 or other crystal wafers conforming to the features of the present invention are reduced in pressure according to the preferred embodiment of the present invention;: ϊίί ;: into a packaging material layer The method is, for example, the chip surname broadcast i, Chengfa. The decompression transfer injection molding method refers to a method in which a package to be introduced is introduced into a rail: Ξ Ξ: a mold, after the mold enters a depressurized state, in the mold ... melt the material, and heat and pressure treatment to harden the resin

11844twf.ptd Page 20 200423337 V. Description of the invention (14) 蕙 4 ^ The transfer of the 'master mold forming method is not decompressed' is likely to cause ^ Γ ^ S gap or insufficient filling of the packaging material between the chip and the heat sink, ^ ^ ^ ~, keep it below 200 ℃-water column can get the best packaging effect 'the best value of decompression state is 10 mm-mercury to seal f Ϊ1 structure 〇Κί ΐί according to the present invention Sectional requirements for forming an encapsulation material layer in a wafer injection molding mold of a preferred embodiment: sealing; 'transfer injection molding equipment (not shown) can place a suitable mold 3 in accordance with the packaging i-type 3, mold 3 〇〇 is mainly composed of Shang Yuancheng decompression transfer to control the molding temperature of the molding temperature is too much 310 and the lower mold 3 2 0. When the upper mold 31 〇 and the lower mold 32 〇 are combined, in order to achieve a more efficient vacuum effect, the mold clamping step is first / first ^ mold = 310, the lower mold 3 2 0 and the vacuum rubber seal ring in the mold m 33 () Minor contact. Then, a vacuum pump (not shown in the figure) is used to perform a vacuum reduction process in the mold cavity 340 through a vacuum pumping line 370. Then, put a tablet (not shown) in the injection pipe 350, and maintain a high degree of vacuum in the space for 5 to 5 seconds, while increasing the temperature in the mold to make the cake into a hot melt state. Packaging material. Finally, the upper mold 3 丨 〇 and the lower 'mold 3 2 0 are completely in close contact' and simultaneously pull up the plunger 360 to introduce a hot-melt packaging material to fill the mold cavity 340. ” Among them, injection molding under reduced pressure is preferably performed at a temperature of at least 5 degrees Celsius below the melting point of the bump 160, and μ π is also reversed. At this time, compared with the packaging material in the molten state during molding, Chip 丨 5 〇 " ^ The pressure generated by the bump, 160 for the wafer 1 50 and the carrier plate 1 8 〇 flip chip bonding strength sheet

200423337 V. Description of the invention (15) Insufficient, easy to move under reduced pressure and other phenomena. During the forming process, the wafer is destructed at 150 ° C. During the wafer lifting process, the wafer packaging of the preferred embodiment has a maximum particle diameter of the packaging material that is smaller than 0.5 of the flip-chip bonding gap. Crystal bonding ". If the gap between the packaging material used or the ^ ^ material between the chip and the heat sink is doubled, the chip-to-chip junction may cause incomplete filling. However, filling is more difficult, and even friction on the surface of the chip can cause the time and degree of filling due to the packaging material. Thermal conductivity added to the packaging material layer ^ ^ ^ f ~ Silicon dioxide that reduces the reliable melting state of the chip, if so, how to dissipate: Know the surface of the fuse used, so the conductivity added is equal to jt Second, it is easy to hurt 1/5 times of the flip-chip bonding gap. The maximum particle diameter of the filler is preferably not oversized. The wafer packaging process of the embodiment is sealed with a liquid packaging material, and the 4 @ 法 系 is in a decompressed state. , Lower temperature process at room temperature. At this time = material is used; material: the two-stage U-thinking printing process is more equipment, but called "Second Printing Machine". The decompression state of the in-line column during the packaging process with the mounting material was incompletely filled with 2 mm-mercury. In addition, after filling the packaging material, add H = 11844twf.ptd. Page 22 200423337 Description of the invention (16) In processing, usually 2 to 5 kg / + ancient eight and eight materials hardening of the case 决 万 A knife pressure, As for heating, it is based on the pressurized shape before sealing. The sealing process is%. At the hardening temperature, heating for more than 3 minutes and 2 degrees Celsius before the hardening temperature can promote the filling of the packaging material. J When the viscosity of the packaging material is increased, the particles used in this process are larger than 1/3 of the particles ^ = ^ accounted for $% of the weight 95. The filling material filled with the gap is easier than the ratio 5 = when the chip is filled. incomplete. Added to = Packaging material = Ϊ ;: In addition to oxygen cutting, if the heat dissipation is improved, heat transfer such as nitriding, nitriding, etc. can be performed. In addition, in order to reduce the stress in the chip packaging structure, and thus avoid the carrier board A warpage phenomenon occurs. The liquid packaging material used = sexually dispersed product. The weight percentage of the elastic dispersion product is preferably 90 or more. 3, and the maximum particle size of the elastic dispersion product is / 3 times the flip-chip bonding gap. The following is good. … (Inventive Application Example) [Example 1] Wafers with an area of 8 mm x 8 mm, 8000 so-called bumps (melting point 183 degrees Celsius, pitch 0.25 mm), and thickness 0.25 H, Bonded in a matrix arrangement on a packaging substrate (FR-5) with an area of 35 mm x 35 mm spread and 0.4 mm. In order to allow the current to flow evenly, aluminum wiring is added to the surface of the wafer. Flip-chip bonding gap is 50 ～ 75

200423337 V. Description of the invention (17) Micron. The heat sink is made of a copper plate of 20¾m x 20mm and a thickness of 0.15mm, and is fixed on the packaging substrate with a commercially available thermally conductive adhesive. The upper and lower surfaces of the copper plate are preferably subjected to a surface roughening treatment in order to improve the bonding strength. Decompression transfer injection molding is performed using a transfer injection molding device with a decompression function. The degree of vacuum in the mold cavity is about 1 m-min. The packaging material is CV8 7 0 0 F2 made by Matsushita Electric Works Co., Ltd. (the maximum particle diameter of the filler is 20 micrometers / meter, and the average particle diameter is 5 micrometers. The filler material is all molten silicon, and the thermal conductivity is 0.9. W / m-Kelvin temperature), the thickness of the packaging material layer is 065 'mm, and the packaging molding area is 29 mm x 29 mm. The encapsulation process is performed at a pressure of 160 ° C, JO kg / cm2 for 2 minutes, and then a post-hardening process of 175 ° C and 4 hours can obtain a device with a structure as shown in Fig. 4 From a cross-sectional view, the thickness of the packaging material layer on the heat sink is 0 · 12 ~ 0 · 15 mm. π Tt's magic order [Example 2] Except changing the package thickness of Example 1 to be the same, it becomes a device as shown in Figure 4. Outside the card, the others are cut from the cross section of the set, and the scattered sheet μ degree is 0 · 〇8 ~ 〇 · 11 mm. …, The thickness of the sealing material layer on the sheet [Example 3] Except for a seven-meter steel plate with a thickness of 0.2 mm aluminum plate, the rest are the same, so that the thickness in Example m is cut from the section of the device See, scattered κ, set at 0 degrees to 0.06 ~ 0. 0 mm. ", The thickness of the on-chip packaging material layer [^ Example 4] on a copper plate with a thickness of 0. 1 mm as shown in Figure 12 The thickness of the retaining piece, and use the sticky rice high, such as the first cut sticky in the four corners to replace the solid

200423337 V. Description of the invention (18) Except for the copper plate with thickness of 0.5 mm in Example 2, everything else is the same, and the device is as shown in Figure 4. From the cross-section of the device, the thickness of the packaging material layer on the heat sink is 0.15 to 0.16 mm. [Example 5] Except replacing the sealing material of Example 1 with 50% of the molten Shi Xiyu and another 50% with alumina (the maximum particle diameter of the filling material is 5 microns, the average particle diameter is 1.5 microns), Everything else is the same, and the structure obtained is the device of FIG. 4. The thermal conductivity of the packaging material used is 1.5 W / m-Kelvin. [Example 6] Except replacing the sealing material of Example 2 with 50% of the molten Shi Xiyan and replacing 50% with boron nitride (the maximum particle diameter of the filling material is 7 microns, and the average particle diameter is 2 microns). In the same way, the resulting structure is shown in the device of FIG. 12. The thermal conductivity of the material used is 1.9 W / m-Kelvin. Example 7 ^ Except that the packaging material of Example 4 was replaced with 50% of the molten $ 2 and replaced with oxide (the maximum particle size of the filling material is 5 microns, average 1 平均 ®, m), the structure is the same. Figure 12 device. Let the thermal conductivity of Γ to Japan ^ > n! Material I be 1.5 Watts / meter-Kelvin temperature. Off the bottom; ^ * Use the wafer, packaging substrate and liquid commercially available in Example 1 (2 materials (Panasonic Electric Co., Ltd. CV5183F)), and use a dispensing equipment to package the crystal 2 2. The packing structure obtained after the filler is not hardened under certain conditions is shown in FIG. 2. ] To ΓΓ, as shown in Fig. 3, the chip package structure 4+ # a _ 1 of Example 2 as shown in Fig. 2 is coated with the mold and packaging material.忡 I Day and Day [Comparative Example 3] As in the device of Example 2, except that no heat sink is used

200423337 V. Description of the invention (19) Same, the resulting chip package structure is shown in Figure 4. The test results of the chip packaging structures of the above examples and comparative examples are shown in FIG. 11. The chip packaging process of the preferred embodiment of the present invention uses the technology disclosed in Japanese Patent J P 3 9 2 6 98 in 2001. However, the present invention optimizes the package size and provides a heat sink so that the chip package structure has the best package reliability and heat dissipation. In summary, according to the chip package structure of the preferred embodiment of the present invention, because it contains a heat sink and the chip is covered with the same material at one time, compared with the conventional chip package structure, it has lower warpage and reliability. High and highly heat dissipation effect. If a high thermal conductivity packaging material is used, the heat dissipation effect is better. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

11844twf.ptd Page 26 200423337 Brief Description of Drawings Face View Figure 1 shows the cross section ί2 of the conventional chip packaging structure using wire connection. The figure shows the wafer package structure of the conventional chip-on-chip bonding technology. Γ is shown as another conventional chip-on-chip bonding technology. ^ ^ Μ 4Λ ^ ^ ^ ^ ^ ^ .i ^ Examples of the present invention The mentioned ... two ... ^ 7 = The drawing shows the finished package structure of the process 彳 t proposed according to the present invention. At 6 ^ B, the wafer diagram of the proposed preferred embodiment is shown. The cross-section of the finished product after the Japanese-Japanese chip packaging process is cut. The packaging of the chip packaging structure of the wafer of the embodiment ^ is shown as a preferred f-thickness 91: d cross-section view according to the present invention. A three-dimensional schematic? The green in the figure is not shown in FIG. 8. The package 31 is shown as a one-sided sheet according to a preferred embodiment of the present invention. It is composed of a middle layer in a reduced pressure injection molding mold. Figure 11 shows an example of a preferred embodiment of the chip package structure according to the present example. Contrast with 11844twf.ptd Page 27 200423337 Brief description of the drawings [Schematic description] 1 0, 4 0, 4 2, 4 4: Chip package structure 2 0, 50: Chip 22, 52: Active surface 2 4: Wire 3 0, 8 0: Carrier board 3 2, 9 0: Solder ball 34, 70, 74: Packaging material layer 6 0 : Bump 7 2: top molding layer 1 0, 1 0 2, 2 0 0: chip package structure 140, 24 0: heat sink 1 4 2: thickness holder 1 4 5, 2 4 5: thermally conductive adhesion Layer 1 5 0: Wafer 1 5 2 · Active surface 1 6 0, 2 6 0: Bump 1 7 0, 2 7 0: Packaging material layer 1 8 0, 2 8 0: Carrier board 1 9 0, 2 9 0: solder ball 1 9 5, 2 9 5: passive element 2 5 0 a · first wafer 2 5 0 b · second wafer 2 5 0 c: third wafer

11844twf.ptd Page 28 200423337 Brief description of the diagram 2 5 2 a: first active surface 2 5 2b: second active surface 2 5 2 c: third active surface 2 5 4b: wire 256 flip-chip bonding gap 2 6 0 a: first bump 2 6 0 b •• second bump 300 mold 310 upper mold 320 lower mold 330 vacuum rubber seal ring 340 mold cavity 350 injection tube 360 plunger 370 vacuum pumping line L: cutting line

11844twf.ptd Page 29

Claims (1)

200423337 VI. Scope of patent application 1. A chip packaging structure including at least: a carrier board; a chip having an active surface, the active surface is provided with a plurality of bumps, and the chip faces the carrier surface with the active surface The flip chip is bonded to the carrier board and electrically connected to the carrier board; a heat sink is disposed on the chip, and the area of the heat sink is larger than the area of the chip, and a packaging material layer is filled in the Between the chip and the carrier board, and covering the heat sink and the carrier board, the packaging material layer is formed of a single packaging material. 2. The chip package structure described in item 1 of the scope of patent application, further includes a plurality of thickness retaining members disposed on the heat sink, and the height of the thickness retaining members is equal to that of the packaging material layer above the heat sink. thickness. 3. The chip package structure described in item 1 of the patent application scope further includes a thermally conductive adhesive layer disposed between the chip and the heat sink. 4. The chip package structure according to item 1 of the scope of patent application, wherein the thermal conductivity of the packaging material layer is greater than 1.2 watts / meter-Kelvin temperature. 5. The chip packaging structure described in item 1 of the scope of patent application, wherein the material of the packaging material layer includes resin. 6. The chip package structure according to item 1 of the scope of patent application, wherein the material of the heat sink comprises metal. 7. The chip package structure described in item 1 of the scope of patent application, further including a plurality of solder balls arranged in an array, arranged on the surface of the carrier board away from the chip. 11844twf.ptd Page 30 200423337 6. Scope of patent application 8 · At least one passive component is included as described in item 1 of the scope of patent application, and the chip package structure is arranged on the carrier board, and it is also packaged and electrically connected to the carrier board. The chip-packaged yttrium-rhenium substrate described in item 1 includes one of a packaging substrate and a lead frame. 1 0 · —a chip packaging structure including at least: a carrier board; A chip set is disposed on the carrier board and is electrically connected to the carrier board. The chip set includes a plurality of wafers, and at least one of the wafers is a flip chip bonded to one of the carrier board and the wafers. And maintain a flip-chip bonding gap; a heat sink disposed on the chipset; the area of the heat sink is larger than the area of the chipset; and a packaging material layer filled in the flip-chip bonding gap and covering The heat sink and the carrier board, and the packaging material layer is formed of a single packaging material. The chip packaging structure described in item 10 of the patent application range, more i.e. a thickness holder, is disposed on the Heat sink, and these thicknesses are 'good'. The degree of reliability is equal to the thickness of the packaging material layer above the heat sink. The thermally conductive adhesive layer as described in item 10 of the patent application scope is arranged in the chip package. < Top surface and the heat sink The chip package structure described in item 10 of the scope of patent application, which 200423337 VI. In the scope of patent application, the thermal conductivity of the packaging material layer is greater than 1.2 Watts / meter-Kelvin temperature. 14. The chip packaging structure according to item 10 of the scope of patent application, wherein the chip set includes at least: a first chip having a first active surface, and the first chip is backed by the first active surface And is disposed on the carrier board toward the carrier board; and a second wafer having a second active surface on which a plurality of bumps are disposed, the second wafer is oriented toward the second active surface The first wafer is flip-chip bonded to the first wafer and is electrically connected to the first wafer, wherein the bumps maintain the flip-chip bonding gap. 15. The chip package structure according to item 14 of the scope of patent application, wherein the chip set further includes a plurality of wires, and both ends of the wires are electrically connected to the second chip and the carrier board, respectively. 16. The chip packaging structure according to item 10 of the scope of patent application, wherein the chip set includes at least: a first chip having a first active surface, and the first active surface is provided with a plurality of first protrusions. Block, the first chip is bonded to the carrier board with the first active surface facing the carrier board, and is electrically connected to the carrier board, a second chip having a second active surface, the first chip The two wafers are disposed on the first wafer with the second active surface facing away from the first wafer; and a third wafer having a third active surface on which a plurality of second protrusions are disposed. Block, the third chip is based on the third active watch 11844twf.ptd Page 32 200423337 6. The scope of the patent application is facing the second wafer and the flip chip is bonded to the second wafer and electrically connected to the second wafer, wherein the first bumps and the first wafers are electrically connected to the second wafer. The two bumps maintain the flip-chip bonding gap. 1 7. The chip package structure according to item 16 of the scope of patent application, wherein the chip set further includes a plurality of wires, and both ends of the wires are electrically connected to the first chip and the carrier board, respectively. 1 8. The chip packaging structure as described in item 10 of the scope of patent application, wherein the material of the packaging material layer includes resin. 19. The chip package structure according to item 10 of the scope of patent application, wherein the material of the heat sink comprises metal. 20. The chip packaging structure described in item 10 of the scope of patent application, further comprising a plurality of arrayed solder balls arranged on the surface of the carrier board away from the chipset. 2 1. The chip package structure as described in item 10 of the scope of patent application, further comprising at least one passive component arranged on the carrier board and electrically connected to the carrier board 2 2. As item 10 of the scope of patent application In the chip packaging structure, the carrier board includes one of a packaging substrate and a lead frame. 11844twf.ptd Page 33