TWI311371B - Double gate semiconductor device having separate gates - Google Patents

Double gate semiconductor device having separate gates Download PDF

Info

Publication number
TWI311371B
TWI311371B TW092130612A TW92130612A TWI311371B TW I311371 B TWI311371 B TW I311371B TW 092130612 A TW092130612 A TW 092130612A TW 92130612 A TW92130612 A TW 92130612A TW I311371 B TWI311371 B TW I311371B
Authority
TW
Taiwan
Prior art keywords
gate
fin
semiconductor device
layer
electrode
Prior art date
Application number
TW092130612A
Other languages
English (en)
Other versions
TW200421595A (en
Inventor
Ahmed Shibly S S
Haihong Wang
Bin Yu
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200421595A publication Critical patent/TW200421595A/zh
Application granted granted Critical
Publication of TWI311371B publication Critical patent/TWI311371B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

1311371 玖、發明說明 .................. 【發明所屬之技術領域】 本發明係關於半導體裝置以及製造該半導體裝置的方 法’尤指一種適用於雙閘極裝置者。 【先前技術】 超大型積體半導體裝置在高密度與高性能的加速需求 上，需如100奈米（nm)以下的閘極長度，高可靠度與製 造產里的增加專結構特性。而結構特性達1 〇〇nln以下時， 則面臨習知技術的極限。 例如’當習知平面金屬氧化物半導體場效電晶體 (MOSFET )之閘極長度小於i 〇〇nm時，與短通道效應有 關的問題，譬如源極與汲極之間的過度漏損，則會變得越 來越難克服。此外，遷移率的降低以及許多製程上的問題， 同樣會難以縮小習知M〇SFETs標有以包括更小的裝置特 性。因此，新的裝置結構乃因運而生，改善FET性能並進 一步縮小裝置。 雙閘極MOSFETs代表已經被視為取代現存平面 MOSFETs的新結構。在許多態樣中，雙閘極m〇sfeTs提 供比習知塊狀矽M0SFETs較佳的特性，其改良處在於雙 閘極MOSFET在通道的兩侧上具有—閘極電極，而不是如 在習知MOSFETs中僅位於一邊側上。當具有兩㈣時， 沒極所產生的電場會較佳地由該通道的源極端過渡。同樣 地，兩閘極能控制之電流約為單一問極的兩倍，而產生更 92454(修正版) 6 1311371
FinFET ( 1式場效電晶體）是目前顯現出良好短通道 行為的·雙間極結構。雖然習知的FinFET稱為、、雙閘極" MOSFETs，但是該兩閘極基本上係實f與電性地連接，從 而形成單-邏輯化的可定㈣極。FinFET包括形成於垂直 鰭部中的通道，FinFET結構可使用類似於製造習知平面 MOSFETs的電路佈局與製程技術來製造。 【發明内容】 本發明之實現在於提供具有雙閘極的FinFET裝置， 該閘極係藉導電鰭部（conductivefin)而有效彼此隔開， 該閘極可獨立地偏置以增加電路設計彈性。 本發明之其餘優點與其它特徵一部分將陳述於下述說 明中，而另-部份對熟諳該技藝者於審查下文時即能瞭 解或者可從實施本發明而知悉。本發明的優點與特徵可 依所附之申請專利範圍指出者而予實現與取得。 根據本發明，以上與其它優點能部份地由包括基板盘 ^成於該基板上之絕緣層的—種半導體裝置達成。縛部可 形成於該絕緣層上’並可包括頂表面與多數個側表 二 1極可形成於該絕緣層上且鄰近該縛部之多數側表面： 一者。第厂閘極可形成在該絕緣層上且與該第一 並且鄰近该鰭部之多數側表面之另外一者。 汗
根據本發明另—誓A & H 貫&心、枚，一種製造半導體裝 法可包括形成絕緣層於A 铲置的方
、土板上，以及形成鰭部結構於哕P 緣層上。該鰭部結構可包括第—側表面、第面= 頂表面。該方法亦可包 表面u及 括將源極與汲極區域形成於該鰭部 92454(修正版) 7 1311371 結構的末端，以及將閘極材料沈積於 極材料圍繞著該頂表面及該第：吉構上。該閘 料可予以㈣’以在該韓部的相對側上該閑極材 極電極。該沈積的問極材料可於鄰近該鰭部處予 很艨本發明 人 ㈣成"其士 …樣’半導體裝置係包括基板 广於該基板上的絕緣層。導電鰭部可形成於該絕緣声 =閑極介電層則可形成料導電鰭部的侧表面上。; =極電極可形成㈣絕緣層上。第—閘極電㈣可位在 :近該閘極介電層之-之導電鰭部的第—側上。第二閑極 電極可形成於該絕緣層i。第二閑極電極可位於導電妹部 的相對側上，鄰近該閘極介電層之另一者，並且與該第一 閘極電極相隔開。 &從下述詳細說明中，本發明的其它優點與特徵將為熟 相該項技藝者所清楚得知。所顯示與用以說明的具體實施 例提供欲實施本發明之最佳模式的說明。本發明能夠以各 種明顯的態樣來修改，而皆未背離本發明。因而，該等圖 式係用以說明本發明之本質而非限定之。 【實施方式】 本發明以下的詳細說明乃參考附圖’在不同圖式中的 相同標號可代表相同或類似的元件。同樣地，以下的詳細 說明並非用以限定本發明。相對地，本發明的範圍係由所 附之申請專利範圍及其等效者所定義出。 本發明之實施態樣係提供雙閘極FinFET裝置與此種 92454(修正版） 1311371 裝置的l造方法。根據本發明所製成之FinFET (鰭式場效 電晶體）f置裡的閘極係有效地彼此.關，且可個別地偏 置。 第1圖說明根據本發明_I體實*例而形成之半導體 裝置100的』面圖。參考第J圖’半導體裝置⑽係包括 石夕在絕緣體上（S0I)之結構，該結構包括—石夕基板110、 -埋設氧化物4120以及在該埋設氧化物層12〇上的一矽 層別。埋設氧化㈣12〇與石夕| 13〇係以一習知方式而 形成於基板11 0上。 在一實施例中，埋設氧化物層 物 ’並且具有從大約咖埃至大約3刪埃範圍的厚度。 石夕層230係包括厚度範圍從3⑽埃至〗埃的單晶或多晶 二，：步詳細於下者’係該石夕層13〇乃用來形成一雙閑 極電晶體裝置用的一鰭部結構。 —本發明之另實施例中，基板110與梦層13G可包括 其它的半導材料，譬如鍺，或者 ^ 干等材枓之組合，嬖如矽 錯。埋設氧化物層12G亦可包括其它的介電材料。= 如石夕氮化物層或者石夕氧化物層（例如，二氧 介電層140係形成於矽層13〇上，以 、 作為保護罩用。在一實施例中 的蝕刻製程中 為約15G埃至約f14G之沈積厚度得 化，以形成一光阻遮罩150用於後續製程 :？圖案 何習知的方式來沈積與圖荦化。 、^光阻係以任 半導體裝置100隨後係予钱刻，再移除該光阻遮軍 92454(修正版) 9 1311371 150。在一實施例中，矽層13〇可以習知的方式來蝕刻，而 該钱刻則終止於埋設氧化物層120上以形成一鰭部。在該 鰭部形成後，源極與汲極區域係形成於鄰近該鰭部的各別 端處。例如，在一具體實施例中，一矽、鍺、或矽與鍺組 合層則可以習知的方式予以沈積、圖案化與蝕刻以形成 源極與汲極區域。 弟2A圖係說明以此方式形成之半導體上，之縛 部結構俯視圖。根據本發明之一具體實施例，源極區域22〇 與汲極區域230係在埋設氧化物層12〇上鄰近鰭部2ι〇的 端處形成。 第2B圖係沿第2A圖之A-A’線所取的剖視圖，以說 明本發明之具體實施例的鰭部結構。介電層14〇與矽層13〇 係予蝕刻以形成鰭部210,該鰭部210係包括矽層13〇與 介電層140。 第3圖係根據本發明之一具體實施例之閘極介電層與 閘極材料形成於鰭部210上的剖視圖。一介電層係形^ 鰭部210上。例如，如第4圖所示，一薄氧化膜3ι〇得熱 生長於鰭部210上。氧化膜310係長至約1〇埃至約5〇埃 的厚度，且形成在鰭部210之矽層130之外露的侧表面上， 以作為一用於後續形成之閘極電極的介電層。類似於該氧 化膜310，介電層14〇得對該鰭部210之頂表面提供電性 絕緣。 在开> 成氧化膜3 1 0後’得沈積一閘極材料層3 2 〇於半 導體裝置1 00上。而該閘極材料層32〇得包含後續形成之 92454(修正版) 10 1311371 閘極電極所用的材料 係包括使用習知化例中，該閘極材料層320 其厚度範圍約3〇〇:二目沈積(CVD)而沈積出的多晶矽， 辟 、至約15〇〇埃。另外，其它的车道从止丨 言如鍺或切與錯的組 、::材料’ 極材料。 个』旳i屬，亦得做為閘 極材系藉由微影術（例如，光學微影）而定義於 極材枓層320中。 〜取玎、 带置HH) ^ 層320得選擇性地钮刻，以
=:。。上的閑極材料層32。形成出一問極結構。如第 者丁存極結構’得使部分閘極材料. $廿A "罨層1 40的頂部上。 第4圖係說明根據本發明具體實施例之閘極材料32〇 千面化的剖視圖。多餘的M極材料得予料（例如，從介 電们40上)’以平面化半導體裝置1〇〇的鰭部區域。例如， 可進灯化學機械式拋光（CMp )，以使該閘極材料（亦即，
閉極材料層320)纟垂直方向上甚至具有或者幾乎甚至具 有介電層140。 參考第4圖’在半導體裝置1〇〇通道區域中的閘極材 料層320係緊靠著鰭部21〇之兩側表自，以形成一第一閘 極41〇與第二閘極42〇。然而，鰭部21〇的頂表面係為： 電層140所覆蓋。此結構亦示於第5圖中，其係說明本發 明之半導體裝置1〇〇的俯視圖。在第5圖中，第一閑極41〇 與第二閘極420係鄰靠但未覆蓋鰭部2丨〇。 該閘極材料層320隨後可予圖案化與蝕刻，以形成雙 閘極電極。如第5圖所示，半導體裝置1〇〇包括具有閘極 92454(修正版) 11 1311371 m51〇肖52〇的雙_結構。如以下所詳述者，閑極電 虽51〇與52〇係有效地由鰭部21。所隔開，並可個別偏置。 為f曰1化起見’圍繞鰭部21〇之側表面之閘極介電 化膜31〇(如第4圖所示）未示於第5圖中。 隨後可將源極/汲極區域22〇與23〇播雜，例如η型或 Ρ型雜質可植入源極/汲極區域22〇與23〇中。特定的植入 劑量與能量可依據特別之終端裝置的需求而選定。一般熟 諳該技藝者將能依電路規格最佳化源極/汲極植入製程，： 該等步驟在此不予揭露，以不致於不當地混淆本發明的重 :。此外’侧壁隔片（未圖示）可在源極/汲極離子植入以 刖選擇14地φ成，以依據特定電路規格而來控制源極/及極 接合的位置。隨後’進行活化退火，以將源極Λ及極區域 220與230活化。 如第5圖所示，閘極電極51〇與閘極電極52〇係實質 以及電性地彼此隔開。根據本發明之—具體實施例，當使 用於電路中時’每—閘極電極510與520係以不同電壓個 別地偏置。獨立偏置第一閘極41〇與第二閘極42〇 (經由 閘極電極5 1 〇與520 )的能力會增加使用半導體裝置j 〇〇 之電路設計的彈性 第5圖中所示之製成的半導體裝置1〇〇係為具有第一 閘極4 1 0與第二閘極42〇的雙閘極裝置。相較於習知的雙 閘極裝置，閘極材料層32〇 (第3圖與第4圖）鄰接鰭部 210的兩表面，並提供半導體裝置1〇〇增大之通道寬度/裝 置之值。該鰭部2 1 0同樣可保留在閘極蝕刻中保護鰭部2 i 〇 12 92454(修正版) 1311371 的介電層140。 第一及第二閘極410與42〇同樣由鰭部21〇有效地隔 開，且係依半導體裝置1〇〇的特定電路規格而個別地偏置 (經由個別的閘極電極51〇與52〇)。相對於包括單閘極連 接的習知FinFETs’此種隔開的雙閘極結構在電路設計的 期間内提供增改的彈性。 因此，根據本發明，雙閘極FinFET裝置在該裝置的 通道區域中形成有兩㈣的_。所製成之結構會呈現出 良好的短通道表現。此外，本發明提供較大的彈性，並能 易於與習知的製程整合。 [其它實施例] 、在二實施例中，係欲將張力應變引入到FinFET (鰭 切效電晶體）的鰭部裡。第6A_6D圖係為說明本發明另 —具體實施例之將張力應變引入到鰭部裡的剖視圖。第6A 圖係示半導體裝置600的剖視圖。參照第6八圖，半導體 裝置600可包括埋設氧化物層（BOX) 610、.鳍部620以及 氧化矽罩63〇。如上述，元件61〇_63〇係依第圖所 逑者而形成。鰭部620係包括矽、鍺、或矽與鍺的組合。 如第6B圖所示，厚的去除式氧化物層得受熱生 :在鰭部620上。厚（例如，2〇〇_4〇〇埃）去除式氧化物 曰640會導入張力應變於鰭部62〇中。如第6c圖所示， 接而，將去除式氧化物層64〇移除，再生成薄閘極氧化物 層650。如第6D圖所示。閘極材料66〇隨後沈積於鰭部 2〇上。FmFET係以典型的方式而由第6D圖中的結構所 92454(修正版) 13 1311371 620將具有一張力應變 性質植入鰭部620中。 形成。在此一 FinFET中的鰭部 而會將熟諳該技藝者所能理解的 在其它的實施例中，係欲—完全石夕化閑極的 此- FinFET可具有-合併的金屬閘㉟，該金屬閘極能移 除多晶石夕消耗效應並且有助於得到用於跑·的適當極 限電壓。第7A圖與第7B圖係用來形成具有完切化閑極 之FinFET之示範性製程的圖式。參照第7A圖，裝置700 包括一鰭部710、源極區域72〇與汲極區域73〇。如上述， 這些層/結構係依第⑽圖所述者而形成。如第7B圖所 不鰭4 71 〇可包括—頂部氧化物罩以及圍繞一石夕結 構的閘極氧化物7 5 0。雜立β 71 η -Γ ·π^ π 710可形成於一埋設氧化（Β〇Χ) 層705上。 第7C圖所示，薄多晶矽層76〇係沈積於鰭部7】〇 上。接而，如第7D圖所示，沈積出一厚，底部抗反射（barc) 層770。如帛7E圖頂部所示，該閘極區域與接觸部780隨 後則可予以圖案化與蝕刻。 ^沒有移除BARq 77G的情形下源極與沒極區域 ;、730可植入離子。因此，所使用的摻雜質會為驗。 θ 所止檔而無法穿透入通道内（例如，鰭部71 〇 )。 =第7Ε圖與第7F圖所示，BARC層770得予以移除， 夕晶石夕760能完全地石夕化以形成金屬閑極彻。該閉 。材料71:亦可以類似上述第4圖所述之方式來平面化。 材料在的說明中’種種特定細節已予說明，譬如特定 、°、化學物、製程等等，以提供對本發明完整的 92454(修正版) 14 1311371 理解。總言之’本發明可在未藉在此所述之特定細節下實 施。在其它情形中’已知的製程結構說明並未細述，以免 不當地混淆本發明的標的。 用以製造本發明之半導體裝置的介電與導電層可藉由 習知的沈積技術而沈積。例如，可應用金屬化技術，譬如 不同型態的CVD製程’包括低壓CVD ( LPCVD )與增強 型 CVD (ECVD)。 本發明可實施於雙閘極半導體裝置的製造上，特別是 具有lOOnm以及以下之結構特徵的FinFET裝置。本發明 可應用於任一不同型態半導體裝置的形成，因而在此不予 夤述，以避免混淆本發明之標的。在實施本發明上，得使 用習知之光學微影術與蝕刻技術，因此，該等技術的細節 在此不另贅述。 本說明書僅將本發明的較佳具體實施例與其部分多用 j實例示出並說明。應理解的是，本發明能用於不同之其 匕組合與環境中’其並能在此所示的發明範内進行修改。 【圖式簡單說明】 以附圖為參考，其中具有相同標號的元件可代表全部 的相同元件。 第1圖係為說明根據本發明具體實施例所形成之鰭部 的剖視圖； 第2A圖係說明本發明之一具體實施例之鰭部結構的 俯視圖； 第2B圖係本發明之一具體實施例之第2A圖所示鰭部 15 92454C修正版） 1311371 結構的剖視圖； 第3圖係本發明一具體實施例之第2b圖所示裝置上 問極介電層舆閘極材料的形成之示意圖； 第4圖係根據本發明—具體實施例之第3圖所示閘極 材料平面化的剖視圖； 具體實施例之第4圖所示之 第5圖係為說明本發明 半導體裝置的俯視圖； 第6A至6D圖係為說明本發明另一實施例之將應變張 力應用導入於一鰭部中的剖視圖；以及 又 第7A至7F圖係為說明本笋 ^ 个知明另一具體實施例而將 全矽化閘極形成於FinFET中的价、 J俯現圖與剖視圖。
[元件符號說明J 100 半導體裝置 120 埋設氧化層 140 介電層 210 鰭部 230 汲極區域 320 閘極材料層 420 第二閘極 520 閘極電極 61〇 埋設氧化（BOX) 620 鰭部 640 犧牲氧化層 660 閘極材料 110 矽基板 13〇 矽層 150 光阻遮罩 220 源極區域 3 1 〇 氧化膜 41〇 第一閘極 51〇 閘極電極 6〇〇 半導體裝置 630 二氧化矽罩 65〇 薄閘極氧化層 7〇0 裝置 92454(修正版) 16 1311371 705 埋 設 氧化 (BOX) 層 710 鰭 部 720 源 極 區 域 730 汲 極 區域 740 頂 部 氧 化罩 750 閘 極 氧化 物 760 薄 多 晶 石夕層 770 BARC 層 80 屬 閘 極 17 92454(修正版)

Claims (1)

1311371 拾、申請專利範圍： 1，一種半導體裝置（100)，包括： 基板（11 0 ); 絕緣層（120)，形成於該基板（110)上； 鰭部（21G)’形成於該絕緣層（12G)上並且包 括頂表面與複數個側表面； 第一閘極（410)，形成於該絕緣層（12〇)上，並 鄰近於該鰭部（210)之複數側表面之一者；以及 第一閘極（420)，形成於該絕緣層（12〇)上，並 與該第一閘極（410)隔開且鄰近該鰭部（21〇)之複數 侧表面之另一個側表面。 2·如申請專利範圍第1項的半導體裝置（100)，其中，該 第一閘極（420 )係形成在該鰭部（21 〇 )之相對側而遠 離該第一閘極（410)。 3.如申請專利範圍第2項的半導體裝置（1〇〇)，其中，該 第與第一閘極（410、42〇)分別包括第一與第二間極 接觸件（510、520)。 4·如申請專利範圍第1項的半導體裝置（100)，復包括： 複數個介電層（3 1 0 )，分別沿該鰭部（2 1 〇 )的複 數個側表面而形成，其中該第一與第二閘極（410、420) 分別緊鄰該複數個介電層（310)之不同者。 5.如申請專利範圍第1項的半導體裝置（1〇〇)，復包括： 介電層（140)，包含形成於該鰭部（210)之該頂 表面上之氮化物與氧化物之至少一者，其中該介電層 18 92454(修正版) 1311371 (14〇)的頂表面、該第一閘極（wo)的頂表面、與該 第二閘極（420 )的頂表面係實質上共平面。 6· —種製造半導體裝置（1〇〇)的方法，包括下列步驟： 形成絕緣層（120)於基板（U0)上； 形成轉部結構（210)於該絕緣層（12〇)上，該鰭 部結構（2 1 0 )包括第一側表面、第二側表面、以及頂 表面； 形成源極與汲極區域（220、23 0 )於該鰭部結構 (210 )的末端； 沈積閘極材料（320)於該鰭部結構（21〇)上，該 閘極材料（320 )圍繞著該頂表面以及該第一與第二側 表面； 將該閘極材料（320 )蝕刻，以將第一閘極電極（41 〇 ) 與第二閘極電極（420 )形成於該鰭部結構（21 〇 )的相 對侧上；以及 將鄰近該鰭部所沈積的閘極材料（32〇 )平面化。 7. 如申凊專利範圍第6項的方法’復包括下列步驟： 將介電層（140)形成於該鰭部結構（210)的該頂 表面上’其中該平面化之步驟包括： 將該閘極材料（320)拋光’俾使該閘極材料（320 ) 不致殘留在該介電層（140)上。 8. 一種半導體裝置（100 )，包括基板（110)、形成於該基 板（11 〇 )上的絕緣層（12〇 )、形成於該絕緣層（1 2〇 ) 上的導電鰭部（2 1 0 )、形成於該導電鰭部（2 1 〇 )之側 19 92454(修正版) 1311371 表面上的間極介電層（310)、以及形成於該絕緣層（120) 上的第—閘極電極（41 0 )’該第一閘極電極（41 0 )係 置在該導電‘鰭部（2 1 0 )之第一側上，且鄰近該閘極 "電層（310)之—者，其特徵在於： : 第二閉極電極（410)係形成於該絕緣層（120)上， 該第二閘極電極（42〇)係配置在該導電鰭部（21〇)的 ’子側上而鄰近該閘極介電層（HQ)之另一者，且與 該第一閘極電極（410)隔開。 9·如申请專利範圍第8項的半導體裝置（ι〇〇)，復包括： 介電蓋狀物（140)，形成於該導電鰭部（21〇)的 頂表面上，其中該第一閘極電極（41〇)與該第二閘極 電極（ 420 )兩者均未延伸超出該介電蓋狀物（14〇)。 1〇·如申請專利範圍第9項的半導體裝置（1〇〇)，其中，該 第閘極電極（410)、該第二問極電極（42〇)與該介 電蓋狀物〇4〇)的頂表面係實質上共平面。 92454(修正版) 20 1311371 柒、指定代表圖： (一） 本案指定代表圖為：第（4 )圖。 (二) 本代表圖之元件代表符號簡單說明: 100 半導體裝置 110 矽基板 120 埋設氧化層 130 矽層 140 介電層 310 氧化膜 410 第一閘極 420 第二閘極
捌、本案若有化學式時，請揭示最能顯示發明特徵的化學式：
92454(修正版)
TW092130612A 2002-11-08 2003-11-03 Double gate semiconductor device having separate gates TWI311371B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/290,158 US6611029B1 (en) 2002-11-08 2002-11-08 Double gate semiconductor device having separate gates

Publications (2)

Publication Number Publication Date
TW200421595A TW200421595A (en) 2004-10-16
TWI311371B true TWI311371B (en) 2009-06-21

Family

ID=27757499

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092130612A TWI311371B (en) 2002-11-08 2003-11-03 Double gate semiconductor device having separate gates

Country Status (9)

Country Link
US (2) US6611029B1 (zh)
JP (1) JP2006505950A (zh)
KR (1) KR101029383B1 (zh)
CN (1) CN100459166C (zh)
AU (1) AU2003291641A1 (zh)
DE (1) DE10393687B4 (zh)
GB (1) GB2408849B (zh)
TW (1) TWI311371B (zh)
WO (1) WO2004044992A1 (zh)

Families Citing this family (109)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6982460B1 (en) * 2000-07-07 2006-01-03 International Business Machines Corporation Self-aligned gate MOSFET with separate gates
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US6800910B2 (en) * 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6815268B1 (en) * 2002-11-22 2004-11-09 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device
US6855990B2 (en) * 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US7091068B1 (en) * 2002-12-06 2006-08-15 Advanced Micro Devices, Inc. Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices
US7001837B2 (en) * 2003-01-17 2006-02-21 Advanced Micro Devices, Inc. Semiconductor with tensile strained substrate and method of making the same
US7148526B1 (en) 2003-01-23 2006-12-12 Advanced Micro Devices, Inc. Germanium MOSFET devices and methods for making same
US6803631B2 (en) * 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US6855606B2 (en) * 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
US7074656B2 (en) * 2003-04-29 2006-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US7029959B1 (en) * 2003-05-06 2006-04-18 Advanced Micro Devices, Inc. Source and drain protection and stringer-free gate formation in semiconductor devices
US6756643B1 (en) * 2003-06-12 2004-06-29 Advanced Micro Devices, Inc. Dual silicon layer for chemical mechanical polishing planarization
US6913959B2 (en) * 2003-06-23 2005-07-05 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device having a MESA structure
US7087506B2 (en) * 2003-06-26 2006-08-08 International Business Machines Corporation Method of forming freestanding semiconductor layer
US7005330B2 (en) * 2003-06-27 2006-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for forming the gate electrode in a multiple-gate transistor
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7078742B2 (en) * 2003-07-25 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel semiconductor structure and method of fabricating the same
US7301206B2 (en) * 2003-08-01 2007-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US7355253B2 (en) * 2003-08-22 2008-04-08 International Business Machines Corporation Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
US8008136B2 (en) * 2003-09-03 2011-08-30 Advanced Micro Devices, Inc. Fully silicided gate structure for FinFET devices
US6970373B2 (en) * 2003-10-02 2005-11-29 Intel Corporation Method and apparatus for improving stability of a 6T CMOS SRAM cell
US7888201B2 (en) * 2003-11-04 2011-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US7105390B2 (en) * 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7624192B2 (en) * 2003-12-30 2009-11-24 Microsoft Corporation Framework for user interaction with multiple network devices
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US8217450B1 (en) 2004-02-03 2012-07-10 GlobalFoundries, Inc. Double-gate semiconductor device with gate contacts formed adjacent sidewalls of a fin
US7060539B2 (en) * 2004-03-01 2006-06-13 International Business Machines Corporation Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
KR100620446B1 (ko) * 2004-03-09 2006-09-12 삼성전자주식회사 핀 전계 효과 트랜지스터 및 이의 제조 방법
US7154118B2 (en) * 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7262084B2 (en) 2004-04-15 2007-08-28 International Business Machines Corporation Methods for manufacturing a finFET using a conventional wafer and apparatus manufactured therefrom
US7098477B2 (en) * 2004-04-23 2006-08-29 International Business Machines Corporation Structure and method of manufacturing a finFET device having stacked fins
US7579280B2 (en) 2004-06-01 2009-08-25 Intel Corporation Method of patterning a film
KR100634372B1 (ko) * 2004-06-04 2006-10-16 삼성전자주식회사 반도체 소자들 및 그 형성 방법들
US7452778B2 (en) * 2004-06-10 2008-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-wire devices and methods of fabrication
US7084461B2 (en) * 2004-06-11 2006-08-01 International Business Machines Corporation Back gate FinFET SRAM
KR100541657B1 (ko) * 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US8669145B2 (en) * 2004-06-30 2014-03-11 International Business Machines Corporation Method and structure for strained FinFET devices
US7042009B2 (en) * 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
KR100618852B1 (ko) * 2004-07-27 2006-09-01 삼성전자주식회사 높은 동작 전류를 갖는 반도체 소자
US6951784B1 (en) 2004-08-05 2005-10-04 International Business Machines Corporation Three-mask method of constructing the final hard mask used for etching the silicon fins for FinFETs
US7348284B2 (en) * 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7348641B2 (en) * 2004-08-31 2008-03-25 International Business Machines Corporation Structure and method of making double-gated self-aligned finFET having gates of different lengths
US7071064B2 (en) * 2004-09-23 2006-07-04 Intel Corporation U-gate transistors and methods of fabrication
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7361958B2 (en) 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7241649B2 (en) * 2004-10-29 2007-07-10 International Business Machines Corporation FinFET body contact structure
WO2006069340A2 (en) * 2004-12-21 2006-06-29 Carnegie Mellon University Lithography and associated methods, devices, and systems
US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
US7518196B2 (en) * 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7288805B2 (en) * 2005-02-24 2007-10-30 International Business Machines Corporation Double gate isolation
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
DE602005014394D1 (de) * 2005-06-16 2009-06-18 Vkr Holding As Sonnenkollektor
US7411252B2 (en) * 2005-06-21 2008-08-12 International Business Machines Corporation Substrate backgate for trigate FET
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
CN100442295C (zh) * 2005-08-05 2008-12-10 中芯国际集成电路制造(上海)有限公司 确定半导体ic可靠性可比性的方法
US7402875B2 (en) * 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7400031B2 (en) * 2005-09-19 2008-07-15 International Business Machines Corporation Asymmetrically stressed CMOS FinFET
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US7566609B2 (en) * 2005-11-29 2009-07-28 International Business Machines Corporation Method of manufacturing a semiconductor structure
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7402856B2 (en) * 2005-12-09 2008-07-22 Intel Corporation Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same
US7439588B2 (en) * 2005-12-13 2008-10-21 Intel Corporation Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate
US7512017B2 (en) * 2005-12-21 2009-03-31 Intel Corporation Integration of planar and tri-gate devices on the same substrate
US7396711B2 (en) 2005-12-27 2008-07-08 Intel Corporation Method of fabricating a multi-cornered film
US7525160B2 (en) 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
JP2007180362A (ja) * 2005-12-28 2007-07-12 Toshiba Corp 半導体装置
US20070148926A1 (en) * 2005-12-28 2007-06-28 Intel Corporation Dual halo implant for improving short channel effect in three-dimensional tri-gate transistors
US7545008B2 (en) * 2006-02-03 2009-06-09 The Hong Kong University Of Science And Technology Complementary metal-oxide-semiconductor transistor structure for high density and high performance integrated circuits
US7791140B2 (en) * 2006-02-13 2010-09-07 Nxp B.V. Double-gate semiconductor devices having gates with different work functions and methods of manufacture thereof
US20070232002A1 (en) * 2006-03-29 2007-10-04 Chang Peter L D Static random access memory using independent double gate transistors
US20070235763A1 (en) * 2006-03-29 2007-10-11 Doyle Brian S Substrate band gap engineered multi-gate pMOS devices
US7425500B2 (en) 2006-03-31 2008-09-16 Intel Corporation Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors
US7449373B2 (en) * 2006-03-31 2008-11-11 Intel Corporation Method of ion implanting for tri-gate devices
US7407847B2 (en) * 2006-03-31 2008-08-05 Intel Corporation Stacked multi-gate transistor design and method of fabrication
US20090321830A1 (en) 2006-05-15 2009-12-31 Carnegie Mellon University Integrated circuit device, system, and method of fabrication
US7670928B2 (en) * 2006-06-14 2010-03-02 Intel Corporation Ultra-thin oxide bonding for S1 to S1 dual orientation bonding
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US7435683B2 (en) * 2006-09-15 2008-10-14 Intel Corporation Apparatus and method for selectively recessing spacers on multi-gate devices
US20080097346A1 (en) * 2006-09-19 2008-04-24 Alcon, Inc. Trocar cannula
US7700470B2 (en) 2006-09-22 2010-04-20 Intel Corporation Selective anisotropic wet etching of workfunction metal for semiconductor devices
US7538391B2 (en) * 2007-01-09 2009-05-26 International Business Machines Corporation Curved FINFETs
US20080173942A1 (en) * 2007-01-22 2008-07-24 International Business Machines Corporation STRUCTURE AND METHOD OF MANUFACTURING A STRAINED FinFET WITH STRESSED SILICIDE
CN101939830A (zh) * 2008-02-11 2011-01-05 Nxp股份有限公司 具有分立栅极的FinFET及其制造方法
JP5285947B2 (ja) * 2008-04-11 2013-09-11 株式会社東芝 半導体装置、およびその製造方法
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US20100155801A1 (en) * 2008-12-22 2010-06-24 Doyle Brian S Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application
US7999298B2 (en) * 2008-12-30 2011-08-16 Intel Corporation Embedded memory cell and method of manufacturing same
US8105901B2 (en) * 2009-07-27 2012-01-31 International Business Machines Corporation Method for double pattern density
CN102479821B (zh) * 2010-11-30 2014-07-16 中国科学院微电子研究所 半导体器件及其形成方法
CN103022124B (zh) * 2011-09-22 2015-08-19 中芯国际集成电路制造(北京)有限公司 双栅晶体管及其制造方法
US9059001B2 (en) * 2011-12-16 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with biased feature
US8785273B2 (en) 2012-04-11 2014-07-22 International Business Machines Corporation FinFET non-volatile memory and method of fabrication
US9024387B2 (en) 2012-06-25 2015-05-05 International Business Machines Corporation FinFET with body contact
US9018713B2 (en) 2012-06-25 2015-04-28 International Business Machines Corporation Plural differential pair employing FinFET structure
CN103811543B (zh) * 2012-11-05 2018-09-18 中国科学院微电子研究所 半导体器件及其制造方法
CN105448688A (zh) * 2014-07-09 2016-03-30 中芯国际集成电路制造(上海)有限公司 栅极的形成方法及半导体器件
US9525072B2 (en) * 2014-08-11 2016-12-20 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and method of formation
US9577101B2 (en) 2015-03-13 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain regions for fin field effect transistors and methods of forming same
CN105632936B (zh) * 2016-03-22 2018-10-16 上海华力微电子有限公司 一种双栅极鳍式场效应晶体管的制备方法
CN106952959B (zh) * 2017-03-16 2020-04-03 北京大学 一种锗硅沟道鳍式场效应晶体管及其制备方法
CN106898553A (zh) * 2017-03-16 2017-06-27 北京大学 一种鳍式场效应晶体管及其制备方法

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1601059A (en) * 1978-05-31 1981-10-21 Secr Defence Fet devices and their fabrication
US5315143A (en) * 1992-04-28 1994-05-24 Matsushita Electric Industrial Co., Ltd. High density integrated semiconductor device
US5910912A (en) * 1992-10-30 1999-06-08 International Business Machines Corporation Flash EEPROM with dual-sidewall gate
JP3252578B2 (ja) * 1993-12-27 2002-02-04 ソニー株式会社 平面型絶縁ゲート電界効果トランジスタの製法
US5757038A (en) * 1995-11-06 1998-05-26 International Business Machines Corporation Self-aligned dual gate MOSFET with an ultranarrow channel
DE19846063A1 (de) * 1998-10-07 2000-04-20 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung eines Double-Gate MOSFETs
US6333247B1 (en) * 1999-02-10 2001-12-25 International Business Machines Corporation Two-step MOSFET gate formation for high-density devices
US6159782A (en) * 1999-08-05 2000-12-12 Advanced Micro Devices, Inc. Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant
US6483171B1 (en) * 1999-08-13 2002-11-19 Micron Technology, Inc. Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same
US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
KR100353551B1 (ko) * 2000-01-28 2002-09-27 주식회사 하이닉스반도체 실리사이드 형성방법
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6396108B1 (en) * 2000-11-13 2002-05-28 Advanced Micro Devices, Inc. Self-aligned double gate silicon-on-insulator (SOI) device
US6472258B1 (en) * 2000-11-13 2002-10-29 International Business Machines Corporation Double gate trench transistor
US6300182B1 (en) * 2000-12-11 2001-10-09 Advanced Micro Devices, Inc. Field effect transistor having dual gates with asymmetrical doping for reduced threshold voltage
JP3543117B2 (ja) * 2001-03-13 2004-07-14 独立行政法人産業技術総合研究所 二重ゲート電界効果トランジスタ
FR2822293B1 (fr) * 2001-03-13 2007-03-23 Nat Inst Of Advanced Ind Scien Transistor a effet de champ et double grille, circuit integre comportant ce transistor, et procede de fabrication de ce dernier
US6458662B1 (en) * 2001-04-04 2002-10-01 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
US6689650B2 (en) * 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6657259B2 (en) * 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6610576B2 (en) * 2001-12-13 2003-08-26 International Business Machines Corporation Method for forming asymmetric dual gate transistor
US20030151077A1 (en) * 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US6657252B2 (en) * 2002-03-19 2003-12-02 International Business Machines Corporation FinFET CMOS with NVRAM capability
US6770516B2 (en) * 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
US6833588B2 (en) * 2002-10-22 2004-12-21 Advanced Micro Devices, Inc. Semiconductor device having a U-shaped gate structure
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US7214991B2 (en) * 2002-12-06 2007-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS inverters configured using multiple-gate transistors
US6812119B1 (en) * 2003-07-08 2004-11-02 Advanced Micro Devices, Inc. Narrow fins by oxidation in double-gate finfet

Also Published As

Publication number Publication date
KR101029383B1 (ko) 2011-04-15
WO2004044992A1 (en) 2004-05-27
KR20050062656A (ko) 2005-06-23
CN1711644A (zh) 2005-12-21
JP2006505950A (ja) 2006-02-16
GB2408849A (en) 2005-06-08
US6611029B1 (en) 2003-08-26
GB2408849B (en) 2006-06-28
AU2003291641A1 (en) 2004-06-03
DE10393687T5 (de) 2005-10-06
GB0504833D0 (en) 2005-04-13
CN100459166C (zh) 2009-02-04
TW200421595A (en) 2004-10-16
US20040126975A1 (en) 2004-07-01
DE10393687B4 (de) 2012-12-06

Similar Documents

Publication Publication Date Title
TWI311371B (en) Double gate semiconductor device having separate gates
KR100993937B1 (ko) Ｕ-형태의 게이트 구조를 가지는 반도체 디바이스
TWI287867B (en) Independently accessed double-gate and tri-gate transistors in same process flow
TWI339406B (en) Locally thinned fins
JP4642786B2 (ja) 複数のスラブを備えるマルチゲートトランジスタの製造方法
JP4006267B2 (ja) ２重ゲート／２重チャネルｍｏｓｆｅｔの製造方法
US7102181B1 (en) Structure and method for dual-gate FET with SOI substrate
JP3962321B2 (ja) 非対称フィン電界効果トランジスタ及びその製造方法
TWI313512B (en) A pull-back method of forming fins in finfets
TWI255543B (en) A CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture
TWI248650B (en) Silicon-on-nothing fabrication process
TWI402984B (zh) 藉由自我對齊氧化之自我對齊平面雙閘極程序
US7141476B2 (en) Method of forming a transistor with a bottom gate
US20060231907A1 (en) Semiconductor device with FinFET and method of fabricating the same
KR100653536B1 (ko) 반도체 소자의 핀 전계효과 트랜지스터 제조방법
US7494895B2 (en) Method of fabricating a three-dimensional MOSFET employing a hard mask spacer
KR20040044343A (ko) 다중 임계 금속 게이트 ｃｍｏｓ 소자 제조 방법 및 공정
KR20050062655A (ko) 반도체 디바이스에서 게이트 임계 치수를 향상시키기 위한게이트 물질 평탄화
JP2006148141A (ja) 自己整合ダブルゲートデバイス及びその形成方法
TW200818507A (en) Semiconductor device and method of manufacturing semiconductor device
US7335945B2 (en) Multi-gate MOS transistor and method of manufacturing the same
JP2006013303A (ja) 半導体装置及びその製造方法
US6876042B1 (en) Additional gate control for a double-gate MOSFET
TW201142929A (en) Dual gate oxide trench MOSFET with channel stop trench and three or four masks process
US20110068404A1 (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent