TWI306312B - Floating gate memory cells with increased coupling ratio - Google Patents

Floating gate memory cells with increased coupling ratio Download PDF

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Publication number
TWI306312B
TWI306312B TW092112230A TW92112230A TWI306312B TW I306312 B TWI306312 B TW I306312B TW 092112230 A TW092112230 A TW 092112230A TW 92112230 A TW92112230 A TW 92112230A TW I306312 B TWI306312 B TW I306312B
Authority
TW
Taiwan
Prior art keywords
layer
conductive
spacer
spacers
stack
Prior art date
Application number
TW092112230A
Other languages
English (en)
Chinese (zh)
Other versions
TW200405578A (en
Inventor
Jos Van Duuren Michiel
Theodorus Fransiscus Van Schaijk Robertus
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Publication of TW200405578A publication Critical patent/TW200405578A/zh
Application granted granted Critical
Publication of TWI306312B publication Critical patent/TWI306312B/zh

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/68Floating-gate IGFETs
    • H10D30/681Floating-gate IGFETs having only two programming levels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/68Floating-gate IGFETs
    • H10D30/6891Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
TW092112230A 2002-05-08 2003-05-05 Floating gate memory cells with increased coupling ratio TWI306312B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02076771 2002-05-08

Publications (2)

Publication Number Publication Date
TW200405578A TW200405578A (en) 2004-04-01
TWI306312B true TWI306312B (en) 2009-02-11

Family

ID=29414749

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092112230A TWI306312B (en) 2002-05-08 2003-05-05 Floating gate memory cells with increased coupling ratio

Country Status (9)

Country Link
US (1) US7045852B2 (enExample)
EP (1) EP1506580B1 (enExample)
JP (1) JP2005524994A (enExample)
CN (1) CN100533772C (enExample)
AT (1) ATE475200T1 (enExample)
AU (1) AU2003216649A1 (enExample)
DE (1) DE60333452D1 (enExample)
TW (1) TWI306312B (enExample)
WO (1) WO2003096431A1 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7221008B2 (en) * 2003-10-06 2007-05-22 Sandisk Corporation Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory
KR100650369B1 (ko) * 2004-10-01 2006-11-27 주식회사 하이닉스반도체 폴리실리콘부유측벽을 갖는 비휘발성메모리장치 및 그제조 방법
US7381615B2 (en) * 2004-11-23 2008-06-03 Sandisk Corporation Methods for self-aligned trench filling with grown dielectric for high coupling ratio in semiconductor devices
US7402886B2 (en) * 2004-11-23 2008-07-22 Sandisk Corporation Memory with self-aligned trenches for narrow gap isolation regions
US7319618B2 (en) * 2005-08-16 2008-01-15 Macronic International Co., Ltd. Low-k spacer structure for flash memory
US7541241B2 (en) * 2005-12-12 2009-06-02 Promos Technologies, Inc. Method for fabricating memory cell
JP4364225B2 (ja) * 2006-09-15 2009-11-11 株式会社東芝 半導体装置およびその製造方法
US8325530B2 (en) * 2006-10-03 2012-12-04 Macronix International Co., Ltd. Cell operation methods using gate-injection for floating gate NAND flash memory
US20080160680A1 (en) * 2006-12-28 2008-07-03 Yuan Jack H Methods of fabricating shield plates for reduced field coupling in nonvolatile memory
US20080157169A1 (en) * 2006-12-28 2008-07-03 Yuan Jack H Shield plates for reduced field coupling in nonvolatile memory
TW200847404A (en) * 2007-05-18 2008-12-01 Nanya Technology Corp Flash memory device and method for fabricating thereof
JP2009278098A (ja) * 2008-05-13 2009-11-26 Hynix Semiconductor Inc フラッシュメモリ素子及びその製造方法
CN101866691B (zh) * 2010-04-29 2015-06-17 上海华虹宏力半导体制造有限公司 获得快闪存储单元电容耦合率的方法
CN102867748B (zh) * 2011-07-06 2015-09-23 中国科学院微电子研究所 一种晶体管及其制作方法和包括该晶体管的半导体芯片
US8664059B2 (en) 2012-04-26 2014-03-04 International Business Machines Corporation Non-volatile memory device formed by dual floating gate deposit
US20130285134A1 (en) 2012-04-26 2013-10-31 International Business Machines Corporation Non-volatile memory device formed with etch stop layer in shallow trench isolation region
US20140015031A1 (en) * 2012-07-12 2014-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and Method for Memory Device
CN103715076B (zh) * 2013-12-27 2016-04-13 上海华虹宏力半导体制造有限公司 提高分栅式闪存中控制栅极对浮栅的耦合系数的方法
US10003014B2 (en) * 2014-06-20 2018-06-19 International Business Machines Corporation Method of forming an on-pitch self-aligned hard mask for contact to a tunnel junction using ion beam etching
CN106992143B (zh) * 2016-01-21 2019-12-17 中芯国际集成电路制造(上海)有限公司 一种半导体器件以及制备方法、电子装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5284784A (en) * 1991-10-02 1994-02-08 National Semiconductor Corporation Buried bit-line source-side injection flash memory cell
US5445984A (en) * 1994-11-28 1995-08-29 United Microelectronics Corporation Method of making a split gate flash memory cell
US5576232A (en) * 1994-12-12 1996-11-19 United Microelectronics Corp. Fabrication process for flash memory in which channel lengths are controlled
US5650345A (en) 1995-06-07 1997-07-22 International Business Machines Corporation Method of making self-aligned stacked gate EEPROM with improved coupling ratio
KR100278647B1 (ko) * 1996-10-05 2001-02-01 윤종용 불휘발성 메모리소자 및 그 제조방법
US6069382A (en) * 1998-02-11 2000-05-30 Cypress Semiconductor Corp. Non-volatile memory cell having a high coupling ratio

Also Published As

Publication number Publication date
JP2005524994A (ja) 2005-08-18
DE60333452D1 (de) 2010-09-02
CN1653621A (zh) 2005-08-10
EP1506580A1 (en) 2005-02-16
US20050218445A1 (en) 2005-10-06
CN100533772C (zh) 2009-08-26
EP1506580B1 (en) 2010-07-21
WO2003096431A1 (en) 2003-11-20
TW200405578A (en) 2004-04-01
ATE475200T1 (de) 2010-08-15
AU2003216649A1 (en) 2003-11-11
US7045852B2 (en) 2006-05-16

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