TWI299559B - Ic substrate with over voltage protection function and method for manufacturing the same - Google Patents

Ic substrate with over voltage protection function and method for manufacturing the same Download PDF

Info

Publication number
TWI299559B
TWI299559B TW091113365A TW91113365A TWI299559B TW I299559 B TWI299559 B TW I299559B TW 091113365 A TW091113365 A TW 091113365A TW 91113365 A TW91113365 A TW 91113365A TW I299559 B TWI299559 B TW I299559B
Authority
TW
Taiwan
Prior art keywords
substrate
layers
variable resistance
resistance material
layer
Prior art date
Application number
TW091113365A
Other languages
English (en)
Inventor
Yuan Lee Chun
Original Assignee
Inpaq Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inpaq Technology Co Ltd filed Critical Inpaq Technology Co Ltd
Priority to TW091113365A priority Critical patent/TWI299559B/zh
Priority to KR1020030039162A priority patent/KR20040002612A/ko
Priority to US10/463,984 priority patent/US7053468B2/en
Priority to JP2003174086A priority patent/JP2004023108A/ja
Priority to US11/363,564 priority patent/US20060138608A1/en
Priority to US11/363,880 priority patent/US20060138611A1/en
Priority to US11/363,773 priority patent/US20060138610A1/en
Priority to US11/363,771 priority patent/US7528467B2/en
Priority to US11/364,404 priority patent/US7253505B2/en
Application granted granted Critical
Publication of TWI299559B publication Critical patent/TWI299559B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/1013—Thin film varistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/12—Overvoltage protection resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Thermistors And Varistors (AREA)

Description

1299559 A7 ______ B7 五、發明説明（1 ) 發明領域 本發明係有關一種具備過電壓保護功能之積體電路承載 基板’特別是在一基板上同時提供多個過電壓保護裝置的 結構。 發明背景 習知技藝的過電壓保護元件，是在印刷電路板中，針對 積體電路元件之需要，個別設置過電壓保護元件於J / 〇埠 附近，以提供對於I c内部電路之保護，惟此一設計必須對 於每一需要保護之積體電路元件設置適當過電壓保護元 件，因此必須從電路的需求設計保護電路，以避免因為出 現突波，使得積體電路元件受到破壞。 請參照圖1 a，該圖為習知技藝I C基板的俯視圖，其中在 基板（1 2 )上配置有多數電極端（n )以及一接地端 (1 3 )，再以焊錫焊接的方式將積體電路元件（丨〇)焊接在 孩多數電極端與接地端上。圖i b則是習知技藝j c基板的剖 面圖’從該圖中我們可以清楚的瞭解各導線之間的關係。 由於此種結構並無法提供過電壓之保護功能，使得該積體 電路元件可能無法有效地承受突波能量，造成積體電路元 件不可回復之損害。 為了保護積體電路元件，許多過電壓保護元件裝置不斯 地被提出。但是該過電壓保護裝置都必須在積體電路元件 製造完成並配置到印刷電路板後，依據實際之需要，而分 別在印刷電路板上之][/ 〇埠附近設置，以對積體電路元件 提供過電壓保護。因此，此種設計具有設計成本高、佔據 _ , - 4 - 本紙張尺度適用㈣时標準(⑽）M規格(2igx撕涵 1 *-- 1299559 A7
印刷電路板空間’以及不能提供積體電路元件全面保護之 缺點。 因此，有需要研究出一種具有過電壓保護功能的積體電 路承載基板，可以同時提供多個或全面性過電壓保護裝 置，以解決習知技藝無法提供過電壓保護或者必須在印刷 電路板上裝設過電壓保護裝置之不便。本發明提供一種具 有過電壓保護功能的積體電路承載基板，以滿足此一需 求。 發明簡沭 本發明的一個目的，在於提供一種具有過電壓保護功能 之積體電路承載基板及其製造方法，使得積體電路元件在 出現過電壓突波之情形下可以受到保護。 本發明的又一目的，在於提供一種具有過電壓保護功能 之積體電路承載基板及其製造方法，其中地線係設置在底 部，可以節省空間並降低成本。 本發明的再一目的，在於使一基板可以同時提供多個過 電壓保護裝置，如此可以節省設計成本、節省有限空間， 以及降低I C電路設置保護裝置所需之單位成本。 本發明的又再一目的，在於提供一種具有過電壓保護功 能之積體電路承載基板及其製造方法，此基板可以設計成 各種1C封裝方式，如插腳式（DIP)及表面接著式（SMD) 等。 本發明的另一目的，在於提供一種具有過電壓保護功能 之積體電路承載基板及其製造方法，其係於1C封裝完成 __ _-5-______ 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 1299559
後，再加入保護電路。 為達成本發明之上述目的’本發明提出-種具有過電壓 保護功能之積體電路承載基板’包含：—基板；一接地導 體層’用以形成接地端，該接地端係配置於該基板下表 面，貫穿延伸至該基板之上表面，其中於該基板之上表面 露出一或多數個端點；一或多數個可變電阻材料層，該可 變電阻材料層係配置在該接地導體層所露出之各端點上， 並與各接地導體層彼此相連接；以及多數導體層，用以形 成電極端，各該導體層係配置在該基板上，並延伸覆蓋各 該可變電阻材料層，與各該可變電阻材料層彼此相連接。 在實際的應用上基板可以是陶瓷基板或印刷電路板 (PCB) ° 為使本發明之技術内容及特點更易於瞭解，茲藉由較佳 實施例，配合圖式說明如下。 圖示簡述 本發明將依照後附圖示來說明，其中： 圖la係一習知積體電路元件配置於基板上之俯視圖； 圖lb係一習知積體電路元件配置於基板上之剖面圖； 圖2a、2b及2c係根據本發明一實施例之具備過電壓保護功 能之積體電路承載基板形成過程之剖面圖，圖2(1及圖“為 根據前述實施例之具備過電壓保護功能之積體電路承載基 板形成過程之俯視圖； 圖3圖4及圖5係根據本發明不同實施例之具備過電壓保 護功能之積體電路承載基板之剖面圖； - . _ 6 - 本紙張尺度適财@國家標準(CNS) ^規格(加χ 297公贊）
1299559 五、發明説明（4 ) 圖6 a、6b及6c係根據本發明一會％ “ 只他例足夕層型具備過電壓 保護功能之積體電路承載基板形成過程之剖面圖· 圖^取城根據本發明—實施例之具備過電 壓保護功能之球格陣列式積體電路包裝形成過程之剖面 TSt · 圖， 圖7 f係根據本發明一實施例之且供 貝1 J疋·具備過電壓保護功能之球 格陣列式積體電路包裝之俯視圖； 圖8 a及8b係根據本發明一實施你丨 > 之 X犯例又多層型具備過電壓保 護功能之積體電路承載基板形成過程之剖面圖； 圖9a及圖9b係根據本發明之一實絲々丨— 貫她例之具備過電壓保護功 能之積體電路承載基板之剖面圖；以及 圖10a、10b、10c、l〇d、l〇e及10f根據本發明一實施例之具 備過電壓㈣功能之積體電路承載基板形成過程之剖面 圖。 主要元件符號說明 10 積體電路晶片（I c Chip) 11 電極端 12 基板 13 接地端 2 0,3 0,40,5 0,60,70,8 0,9 0，100 積體電路晶片（IC Chip) 2 1，3 1，4 1，5 1，7 1，9 1，1 0 1 導體層 22,3 2,42,5 2,7 2,92, 1 02 基板 23,33,43,53,63,83,93,103 接地導體層 24,3 4,44,54,64,74,84,94，104 可變電阻材料層 -7- 本紙張尺度適财國@家標準(CNS) A4規格(21GX 297公爱)"—"—"〜----— 1299559 A7
2 5,3 5,4 5,5 5,6 5,7 5 76 611,811 6 12,812 6 13 621,821 622,822 623 73 1,7 3 2,7 3 3 8 5，9 5 保護層 第二保護層 第一導體層 第二導體層 第三導體層 第一基板 第二基板 第三基板 導體層
發明詳述 以下將參考圖示說明本於明^香 令赞明的實施例。圖示中相同的 件具有相同的參考符號。 訂
線 圖2a、2b及2c係根據本發明一實施例之具備過電壓保確功 能之積體電路承載基板形成過程之剖面圖。如圖2&所=, 於-基板（22 )上形成-第_導體層以作為接地導體層 (2 3 )，其中該第一導體層係形成於該基板之下表面並貫 穿延伸至該基板之上表面，其中於該基板之上表面形成一 或多數個端點。如圖2b所示，再於該基板形成一或多數個 可變電阻材料層（2 4 )，其中各該可變電阻材料層係配置 在該接地導體層所露出之各端點上，並與各接地導體層彼 此相連接。另外於基板上表面形成多數第二導體層 (2 1 )，以作為上電極。該第二導體層係延伸覆蓋各該可 變電阻材料層，與各該可變電阻材料層彼此相連接。圖2c 本纸張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1299559 、發明説明（6 所不為將積體電路晶片（2 該晶片以銲錫球鱼上電極柏壶置在孩基板上之剖面圖， 防止灰塵及水氣進入。為便於接夺’並加上保護層（25)以 圖，而圖之俯視圖；瞭解’圖2d係圖2a之俯視 實施例]。疋將積祖電路晶片以辉線與上電極相連接之另一種 圖4係根據本發明不同鲁、> 體電路杀韶t 實她例又具備過電壓保護功能之積 一. 其匕3在一基板（42)上形成 配=數個可變電阻材料層（44)，該可變電阻材料層係 接妯广基板义下表面。一接地導體層（43)係用以形成 ⑹孩接地端係配置於該基板下表面，延伸覆蓋各可 ^阻材料層，並與各該可變電阻材料層連接。多數導體 胃（41)係、用以形成電極端。各該導體層係配置在基板上 表面3穿延伸至基板下表面’並與各該可變電阻材料層 彼此相連接β 、圖5顯示根據本發明另_種實施例之具備過電壓保護功能 之積體電路承載基板，其包含在一基板（52)上具有一接 地導體層（53)，用以形成接地端，該接地端係配置於該 基板下表面。一或多數個可變電阻材料層（54),該可變 电阻材料層係貫穿配置在該基板中，並與該接地導體層彼 此相連接。多數導體層（51 )係用以形成電極端，各該導 心層係配置在該基板上表面，覆蓋在各該可變電阻材料層 上，並與各該可變電阻材料層彼此相連接。 當出現一突波（surge pulse)時，該突波的能量將會藉 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公爱） 1299559
由電極端進入，通過可變電阻材料層到地線。因為該可變 電阻材料層係非線性電阻材料及其結構之特性，該能量= 可以釋放到地線中，而不致對積體電路元件造成破壞，因 此達到保護積體電路元件之目的。 圖8a及8b係根據本發明一實施例之多層型具備過電壓保 護功能之積體電路承載基板形成過程之剖面圖。如圖“所 示 第基板（821)上形成有一或多數接地導體層 (8 3 )，用以形成接地端。該接地端係配置於該第一基板 下表面，f穿延伸至該第一基板之上表面，其中於該第一 基板t上表面露出一或多數個端點。該第一基板 之上表面上形成一或多數個可變電阻材料層（8 4 )。該可 變電阻材料層係配置在該接地導體層所露出之各端點上， 並與各接地導體層彼此相連接；並於該第一基板（821) 之上表面上尚形成有多數第一導體層（811)，各該導體 層（8 1 1 )係配置在該基板上，並延伸覆蓋各該可變電阻 材料層（84),與各該可變電阻材料層彼此相連接。該多 數第一導體層（811)f穿該第-基板（821)，並於該 第一基板（821)之上、下表面露出端點。. 如圖8b所π，一第二基板（822)上形成多數第二導體 層（812) ’用以形成電極端，其貫穿第二基板 (822) ’並於該第二基板（822)之上表面露出端點。 該第一基板（822 )覆蓋在第一基板（821)上表面上。 ▲第一導體層（8 1 1 )係與第二導體層（8 1 2 )彼此相互 連接°而孩圖將積體電路晶片（8 〇 )放置在該基板之配置 -10- 1299559 五、發明説明（8 情形與加上一保護層（85)之情形顯示出來。 圖6a、6b統係根據本發明—實施例之多層型具備過電壓 保護功能之積體電路承載基板形成過程之剖面圖。如圖“ 所不，於一第—基板“2"形成多數第—導體層 (6⑴。各該導體層（6U)係配置在該第_基板上， 並貫穿孩第-基板，於該第—基板上表面及下表面露出端 點。m ( 622 )上形成多數第：導體声 …2)。各該導體層（612)係貫穿第二基板於該第 二基板之上表面及下表面露出端點。接著，在該第二基板 (622) _L挖孔並置入—或多數個可變電阻材料層 (64)。各該可變電阻材料層（64)係貫穿配置在第二基 板’其上邵係於第二基板上表面露出端點。該第二基板 ( 622 )上形成一接地導體層（63)，用以形成接地端， 該接地端係配置於該基板（622)下表面。於一第三基板 ( 623 )上形成多數第三導體層（613)，用以形成電極 端，其貫穿第三基板’且於第三基板之上、下表面露出端 點。 如圖6b所示，該第二基板（622)覆蓋於第一基板上， 其中該可變電阻材料層之下部係與該接地導體層（63)相 連接，其下表面端點與該第一基板（621)之上表面端點 彼此相連接。該第三基板（62 3 )覆蓋於第二基板. (6 2 2 )上。該第三導體層（6丨3 )分別與可變電阻材料 層（64)及第二導體層（612)之上表面端點彼此相連 接。 _ -11 - 本紙張尺度適用中國國家標準(CNS) AA規格(21〇 X 297公釐） 1299559 發明説明（9 圖6 C所不，積體電路晶片（6 〇 )係放置在該第三基板 | 6 2 3 )上。該晶片以銲錫球與上電極相連接，並加上保 護層（6 5 )以防止灰塵及水氣進入。 圖7a 7b、7c、7d及7e係根據本發明一實施例之具備過電 壓保護功能之球格陣列式積體電路包裝形成過程之剖面 圖圖7 f係根據本發明一實施例之具備過電壓保護功能之 球格陣列式積體電路包裝之俯視圖。 如圖7 a所示’於一球格陣列式積體電路包裝中形成多數 接地導體層（7 3 1，7 3 2，7 3 3 )，用以形成接地端。該等接 地端係配置於該球格陣列式積體電路包裝之表面。如圖7 b 所示’於该等接地導電層上形成一或多數個可變電阻材料 層（74)。該可變電阻材料層係配置在該接地導體層所露 出 < 各端點上，並與各接地導體層彼此相連接。如圖7 c所 示’多數可變電阻材料層（7 4 )係用以連接電極端（7 1 ) 與接地導體層（731，732,733);圖7d所示，一第二保護 層（7 6 )係配置於該上電極及可變電阻材料層。圖7 e顯示 加上銲錫球後之本發明的剖面圖。 圖9a及圖9b係根據本發明之一種具備過電壓保護功能之積 體電路承載基板之製造過程中之剖面圖。 圖10a、10b、、l〇d、l〇e及l〇f顯示根據本發明一實施例 4形成過程中之具備過電壓保護功能之積體電路承載基板 之剖面圖。 根據本發明之_個實施例，形成該一具備過電壓保護功 能之積體電路承載基板包含下列步驟：如圖1 〇 a所示，首 _-12· 本紙張尺度適财S ®家標準(CNS) M規格(21QX 297公爱） 1299559
先於一基板（102),如圖1〇b所示，於該基板以雷射或 沖孔之方式挖出一或多數個所需要之孔洞。如圖1〇c所 不，於？豕孔洞中置入可變電阻材料層（丨〇 4 )，如圖夏〇 d 所不，於孩基板上表面形成多數下電極（i 〇·3 )，該等下 電極係覆蓋各該可變電阻材料層（1G4)，並彼此連接。 如圖1〇e所示，於該基板上表面形成多數上電極 (1 0 1 )，該等上電極係覆蓋各該可變電阻材料層 (1 0 4 )，並彼此連接。該形成上電極及下電極之方法可 用印刷之方式或是以金屬箔壓合之方式。如圖1〇f所示， 積體電路晶片（1 00 )形成在該基板（1〇2)後之剖面 本發明之特點及技術内容已充分揭示如上，任何熟習本 項技藝义人士可依據本發明之揭示及教示而作各種不背離 本發明精神4替換或修飾。因此本發明之保護範圍不應限 於所揭示之實施例，而應涵蓋這些替換及修飾。 -13-
本紙張尺度適用中國國家標準(CNS) A4規格（210X297公聲Y

Claims (1)

  1. 種具備過電壓保護功能之積體電路承載基板，包含： —基板（22,3 2 ); =地導體層（2 3,3 3 ) ’用以形成接地端，該接地 响係配置於該基板下表面並貫穿該基板而延伸至 其上表面，藉此於該基板之上表面露出一或多數 個端點； —或多數個可變電阻材料層（24,3 4 ),該可變電阻 材料層係配置在該接地導體層所露出之各端點 上，並與各接地導體層彼此相連接；以及 多數導體層（21，31)，用以形成電極端，各該導體 層係配置在該基板上，並覆蓋各該可變電阻材料 層，以與各該可變電阻材料層彼此相連接。 2· 一種具備過電壓保護功能之積體電路承載基板，包含： 一基板（4 2 ); —或多數個可變電阻材料層（44)，該可變電阻材 料層係配置在該基板之下表面； 一接地導體層（43)，用以形成接地端，該接地端 係配置於該基板下表面，延伸覆蓋各可變電阻材 料層’並與各該可變電阻材料層連接；以及 多數導體層（41)，用以形成電極端，各該導體層 係配置在基板上表面，並貫穿基板而延伸至其下 表面，以與各該可變電阻材料層彼此相連接。 3·—種具備過電壓保護功能之積體電路承載基板，包本： -14- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 1299559
    —基板（5 2 ); 一接地導體層（5 3 )，用以形成接地端，該接地端 係配置於該基板下表面； —或多數個可變電阻材料層（5 4 )，該可變電阻材 料層係貫穿該基板並與該接地導體層彼此相連 接；以及 多數導體層（51)，用以形成電極端，各該導體層 係配置在該基板上表面，並覆蓋各該可變電阻材 料層上以與各該可變電阻材料層彼此相連接。 4 ·種具備過電壓保護功能之積體電路承載基板，包含： 一第一基板（8 2 1 ); 一或多數接地導體層（8 3 )，用以形成接地端，該 接地端係配置於該第一基板下表面，並貫穿該第 一基板而延伸至其上表面，藉此於該第一基板之 上表面露出一或多數個端點； 一或多數個可變電阻材料層（8 4 )，該可變電阻材 料層係配置在該接地導體層所露出之各端點上， 並與各接地導體層彼此相連接； 多數第一導體層（811),各該導體層係配置在該基 板上，並覆蓋各該可變電阻材料層以與各該可變 電阻材料層彼此相連接，而該多數第一導體層貫 穿該第一基板，並於該第一基板之上下表面露出 端點； 一第二基板（822),該第二基板係配置在第一基板 -15-
    ABCD 1299559 六、申請專利範圍 上表面；以及 多數第二導體層（812)，用以形成電極端，其貫穿 第二基板，並與第一基板之第—導體層彼此相連 接’且於第一基板之上表面露出端點。 5·—種具備過電壓保護功能之積體電路承載基板，包含： 一第一基板（621 ); 多數第-導體層（611) ’各該第一導體層⑷。 係配置在該第-基板（621) ±，並貫穿該第一基 板而於該第-基板上表面及下表面露出端點； -第二基板（622)，該第二基板係配置在第一基板 上方； 多數第二導體層（612)，各該第二導體層（612) 係貫穿第二基板，於該第二基板之上表面及下表 面露出端點，其下表面端點與第一基板之上表面 端點彼此相連接； -接地導體層（63)，用以形成接地端，該接地端 係配置於該第二基板下表面； 一或多數個可變電阻材料層（64)，各該可變電阻 材料層係貫穿第二基板，以便其下部與該接地導 體層（63 )相連接，其上部係於第二基板上表面 露出端點； 第二基板（623)，該第三基板係配置在第二基板 上表面；以及 多數第三導體層（613)，用以形成電極端，其貫穿 -16· 本紙張尺度適用中國國家標準(CNS) A4規格[21〇X297公釐)—~一一~:----- ABCD 1299559 六、申請專利範圍 居弟二基板使其下部端點分別與該第二基板之第 二導體層與該接地導體層彼此相連接，且於第三 基板之上表面露出端點。 6.如申請專利範圍第丨至第5項中任一項之具備過電壓保護 功能之積體電路承載基板，其中該可變電阻材料層係非 線性電阻材料層。 7 ·如申請專利範圍第1至第5項中任一項之具備過電壓保護 功能之積體電路承載基板，其中該基板之材料可以是陶 瓷材料（ceramic materials)或高分子材料 materials)。 8·如申請專利範圍第丨至第5項中任一項之具備過電壓保護 功能之積體電路承載基板，其中該電極端與一晶片連 接’其連接可以是焊錫球之方式或是以引線焊接之方式 達成。 ^ 9 ·如申請專利範圍第丨至第5項中任一項之具備過電壓保護 功能<積體電路承載基板，進一步包含一保護層用以減 少外界環境所造成之影響。 1 0 · —種具備過電壓保護功能之球格陣列式積體電路包 裝，包含： ％ 一球格陣列式積體電路包裝； 多1接地導體層（731，7 3 2,7 3 3 )，用以形成接地 端，各該接地端係配置於該球格陣列式積體電路 包裝之表面； 一或多數個可變電阻材料層（74)，各該可變電阻材 -17- 本紙張尺度適财國國家標準(C_NS) A4規格(21GX 297 ------- 1299559 A B c D 六、申請專利範圍 料層係覆蓋在該接地導體層上，並與各接地導體 層彼此相連接；以及 多數電極端（7丨），其中該可變電阻材料層係連接 泫多數電極端（7 1 )與該多數接地導體層 (731，73 2,733)。 1 1 ·如申請專利範圍第丨〇項賴之具備過電壓保護功 旎之球格陣列式積體電路包裝，其中該基板之材料可以 疋陶t:材料（ceramic materials)或高分子.·材料 (polymer materials) 〇 1 2 ·如申請專利範圍第1 〇項之具備過電壓保護功 能之球格陣列式積體電路包裝，其中該電極端與一晶片 連接，其連接可以是焊錫球之方式或是以引線焊接之方 式達成。 1 3 ·如申請專利範圍第i 〇項摩糊關^之具備過電壓保護功 能之球格陣列式積體電路包裝，進一步包含一保護層用 以減少外界環境所造成之影響。 14· 一種製造具備過電壓保護功能之積體電路承載基板之 方法，包含下列步驟·· 於一基板（22)上形成一第一導體層以作為接地導體層 (23)，其中該第一導體層係形成於該基板之下表面並 貫穿該基板而延伸至其上表面，藉此於該基板之上表面 形成一或多數個端點； 於該基板上形成一或多數個可變電阻材料層（24)，其 中各該可變電阻材料層係覆蓋在該接地導體層所露出之 -18 - 本紙張尺度適用中國國家標準(CNS) A4規格7^ι〇Χ297公D _ ----- A B c D 1299559 各端點上，並與各接地導體層彼此相連接；以及 於基板上表面上形成多數第二導體層（21)，以作為上 電極，孩第二導體層係延伸覆蓋各該可變電阻材料層， 與各該可變電阻材料層彼此相連接。 1 5 · —種製造具備過電壓保護功能之積體電路承載基板之 方法，包含下列步驟： 於一基板上形成一第一導體層（41)以作為上電極，其 中該第一導體層係形成於該基板之上表面並貫穿至該基 板而延伸至其下表面，藉此於該基板之下表面形成一或 多數個端點； 於該基板形成一或多數個可變電阻材料層（44),其中 各該可變電阻材料層係配置在該接地導體層所露出之各 端點上’並與各接地導體層彼此相連接；以及 於基板上表面形成多數第二導體層（4 3 )，以作為接地 導體層，孩第二導體層係延伸覆蓋各該可變電阻材料 層，與各該可變電阻材料層彼此相連接。 16.—種製造具備過電壓保護功能之積體電路承載基板之 方法，包含下列步驟： 於一基板（102)上形成一導體層（1〇3); 蝕刻該導體層（10 3 )使之形成所需要之形狀，以作為 接地導體層（1 0 3 ); 將該基板挖出一或多數個所需要之孔洞； 將該基板反轉，並於該孔洞中置入可變電阻材料層 (104);以及 -19 - 本紙張尺度適用中國國家標準(CNS) A4規招^〇X297公酱)--------- A B c D 1299559 六、申請專利範圍^ ^ " 於該導體層（相對側之基板表面上形成多數上電極 (10 1)，各该上電極係覆蓋各該可變電阻材料層 (104)。 17.—種製造具備過電壓保護功能之積體電路承載基板之 方法，包含下列步騾： 糸第基板（821)上形成一或多數接地導體層 (8 3 )，以便形成接地端，該接地端貫穿延伸至 孩第一基板之上表面而配置於該第一基板下表 面，藉此於該第一基板之上表面露出一或多數個 端點； 於该第一基板（821)之上表面上形成一或多數個可 變電阻材料層（8 4 )，該可變電阻材料層係配置 在該接地導體層所露出於該基板之各端點上，並 與各接地導體層彼此相連接； 於該第一基板（821)之上表面上形成多數第一導體 層（8 1 1 )，各該導體層係配置在該基板上，並 覆盍各該可變電阻材料層（8 4 )，以與各該可變 電阻材料層彼此相連接，且該多數第一導體層 (811) 貫穿該第一基板（821)，並於該第一基 板（8 2 1 )之上下表面露出端點； 於一第二基板（822)形成多數第二導體層 (812) ’用以形成電極端，其貫穿第二基板 (822)，並於該第二基板（822)之上表面露出 端點；以及 -20- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 1299559 ABCD 六、申請專利範圍 將該第二基板（822)配置在第一基板（821)上表 面，其中該第一導體層（811)係與第二導體層 (8 1 2 )係彼此相互連接。 18·種製造具備過電壓保護功能之積體電路承載基板之 方法，包含下列步驟： 於一第一基板（62 1)上形成多數第一導體層 (6 1 1 )，各該導體層係貫穿該第一基板，於該 第一基板上表面及下表面露出端點； 於一第二基板（ 622 )形成多數第二導體層 (612)，各該導體層係貫穿第二基板，於該第二 基板之上表面及下表面露出端點，· 於該第二基板（ 622 )挖孔並置入一或多數個可變電 阻材料層（64)，各該可變電阻材料層係貫穿配 置在第二基板，其上部係於第二基板上表面露出 端點； 於孩第二基板（6 2 2 )上形成一接地導體層 (6 3 )，用以形成接地端，該接地端係配置於該 基板下表面； 將該第二基板（ 622 )配置於第一基板上，其中該可 變電阻材料層（64)之下部係與該接地導=層 (63)相連接，其下表面端點與該第一基板之上 表面端點彼此相連接； 於一弟三基板（623)形成多數第三導體層 (613),用以形成電極端，其貫穿第三基板，且 -21 - 本紙張尺度適用中國S家標準(CNS) A4規格(210X297公董) A8 B8 C8 D8
    1299559 六、申請專利範圍 於第三基板之上、下表面露出端點；以及 将該第三基板（ 6 2 3 )配置於第二基板（622 )上， 其中各该第二導體層（613)分別與可變電阻材料 層（64)及第二導體層之上表面端點彼此相連 接。 19· 一種製造具備過電壓保護功能之球格陣列式積體電路 包裝之方法，包含： 於一球格陣列式積體電路包裝中形成多數接地導體 層（731，732,733) ’用以形成接地端，各該接 地端係配置於該球格陣列式積體電路包裝之表 面； 於该多數接地導電層上形成一或多數個可變電阻材 料層（74) ’各該可變電阻材料層係配置在各該 接地導體層所露出之各端點上，並與各接地導體 層彼此相連接；以及 多數電極端（7 1 )，其中該可變電阻材料層係連接 該多數電極端（7 1 )與該多數接地導體層 (73 1，7 3 2,7 3 3 )。 2〇·如申請專利範圍第14至18項中任一項之方法，其中導 體層之形成步驟中，可包含下列步驟： 於该基板上旋塗（s p i η )光阻劑； 以微影術蝕刻出所需要之形狀。 2 1 ·如申印專利範圍弟1 4至1 8項中任一項之方法，其中光 -22- 本紙張尺度適用中國國家標準(CNS) Α4規格Τ^1〇Χ297公釐） 1299559
    1且劑係以清洗 22·如申請專利範圍第“至18項中任一 、 , 、'^方法，龙中1 板中孔洞之蝕刻係以雷射或沖孔之方式達成 /、Τ基 3 ·如申凊專利範圍第1 6或1 8項之方法，其 阻材料層係填入各該孔洞。 "各該可變 2 4 ·如申請專利範圍第Μ至1 8項中 月又万法，JL中 電極端係以印刷或金屬络壓合之方式形成於該基板上 2 5 ·如申請專利範圍第1 4至丨8項中任一項之方法二進一 包含該電極端與一晶片之連接，其連接可以是焊錫球 方式或是以引線焊接之方式達成。 電 該 步 之 -23- 本紙張尺度適用中國國家標準(CNS) A4規格(210x297公羡)
TW091113365A 2002-06-19 2002-06-19 Ic substrate with over voltage protection function and method for manufacturing the same TWI299559B (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
TW091113365A TWI299559B (en) 2002-06-19 2002-06-19 Ic substrate with over voltage protection function and method for manufacturing the same
KR1020030039162A KR20040002612A (ko) 2002-06-19 2003-06-17 과전압 보호 기능을 갖춘 ｉｃ 기판 및 이를 제조하는 방법
US10/463,984 US7053468B2 (en) 2002-06-19 2003-06-18 IC substrate having over voltage protection function
JP2003174086A JP2004023108A (ja) 2002-06-19 2003-06-18 過電圧保護機能を有するｉｃ基板およびこの基板を製作する方法
US11/363,564 US20060138608A1 (en) 2002-06-19 2006-02-28 IC substrate with over voltage protection function
US11/363,880 US20060138611A1 (en) 2002-06-19 2006-02-28 IC substrate with over voltage protection function
US11/363,773 US20060138610A1 (en) 2002-06-19 2006-02-28 Ball grid array IC substrate with over voltage protection function
US11/363,771 US7528467B2 (en) 2002-06-19 2006-02-28 IC substrate with over voltage protection function
US11/364,404 US7253505B2 (en) 2002-06-19 2006-02-28 IC substrate with over voltage protection function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW091113365A TWI299559B (en) 2002-06-19 2002-06-19 Ic substrate with over voltage protection function and method for manufacturing the same

Publications (1)

Publication Number Publication Date
TWI299559B true TWI299559B (en) 2008-08-01

Family

ID=29778228

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091113365A TWI299559B (en) 2002-06-19 2002-06-19 Ic substrate with over voltage protection function and method for manufacturing the same

Country Status (4)

Country Link
US (6) US7053468B2 (zh)
JP (1) JP2004023108A (zh)
KR (1) KR20040002612A (zh)
TW (1) TWI299559B (zh)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU6531600A (en) * 1999-08-27 2001-03-26 Lex Kosowsky Current carrying structure using voltage switchable dielectric material
US20100044080A1 (en) * 1999-08-27 2010-02-25 Lex Kosowsky Metal Deposition
US20100038119A1 (en) * 1999-08-27 2010-02-18 Lex Kosowsky Metal Deposition
US7825491B2 (en) 2005-11-22 2010-11-02 Shocking Technologies, Inc. Light-emitting device using voltage switchable dielectric material
US20100038121A1 (en) * 1999-08-27 2010-02-18 Lex Kosowsky Metal Deposition
US20100040896A1 (en) * 1999-08-27 2010-02-18 Lex Kosowsky Metal Deposition
US20100044079A1 (en) * 1999-08-27 2010-02-25 Lex Kosowsky Metal Deposition
US7612976B2 (en) * 2005-07-21 2009-11-03 Cooper Technologies Company Transient voltage protection circuit boards and manufacturing methods
KR20080084812A (ko) * 2005-11-22 2008-09-19 쇼킹 테크놀로지스 인코포레이티드 과전압 보호를 위해 전압 변환가능 재료를 포함하는 반도체디바이스
US7981325B2 (en) 2006-07-29 2011-07-19 Shocking Technologies, Inc. Electronic device for voltage switchable dielectric material having high aspect ratio particles
US20080029405A1 (en) * 2006-07-29 2008-02-07 Lex Kosowsky Voltage switchable dielectric material having conductive or semi-conductive organic material
EP2084748A4 (en) 2006-09-24 2011-09-28 Shocking Technologies Inc FORMULATIONS FOR A VOLTAGE-SWITCHABLE DIELECTRIC MATERIAL WITH A DEVICED VOLTAGE CONTACT BEHAVIOR AND METHOD OF MANUFACTURING THEREOF
US7812459B2 (en) * 2006-12-19 2010-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuits with protection layers
EP1990834B1 (en) * 2007-05-10 2012-08-15 Texas Instruments France Local integration of non-linear sheet in integrated circuit packages for ESD/EOS protection
US7793236B2 (en) * 2007-06-13 2010-09-07 Shocking Technologies, Inc. System and method for including protective voltage switchable dielectric material in the design or simulation of substrate devices
US8206614B2 (en) 2008-01-18 2012-06-26 Shocking Technologies, Inc. Voltage switchable dielectric material having bonded particle constituents
US8203421B2 (en) 2008-04-14 2012-06-19 Shocking Technologies, Inc. Substrate device or package using embedded layer of voltage switchable dielectric material in a vertical switching configuration
US9208930B2 (en) 2008-09-30 2015-12-08 Littelfuse, Inc. Voltage switchable dielectric material containing conductive core shelled particles
US9208931B2 (en) 2008-09-30 2015-12-08 Littelfuse, Inc. Voltage switchable dielectric material containing conductor-on-conductor core shelled particles
US8362871B2 (en) * 2008-11-05 2013-01-29 Shocking Technologies, Inc. Geometric and electric field considerations for including transient protective material in substrate devices
US8272123B2 (en) 2009-01-27 2012-09-25 Shocking Technologies, Inc. Substrates having voltage switchable dielectric materials
US9226391B2 (en) 2009-01-27 2015-12-29 Littelfuse, Inc. Substrates having voltage switchable dielectric materials
US8399773B2 (en) 2009-01-27 2013-03-19 Shocking Technologies, Inc. Substrates having voltage switchable dielectric materials
CN102550132A (zh) 2009-03-26 2012-07-04 肖克科技有限公司 具有电压可切换电介质材料的元件
US9053844B2 (en) 2009-09-09 2015-06-09 Littelfuse, Inc. Geometric configuration or alignment of protective material in a gap structure for electrical devices
US20110198544A1 (en) * 2010-02-18 2011-08-18 Lex Kosowsky EMI Voltage Switchable Dielectric Materials Having Nanophase Materials
US9082622B2 (en) 2010-02-26 2015-07-14 Littelfuse, Inc. Circuit elements comprising ferroic materials
US9224728B2 (en) 2010-02-26 2015-12-29 Littelfuse, Inc. Embedded protection against spurious electrical events
US9320135B2 (en) 2010-02-26 2016-04-19 Littelfuse, Inc. Electric discharge protection for surface mounted and embedded components
JP5960383B2 (ja) * 2010-06-01 2016-08-02 スリーエム イノベイティブ プロパティズ カンパニー 接触子ホルダ

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648364A (en) * 1970-04-30 1972-03-14 Hokuriku Elect Ind Method of making a printed resistor
EP0327860A1 (de) 1988-02-10 1989-08-16 Siemens Aktiengesellschaft Elektrisches Bauelement in Chip-Bauweise und Verfahren zu seiner Herstellung
US4993142A (en) 1989-06-19 1991-02-19 Dale Electronics, Inc. Method of making a thermistor
US6013423A (en) * 1991-08-22 2000-01-11 Fuji Photo Film Co., Ltd. Developing solution for silver halide photographic material and method for processing silver halide photographic material by using the same
WO1995031816A1 (en) 1994-05-16 1995-11-23 Raychem Corporation Electrical devices comprising a ptc resistive element
AU704862B2 (en) 1994-07-14 1999-05-06 Surgx Corporation Variable voltage protection structures and methods for making same
CN1094237C (zh) * 1994-07-14 2002-11-13 苏吉克斯公司 单层及多层可变电压保护装置及其制作方法
JP2679681B2 (ja) 1995-04-28 1997-11-19 日本電気株式会社 半導体装置、半導体装置用パッケージ及びその製造方法
US6172590B1 (en) * 1996-01-22 2001-01-09 Surgx Corporation Over-voltage protection device and method for making same
US5884391A (en) 1996-01-22 1999-03-23 Littelfuse, Inc. Process for manufacturing an electrical device comprising a PTC element
JPH09260106A (ja) 1996-03-22 1997-10-03 Murata Mfg Co Ltd 電子部品の製造方法
US5888837A (en) 1996-04-16 1999-03-30 General Electric Company Chip burn-in and test structure and method
US6013358A (en) 1997-11-18 2000-01-11 Cooper Industries, Inc. Transient voltage protection device with ceramic substrate
US20030161086A1 (en) * 2000-07-18 2003-08-28 X2Y Attenuators, Llc Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package
TW377504B (en) 1997-07-30 1999-12-21 Magnachip Semiconductor Ltd Semiconductor components using non-impedance materials for ESD protection
JP4000633B2 (ja) 1997-08-25 2007-10-31 株式会社デンソー 配線基板の製造方法
US6020808A (en) 1997-09-03 2000-02-01 Bourns Multifuse (Hong Kong) Ltd. Multilayer conductive polymer positive temperature coefficent device
JP3914620B2 (ja) * 1997-10-16 2007-05-16 シチズン時計株式会社 Ｉｃカード
US6242997B1 (en) 1998-03-05 2001-06-05 Bourns, Inc. Conductive polymer device and method of manufacturing same
US6549114B2 (en) * 1998-08-20 2003-04-15 Littelfuse, Inc. Protection of electrical devices with voltage variable materials
US6162159A (en) * 1998-08-24 2000-12-19 Martini; Calvin Duke Ticket dispenser
JP4419214B2 (ja) 1999-03-08 2010-02-24 パナソニック株式会社 チップ形ｐｔｃサーミスタ
US6429533B1 (en) 1999-11-23 2002-08-06 Bourns Inc. Conductive polymer device and method of manufacturing same
JP3822768B2 (ja) * 1999-12-03 2006-09-20 株式会社ルネサステクノロジ Ｉｃカードの製造方法
US6285275B1 (en) 2000-09-15 2001-09-04 Fuzetec Technology Co., Ltd. Surface mountable electrical device
US6297722B1 (en) 2000-09-15 2001-10-02 Fuzetec Technology Co., Ltd. Surface mountable electrical device
US6587008B2 (en) * 2000-09-22 2003-07-01 Kyocera Corporation Piezoelectric oscillator and a method for manufacturing the same
JP3649111B2 (ja) * 2000-10-24 2005-05-18 株式会社村田製作所 高周波回路基板およびそれを用いた高周波モジュールおよびそれを用いた電子装置
US6879492B2 (en) * 2001-03-28 2005-04-12 International Business Machines Corporation Hyperbga buildup laminate
US6806553B2 (en) * 2001-03-30 2004-10-19 Kyocera Corporation Tunable thin film capacitor
US6498715B2 (en) * 2001-05-15 2002-12-24 Inpaq Technology Co., Ltd. Stack up type low capacitance overvoltage protective device
TW529215B (en) * 2001-08-24 2003-04-21 Inpaq Technology Co Ltd IC carrying substrate with an over voltage protection function
TW510034B (en) * 2001-11-15 2002-11-11 Siliconware Precision Industries Co Ltd Ball grid array semiconductor package
CN1311553C (zh) 2001-12-12 2007-04-18 松下电器产业株式会社 非易失性存储器及其制造方法
JP2003189460A (ja) * 2001-12-17 2003-07-04 Yazaki Corp 過電流保護回路
US7196415B2 (en) * 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
JP4005451B2 (ja) * 2002-08-29 2007-11-07 富士通株式会社 多層基板及び半導体装置
US6972481B2 (en) 2002-09-17 2005-12-06 Chippac, Inc. Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
US7095053B2 (en) * 2003-05-05 2006-08-22 Lamina Ceramics, Inc. Light emitting diodes packaged for high temperature operation
JP4657640B2 (ja) 2004-07-21 2011-03-23 株式会社日立製作所 半導体装置
US7218492B2 (en) * 2004-09-17 2007-05-15 Electronic Polymers, Inc. Devices and systems for electrostatic discharge suppression
JP4215023B2 (ja) 2005-04-13 2009-01-28 ソニー株式会社 複数の半導体集積回路を備えた半導体装置及び半導体集積回路間の接続状態の検査方法

Also Published As

Publication number Publication date
KR20040002612A (ko) 2004-01-07
US20040000725A1 (en) 2004-01-01
US20060138611A1 (en) 2006-06-29
JP2004023108A (ja) 2004-01-22
US20060138608A1 (en) 2006-06-29
US7053468B2 (en) 2006-05-30
US20060138610A1 (en) 2006-06-29
US7528467B2 (en) 2009-05-05
US20060138609A1 (en) 2006-06-29
US20060138612A1 (en) 2006-06-29
US7253505B2 (en) 2007-08-07

Similar Documents

Publication Publication Date Title
TWI299559B (en) Ic substrate with over voltage protection function and method for manufacturing the same
TW571373B (en) Semiconductor device, circuit substrate, and electronic machine
TW498508B (en) Semiconductor package and method of fabricating the same
TW589930B (en) Electrostatic discharge protection device for a high density printed circuit board
TW388936B (en) Semiconductor device and manufacture thereof
JP5090749B2 (ja) 半導体パッケージ及びその製造方法
US20110075306A1 (en) Local integration of non-linear sheet i integrated circuit packages for esd/eos protection
JPH08172143A (ja) プリント配線板とこれを用いた電子装置
JP2009520368A5 (zh)
CN1878444A (zh) 静电放电防护的电路板
TWM324375U (en) Stacked packaging structure for communication module
TWI420988B (zh) 垂直結構被動元件的裝置和方法
WO2017024981A1 (zh) 一种端口防护电路集成封装件
TW440981B (en) Multiple line grids incorporating therein circuit elements
US20080083984A1 (en) Wiring board
TW529215B (en) IC carrying substrate with an over voltage protection function
JP2010272488A (ja) 小型コネクタに静電気保護部を組み込むこと
CN215871996U (zh) 一种抗高压电路板
KR100809711B1 (ko) 칩저항기가 리버스 형태로 실장되어 있는 반도체 메모리모듈
TW200820384A (en) Semiconductor device having a passive device
JPS6147689A (ja) プラグインパツケ−ジ
JPH0121566Y2 (zh)
KR100367729B1 (ko) 멀티플 라인 그리드 어레이 패키지
JPH03179796A (ja) ハイブリッド集積回路
JP3914478B2 (ja) Ｌｓｉチップ実装可撓配線板