TW377504B - Semiconductor components using non-impedance materials for ESD protection - Google Patents

Semiconductor components using non-impedance materials for ESD protection

Info

Publication number
TW377504B
TW377504B TW086110869A TW86110869A TW377504B TW 377504 B TW377504 B TW 377504B TW 086110869 A TW086110869 A TW 086110869A TW 86110869 A TW86110869 A TW 86110869A TW 377504 B TW377504 B TW 377504B
Authority
TW
Taiwan
Prior art keywords
esd protection
semiconductor components
impedance materials
impedance material
impedance
Prior art date
Application number
TW086110869A
Other languages
Chinese (zh)
Inventor
Ki-Won Hong
Nam-Ho Kim
Dae-Hyung Cho
Original Assignee
Magnachip Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Magnachip Semiconductor Ltd filed Critical Magnachip Semiconductor Ltd
Priority to TW086110869A priority Critical patent/TW377504B/en
Application granted granted Critical
Publication of TW377504B publication Critical patent/TW377504B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

This invention pertains to a kind of electro-static discharge protection and surge pulse protection implemented on packaged chips, independent of pre-buffer type of circuit protections, wherein the components includes: (1) all output legs of lead wire frame of specific voltage are connected to non-impedance material; or (2) power line, grounding wire, and output ports of internal circuit of the chip are connected to non-impedance material.
TW086110869A 1997-07-30 1997-07-30 Semiconductor components using non-impedance materials for ESD protection TW377504B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW086110869A TW377504B (en) 1997-07-30 1997-07-30 Semiconductor components using non-impedance materials for ESD protection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW086110869A TW377504B (en) 1997-07-30 1997-07-30 Semiconductor components using non-impedance materials for ESD protection

Publications (1)

Publication Number Publication Date
TW377504B true TW377504B (en) 1999-12-21

Family

ID=57942091

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086110869A TW377504B (en) 1997-07-30 1997-07-30 Semiconductor components using non-impedance materials for ESD protection

Country Status (1)

Country Link
TW (1) TW377504B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7528467B2 (en) 2002-06-19 2009-05-05 Inpaq Technology Co., Ltd. IC substrate with over voltage protection function

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7528467B2 (en) 2002-06-19 2009-05-05 Inpaq Technology Co., Ltd. IC substrate with over voltage protection function

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