TWI296441B - Semiconductor device including a superlattice with regions defining a semiconductor junction - Google Patents

Semiconductor device including a superlattice with regions defining a semiconductor junction Download PDF

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TWI296441B
TWI296441B TW095111313A TW95111313A TWI296441B TW I296441 B TWI296441 B TW I296441B TW 095111313 A TW095111313 A TW 095111313A TW 95111313 A TW95111313 A TW 95111313A TW I296441 B TWI296441 B TW I296441B
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semiconductor
layer
superlattice
semiconductor component
band
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TW200701452A (en
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J Mears Robert
John Stephenson Robert
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Mears Technologies Inc
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    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8254—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using II-VI technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

Description

I .1296441 f 九、發明說明： 【發明所屬之技術領域】 本申請案係為2003年8月22日提出之美國專利申請第腦7，_ 號之部份連續申請案(C〇ntmuati〇n_in_part ⑽ 腦7，_號係為屬年6月26日提出之美國專利申請第麵3 6%號 及第臟卿號兩申請案之部份連續申請案。上述各申請案之整體揭示 内容在此列為本發明之參考資料。 、 本發明係有關半導體之領域，且_是錢触能帶王程㈣职 band engineering)為基礎而具有增進特性之半導體及其相關之方法。 【先前技術】 利用諸如職1:荷雜(eharge earriera)之祕⑽bility)，以便增進半 導體元件性能之相_造及技術’已多有人提出。例如，CmTie等人之美國 # 專利申請第2003/0057416號案中揭示了石夕、矽领sili_-g_nium)、以及 釋力矽(relaxed silicon)與包括原本將會導致性能劣退的無雜質區 (impurity-freezones)等的形變材質層(伽inedmaterial心㈣。其在上矽層中 — 所形成的雙軸向形變(biaxial strain)改變了載體的動性，並得以製作較高速與 -/或較低功率的元件。FitZgerald等人的美國專利申請公告第2003/0034529 號案中則揭示了同樣亦以類似的形變矽技術咖_ smc〇n咏㈣㈣為 基礎的一種CMOS反向器(CMOS invertei〇。
Takagi的第6,472,685B2號美國專利中揭示了一種半導體元件，包含 有夾在销之間的-树及碳層，以使其第二销的傳導能帶(咖血= 5 1296441 band)及鍵結能帶(valence band)承受伸張形變(tensile stmin)。具有較小等效 質量(effectivemass)並由施加於閘電極上的電場所誘發的電子，便會被限制 在其第二矽層内，因此即可認定其n通道]^〇81^11得以具有較高的動性。
Ishibashi等人的第4,937,204號美國專利中揭示了一種超晶格，其中 包s整層的或部份層的雙元化合物(binary compound)的半導體層多層(少 於八個單層(monolayer))構造，係交替地以磊晶成長(epitaxialgr〇wth)的方式 . 增長而成。其中的主電流流動方向係垂直於超晶格中的各層平面。 馨\\^1^專人的第5,357，119號美國專利中揭示了8^^的一種短週期超 晶格(short period superlattice)，利用減低超晶格中的合金散佈⑽〇y scattering) 而達成其較咼的動性。依據類似的原理，Candelaria的美國第5,683,943號 專利中揭示了一種增進動性之MOSFET，其包含一通道層(channel layer)， 該通道層包括有矽合金與第二種物質，此第二種物質於矽晶格中係替代性 地出現’其成分百分比係能使通道層處於伸張應力(tensile stress)之狀態。
Tsii的第5,216,262號美國專利中揭示了一種量子井(quantum wel· φ 造，其包含有兩個屏蔽區(barrier region)以及夾在屏蔽區之間的一薄的磊晶 長成半導體層。其每一屏蔽區各係由厚度範圍大致在二至六個交疊的 Si02/Si單層所構成。屏蔽區之間亦另夾有更厚的矽材質部份。 一 2000年9月6日線上發行的應用物理及材料科學及製程(Applied
Physics and Materials Science & Processing)391 - 402 頁，一篇題為「石夕質奈 米構造元件中之現象」（“Phenomena in silicon nanostructure devices”)的文章 中，Tsu揭示了 一種矽及氧的半導體-原子超晶格(semic〇nduetOT_atQmk superlattice，SAS)。此Si/O超晶格構造被揭露為一種有用的碎量子及發光元 件。其中特別揭示了如何製作並測試一種綠色電輝光二極體 6 1296441 (electroluminescence diode)的構造。該二極體構造中的電流流動方向是垂直 的’亦即，垂直於SAS的層面。該文中所揭示的SAS可以包含半導體層， 半導體層之間係由諸如氧原子及CQ分子等被吸收的物質(adsGrbed species) 所分離開。被吸收的氧單層以外所長成的石夕，被描述是為j晶層，其具有 相當低的缺陷密度(defect density)。其中的一種SAS構造包含有一個u nm 尽度的石夕貝ap伤，其係約為八個石夕原子層，而其另一種構造中的石夕質部份 的厚度财其述厚度賴倍。物理評論通訊(Physies Review Let㈣，ν〇1· 89, • Ν〇· 7(2002年8月12日）中，Luo等人所發表的—篇題為「直接間隙發光石夕 之化學设計」（“Chemcal Desi职 of Direct-Gap Light-Emitting Silicon”)的文 ® 章，更進一步地討論了 Tsu的發光SAS構造。
Wang、Tsu及Lofgren等人的國際申請公報w〇 〇2/1〇3,767 A1號案中 揭不了財及氧，碳，氮，鱗，録，石巾或氫的—麵蔽建構區塊，其可以 將垂直流經晶袼的電流減小超過四個十之次方冪次尺度 orders of magnitude)。其、絕緣層/屏蔽層可容許在鄰接著絕緣層之處沉積有低缺陷度的 蠢晶砍。 藝 Mears #人在已公告的英國專利申請第Μ47，，號案中揭示，非週期 I*生光子此㈣隙的原理構造(aperi〇dic ph〇t〇nic band g叩，^BG)可應用於電 子能帶間隙工程(electronic bandgap engineering)之中。特別是該申請案中 ， 揭示，材料參數(material parameters)，例如，能帶最小值的位置，等效質量， - 等等，皆可加以調節，以便獲致具有所要能帶構造的特性之新的非週期性 材料/、他的參數，諸如導電性(electrjcal，熱傳導性(thermai conductivity)及介電係數（dielectric permittivi明或導磁係數㈣㈣c permeability) ’皆被宣稱亦可能被設計於材料之中。 1296441 賴材料X簡域之巾已有投人讀的努力，㈣圖增加半導體元件 巾的電荷健之雜，難間财很纽進的絲。歓_性可以增加 兀件的速度與/或減低元件的功率消耗。雖然3直的尺度縮得越來越小：若 有較大的動性，則元件仍可維持其性能。 【發明内容】 基於前述背景，本發明之—目的即在於，例如，提供-種製作具有較 高電荷載體之動性之半導體元件。 本發日狀上述及其他目的，雜及優關由—料導體元件提供，該半導 體70件包含形成-超晶格，而該超晶格則包含有複數個堆疊的層群組。超 格的每-個料組各包含有界定_基底謂部份的複數個堆疊基底石夕質 單層（stacked base silicon mon〇layers)，以及其上之一能帶修改層 (band-modifying layer)。能帶修改層包含至少一個非半導體單層，非半導^ 單層被限絲與其相鄰的基底半導體部份的—晶體晶格内。^格可進一 步包含至少一對以對向摻雜的區域(〇pp〇sitely_d〇ped regi〇ns)於其中，其界定 至少一半導體接面。因此，此種半導體元件可以有利地應用於數種用途之 中。例如，其應用用途可包括有二極體、場效或雙極電晶體、光學元件等 等。 該至少一對以對向摻雜的區域可包括彼此直接接觸之第一與第二區 域。或者’弟一與第二區域可以彼此互相分離。例如，該至少一對以對向 摻雜的區域亦可被安排於垂直方向，以使半導體接面以橫向方向延伸，或 者被安排於橫向方向，以使該至少一半導體接面於垂直方向延伸。 每一個能帶修改層可各包括諸如氧，氮，氟及碳_氧之非半導體。再 1296441 者，每一能帶修改層各係為單一單層的厚度，以及每一基底矽質部份各皆 小於八個單層的厚度。該超晶格於其頂部層組之上可更包含一基底半導體 蓋層。再者，所有的基底矽質部份全皆為相同數目單層之厚度，或者該些 基底矽質部份之中的至少某些係為不同數目單層之厚度。 【實施方式】 配合本發明說明書所附圖式，後面的說明文字段落之中將詳細說明本 發明，而圖式之中所顯示的係為本發明之較佳實施例。不過，本發明仍可 以許多種不同的形式實地施行，因此本發明之範疇當然不應限定於圖式中 所顯示之實施例上。相對地，此些實施例僅是被提供來使本發明所揭示之 發明内谷更為完整詳盡，並得使習於本技藝者能夠完全地瞭解本發明之範 缚。在本發明的整篇說明文字之中，相同的圖式參考標號係用以標示相同 或相當的元件’而加撇(prime)符號則係用以標示不同實施例中的類似元件。 本發明係相關於在原子或分子的層級上控制半導體材料的特性，以達成 增進半導體元件之性能。此外，本發明亦係有關於增進材料的辨別、創造 以及使用，以便將其應用於半導體元件的導電性通路之中。 本案申請人所提之理論顯示，本發明此地所揭示描述的某些超晶格構 造’可以降低電荷載體的等效質量，並藉由於此種降低可導致較高的電荷 載體動性，但申請人同時聲明本發明之範疇不應限定於此理論上。本發明 所屬技藝瘤域内的文獻之中，對於等效質量有多種定義加以描述說明。作 為等效質量上之增進的一種量測尺度，申請人使用r導電性反等效質量張 里」（conductivity reciprocal effective masstensor”），以]y^1 及 μ:1 分別代表電 子及電洞，其定義： 9 1296441 m:\AEf ^T) Σ S (Vkm，n)l (V^(k,n))y ¥^),EfJ) ^ e>ef b.z. 2 ~^f(E(KnlEFJ)d3k E>Ef B.Z. 為電子之定義，以及 E<Ef b.Z. -Σ ί(ν^-Λ (Vk帥，吨奶殉ς)，〜，7Vk E<Ef B.Z. X j(l-f(E(k9n)9EF9T))d3k 則為電洞之定義，其中/係為費米-狄拉克分佈(Fermi-Dirac distribution)， Ef為費米能量(Fermi energy) ’ T為溫度’ E(k，n)為電子在對應於波向量k 及第η個能帶的狀態之中的能量，下標1及』係對應笛卡兒座標(Cartesian coordinates)x，y及z，積分係在布里羅因區(B.Z.，Brillouin zone)進行，而加 總則是在電子及電洞的能帶分別高於及低於費米能量的能帶之中進行。 申請人對導電性反等效質量張量之定義，係使得材料之導電性反等效質 量張量之對應分量中的較大數值者，其導電性的張量分量(tens〇rial
component)亦得以較大些。在此申請人再度提起下述理論，即此地所描述說 明之超晶格其針對導電性反等效質量張量所設定之數值，係可增進材料的 導電性質，諸如典型地可使電荷載體傳輸有較佳之方向。適當張量項數的 倒數，在此被稱為是導電性等效質量。換句話說，若要描述半導體材料構 造的特性，«子/制的導電料效質量，以及在麵預定要傳輸的 方向上的計异結果，便可用來分辨出其功效已有增進的該些材料。 應用前述方式便可為特定目_選出具有齡能帶構造㈣料。參考 卜這樣的一種實例會是一半導體元件20，其包括-超晶格25，且有_ 以對向摻雜的區域21，22，其界定—半導體接面23。如圖所示之實例， ρ/ί^Γ具有P型導電性，第：區域22具有㈣導電性，藉此形成一 接面23。半導體元件2〇之膽接面構造可利於數種應用用途。舉例 Ϊ296441 言，如同熟習本技藝者眾所週知， 極性電晶體、光學元件等。 此等應用用途可包括二極體、場效或雙 如===’第—與第二_ 21，22係彼此直接互相接觸。第一 ” 2卜23亦被安排為橫向排列（也就是並鄰 ^大致於垂直方向延伸。在其他的構形之中，第一與第二區= 亦可被安齡《額，錢半導雜面23，大酬細_，如目2所示。 一考圖3所“述的另—種構形，半導體元件2()，，亦可包含鄰接著超晶格 的-半導體層24”。在圖示之例中，半導體層24”係垂直地位在超晶格^” 之上，，但是在其他的實施例中，如熟f本項技術領域者所可理解，半導體 曰24亦可錄超㉟格之下，或者躺地與超㉟格轉。軸林他實施例 中’接雜質所佔據的部份較小，在此，P型摻雜質涵蓋整個超晶格25”， 而N型摻雜質則涵蓋整個半導體層24”。 在又另種構形之中，第一與第二區域2卜22可彼此分隔開。特別表 考圖4 ’半導體元件20”，擁有一 p损構造，其具有介於n型推雜質的半 • 導體層24”，與P型摻雜質的超晶格25，”之間的一層本質半導體層(intrinsic ' SemiC〇nduCtor咖如’”。當然亦可利用其N與P型區域都位在超晶格25 内，例如分別介於元件20，20,的第一與第二區域2卜22及2i，A，的— 本質區域。 應注意的是，在某些實施例中亦可糊數對對向摻雜區域礼。以提供 多個半導體（也就是PN)接面。再者，第一或第二區域21，22其中之一 或更多者可與用於提供PNP或NPN構造的對向摻雜區域一起應用'，如同習 於本技藝者所可以理解的。亦可理解的是，第一與第二區域21，22不需要 總是被安排於垂直或橫向的方向上。也就是，區域21，22可被安排於一第 11 1296441 -對驗方向上，以使半導雜面23沿著與第-對角線方向橫切的第二對 角線方向延伸。舉例而言，如熟習本項技術者眾所週知，這可藉由以一角 度植入換雜質而達成。 額外地參考圖5與圖6，其材料或構造係超晶格25的形式，其構造係 於原子或分子層級控制，並可以利用習知的原子或分子層沉積的技術 (techniques of atomic or molecular layer deposition)製作形成。超晶格乃包括 有以堆疊形式安排的複數個的層組(layer gr〇UpS) 45a — 45n，透過參考圖5 之示意橫截面圖也許可最為清楚地瞭解。 » 超晶格25的每個層組45a-45η，如圖所示包含有分別界定對應基底半 導體部份(base semiconductor P〇rti〇n) 46a — 46η的複數個的堆疊的基底半導 體單層(base semiconductor monolayer) 46，以及其上的一個能帶修改層 (energybandmodifying layer) 50。為了說明清楚之故，能帶修改層5〇於圖5 之中係以雜點加以標示。 圖中所示之能帶修改層50在與其鄰接之基底半導體部份的晶體晶格内 • 包含有一非半導體單層(non_semic〇nduct〇r m〇n〇layer)。在其他實施例之 中，多於-個㈣種單層亦是可行的。應注意者，於此所指之非半導體單 層或半導鮮層係絲，如餘整體區塊之喊·，職耻單層的材 料可以是非轉體或半導體。也就是，如熟習本項技術者眾所週知，諸如 _ 轉翻材料的單-單層，並不必鋪現與其若形成整體區塊或相對之厚 層者時相同的特性。 申請人仍聲明本發明之範疇不應限定於其理論上，亦即能帶修改層5〇 及其所鄰接之基底半導體部份46a_ 46η，會使超晶格25在平行於層面之方 向上的電荷《，較之無此安排者，具有較低的適料電性等效質量。考 12 1296441 慮另-種方式，此平行方向係與堆疊的方向正交。能帶修改層5〇亦可能使 超晶格25具有一般常見的能帶構造。 本發明之理淪顯示，諸如圖中所顯示的M〇SFET 2〇之類的半導體元 件’基於較低的導電性等效質量，較之無此安排者，可享有更高的電荷載 體動性。在某些實施例之中，亦由於本發明所達成之能帶工程的成果，超 晶格25亦可以具有-個實質的直接能帶_，例如，其對光電元件而言乃° 有特別優點，以下將進一步詳細說明。 丨如同熟習於本技藝者所可以理解者，M〇SFET2〇的源極/汲極區Μ，^ 及閘極35,可被當成是導致電荷載體以相對於堆疊層組45& — 4如之各層平 仃的方向通過超晶格的區域。本發明亦以同樣方式考量其他類似的區域。 圖中亦顯示超晶格25包括有-蓋層(eap layer) %，其係位於頂部層組 45η之上。蓋層52亦可包含複數個的基底半導體單層恥。蓋層％可以擁 有2至1〇〇個單層的基底半導體，且其較佳者應為1〇至5〇個單層。 丨 每一個基底半導體部份46a-46η，可以包含有由IV族半導體，m々族 半導體，以及II-VI族半導體等所組成的群組之中所選定的一個基底半導 體。如同熟習於本技藝者所可以理解的，IV族半導體一詞當然亦包含了 IV-IV族的半導體。尤其是，基底半導體可包含諸如矽與鍺之至少其中之s一。 能帶修改層50可以包含有由諸如氧，氮，氟，以及碳·氧等的組合之 中選定的-種非半導體(non_semic〇nduct〇r)。非半導體可利崎相鄰層進行 沉積以利製程的進行，而亦得以擁有較可斯待的熱穩定性(thermally stable)。在其他的實施例之中，如同習於本技藝者所可以理解的，非半導體 亦可為另一種無機或有機物或化合物，其符合特定半導體的製作程序。尤 13 1296441 八疋，基底半導體可包含諸如梦與錯之至少其中之一。 子雜nglemolecularla帅另亦應注意的是，由單原子層所提例 tTm ^ 〇 ，考圖、中顯不了-種4/1的重覆構造，其係以⑨作為 體材料及以氧作為能雜輯料。射只有键的氧断紐置^佔滿。 在其他的實施例之中及/或在不隨料的情況之下，如㈣ ，財必蚊雜料蘭狀觀。㈣了解原子轉2 技云者所可以理解的情形，在本示意圖中亦可看出，在一特定單層之中， 原子並未沿-平面精確地排列。舉例而言，被佔據的較佳範圍係 瞻獅在 由於石夕及氧目前係被廣泛地應用於一般的半導體製程之中，製造業者因 此=得以使牀發騎描述的這些材料。原子或單層的沉積，亦是為目前 # 所=泛姻的技術。因此，如㈣於本技藝者所可以理解的，半導體元件 即得以立即地利用並實施本發明所揭示之超晶格25。 ‘ t請人仍聲明本發明之範料舰定於其理論上，亦即，就-個超晶格 - ㈣，像是超，料制層數最好麟七層或更少，贿超晶格 的月：在整體範圍内皆共通或相對地均勻，以便獲得所要的優點。圖5及6 中所^的4/1重覆構造，就si/0而言，其模型指出在χ方向上電子及電 洞的有較佳動性。例如，其電子(就整體區塊的石夕而言具等向性)經計算過的 導電性等效質量係為〇.26’而χ方向上的4/1⑽超晶格則為㈣，其結果， 兩者的_為0.46。同樣的’電洞方面的計算所得結果，整體區塊的石夕所 1296441 叶算出的數值為0.36，4/1 Si/O超晶格則為〇·16，兩者比例為〇叫 :然:種方向取性上的特性對某些半他 切體讀之中，平行於層組的群組平面中任何方向上均勻的: =能更為有利。對習財技藝者而言，啊增加電子及電^戈 、有增加其中一種電荷載體的動性，亦皆可能有其好處。動或 超晶格25之奶Sl/0實補中，其較低導電性等效質量可能 曰)=之導電性等效質量的三分之二之值還來得低，且此情形就電子。 洞兩者而言皆然。賴，如同習於本賴者所可以理解的，超晶㈣ 更可包含至少-種鶴的導祕雜f (_uetivitydQp㈣。 - 額外地同時參考圖7，接著描述依據本發明具有不同性質的超晶格％， 的另-實施例。在此實施例之中，其顯示3/1/5/1之重覆模式。更特定而言， 最底下的基底半導體部份46a，具有三個單層，而第二最底層 ❿ 部份她，則有五個單層。此種組合模式在整個超晶格25,之中重覆。·^能 帶修改層50,則各可以包含一個單一的單層。就包含了 _的此種超晶格 25而έ ’其電何载體動性的增進是與各層之平面中的指向無關的。圖7之 中在此未特別提及的其他構造部份係與前述圖$中所討論者類似， 不再重覆討論。 在某一元件實知例之中，超晶格的所有基底半導體部份，其厚度可能為 相同數目單層疊合的厚度。在其他的實施例之中，超晶格的至少某些基底 半導體部份，其厚度可能是為不同數目單層疊合之厚度。在另外的實施例 之中超Μ格的所有基底半導體部份，其厚度則可能完全是為不同數目單 層疊合之厚度。 15 1296441 圖8A-8C顯示應用密度功能理論Functi(mal 算的能帶構造。本技藝情廣柄知献，爾通常條轉_的絕對 值。因此間隙以上的所有能帶皆可利用適當的「剪刀形修正」㈤s咖 瞻eetiGn”)純偏移。不過，能帶_細是公認遠較為可靠 2 應在此等認知之下加以考量。 幻犯帶 圖8八為整體區塊的石夕（bulk silicon，實線表示)以及_ 5 —6中所顯示之 4/1 Si/Ο超晶格25(虛線表示），兩者由迦碼點(G)之處計算得之能帶構造之 曲線圖。雖然圖中其(001)之方向係與Si之一般單位晶元的(謝)方向相^， 然其方向係指4/1 Si/O結構之單位晶元(unit cell)而非Si的一般單位晶元， 並因而顯示了 Si傳導能帶最小值的期待位置。圖中的(1〇〇)及_)方向係與 Si之一般單位晶元的(110)及(_11〇)方向符合。習於本技藝者可以理解，圖;
Si之能帶係以摺合顯示，以表示他們在4/1 Si/〇構造之適當的反晶格方向 (reciprocal lattice directions)。 圖中可看出，與整體區塊矽相較之下，4/1 Si/O構造之傳導能帶最小值 係位於迦碼點(G)之處，而其鍵結能帶的最小值則是出現在(〇〇1)方向上，在 .布里羅因區(Brillouinzone)的邊緣，稱之為z點之處。另亦可以注意到，4/1 Si/Ο構造與si的傳導能帶最小值之曲率，其相較之下前者具有較大的曲 率’這是因為額外氧層引入了擾亂所造成的能帶分離之故。 * 圖8B為整體區塊石夕(實線)以及4/1 Si/Ο超晶格％ (虛線），兩者由z點 之處計算得的能帶構造之曲線圖。此圖中所顯示的是(100)方向上鍵結能帶 之增加曲率。 圖8C為整體區塊矽(實線)以及圖7中所顯示之5/1/3/1 Si/O超晶格25, (虛線），兩者由迦碼及Z點之處計算得之能帶構造之曲線圖。由於5/1/3/1 1296441
Si/O構造的_性，在⑽)及_)方向上計算所得雜帶結構是相 因此，在平仃於各層的平面，亦即，在垂直於剛的堆疊方向上，導 等效質量及動性可以職是等向性的。注意到在·/isi/〇的實例 傳導能帶最小值及鍵結能帶最大值兩者皆位於或近於2點之處。 u曲率的、加疋為等效質量減小的一個指標，但經由導電性反等效所 量張量的計算，仍可㈣㈣麵比較及_。此使得本料請人進二 推論，5/V3/1的超晶格25，實f上應是直接的能帶_。如同習於本二 斤可、里解的可供光學轉移(〇ρΜίΓ咖出⑽)的適當矩陣單元(峨^ element)乃是區別直接與間接能_隙行為的另—種指標。 就本發明之方法而言，其係用以製作半導體元件，該方法可包括形成_ 超晶格25，該超晶格25白人幻m %田t 成曰曰裕25包含多個堆疊的層群組必。超晶格25的每個 =5中==^物綱4⑽㈣,帶㈣ :中基底石夕貝早層46界定一基底半導體部份彻。能帶修改層^ =二限紐其相鄰基底半導體部份46的_晶體晶格内的至少― 方法可更包括在超晶格25中形成至少—對崎向摻雜的區域2] 2於该超09格25，界定至少_半導體接面23。 質(Η 3所£域，該第-區域包含—第-傳導型態的摻雜 二(圖3所讀實__)。在超晶格巾可形成至少—第二區域，料含一 示的實例為，’其與至少-第，界定了至 含====== 17 1296441
FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A
SUPERLATTICE WITH REGIONS DEFINING A SEMICONDUCTOR JUNCTION”)律師文件號62683 ;題為「包含超晶格及具有界定半導體接面 之摻雜區域之鄰接半導體層的半導體元件」（“SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ADJACENT SEMICONDUCTOR LAYER WITH DOPED REGIONS DEFINING A SEMICONDUCTOR JUNCTION”)律師文件號62693 ;以及題為「製作包含超晶格及具有界定半 導體接面之摻雜區域之鄰接半導體層的半導體元件之方法」（“method FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A , SUPERLATTICE AND ADJACENT SEMICONDUCTOR LAYER WITH DOPED REGIONS DEFINING A SEMICONDUCTOR JUNCTION”)律師文 件號62694的三件共同專利申請案中，該三案在此列為本案之參考。 習於本技藝者在瞭解了本案於前述說明文字及附圖所描述的發明揭示 内容、的情況之下，當可推知瞭解針對本發明的許多修改變動以及其他不同 的貫施例作法。因此，應予瞭解的是，本發明之範疇不應限定於前述特定 實施例的範圍，其他的修改變動及其他實施例仍應是屬本發明之精神範疇。 •【圖式簡單說明】 圖1_4之示意圖顯示依據本發明之不同實施例的半導體元件部份之横 截面圖。 、 圖5之示意圖為圖1之超晶格之大比例放大橫截面圖。 圖6之立體圖顯示圖1中超晶格之一部份之原子構造。 圖7之示意圖為一超晶格之另一實施例之大比例放大橫截面圖，該 晶格可應用在圖1之元件中。 ° 圖8A為習知技藝中之整體區塊矽以及圖丨、5與6中所顯示之 18 1296441 ，超晶格，兩者岭·(取錢算狀能帶之曲線圖。 圖犯為習知技藝中之整體區塊石夕以及圖i、5與6 ，超晶格’兩者由z點之錢算得之鮮觀之曲線圖。 圖8C為習知技藝中之整體區塊石夕以及圖7中所顯示之5娜Si/Ο超 晶格’兩者由迦碼及Z點之處計算得之能帶構造之鱗圖。 【主要元件符號說明】 20 21 22 26 35 45a 〜45η 46 46a〜46η、 50、50， 52 半導體元件 對向摻雜的第一區域 對向摻雜的第二區域 超晶格 閘極 46a’〜46η’ 堆疊層組 基底半導體單層 基底半導體部份 能帶修改層 蓋層 十、申請專利範圍：
1· 一種半導體元件，其包含： 一輕—晶—格，包含複數個堆疊的層群組； 該超晶格的每一個層群組各包含有界定了一個基底矽質部份之複數 個堆疊基底矽單層，以及其上之一能帶修改層； 該能帶修改層包含有限定於相鄰基底矽質部份一晶體晶格内的至少 一個非半導體單層；且 夕 的區域 該超晶袼其中包含界定了至少一半導體接面的至少一對以對向推雜

Claims (1)

1296441 ，超晶格，兩者岭·(取錢算狀能帶之曲線圖。 圖犯為習知技藝中之整體區塊石夕以及圖i、5與6 ，超晶格’兩者由z點之錢算得之鮮觀之曲線圖。 圖8C為習知技藝中之整體區塊石夕以及圖7中所顯示之5娜Si/Ο超 晶格’兩者由迦碼及Z點之處計算得之能帶構造之鱗圖。 【主要元件符號說明】 20 21 22 26 35 45a 〜45η 46 46a〜46η、 50、50， 52 半導體元件 對向摻雜的第一區域 對向摻雜的第二區域 超晶格 閘極 46a’〜46η’ 堆疊層組 基底半導體單層 基底半導體部份 能帶修改層 蓋層 十、申請專利範圍：
1· 一種半導體元件，其包含： 一輕—晶—格，包含複數個堆疊的層群組； 該超晶格的每一個層群組各包含有界定了一個基底矽質部份之複數 個堆疊基底矽單層，以及其上之一能帶修改層； 該能帶修改層包含有限定於相鄰基底矽質部份一晶體晶格内的至少 一個非半導體單層；且 夕 的區域 該超晶袼其中包含界定了至少一半導體接面的至少一對以對向推雜 1296441 2·申請專利範圍項丨之半導體元件，其中該至少—對以對向格雜的 區域包含彼此直接觸之第一與第二區域。 3.申請專利範_丨之半導體磁，其中該至少—對以對向摻雜的 區域包含彼此相分隔之第一與第二區域。 4· t赫職n項1之轉體元件，其巾該至少—對讀向摻雜的 11域被安排輕直方向，以使該至少-半導體接面崎向方向延伸。 ⑩ 5. t清專利範圍項[之半導體元件，其中該至少—對以對向播雜的 區域被安排為橫向方向，以使該至少一半導體接面以垂直方向延伸。 6·申請專利範圍項1之半導體元件，其中每一能帶修改層各包含氧。 7·巾請專利範Μ 1之轉體元件，其巾每—能帶修改層各包含由 氧’氮，氟及碳-氧所構成之群組中所選定的一非半導體。 δ·申請專利範圍項1之半導體元件，其中每一能帶修改層各係為一 單一單層的厚度。 • 9·申請專利範圍項1之半導體元件，其中每一基底矽質部份各皆小 於八個單層的厚度。 10. 申請專利範圍項1之半導體元件，其中該超晶格於一最頂部層組 之上更包含一基底半導體蓋層。 11. 中請專利範圍項1之半導體元件，其中所有的該些基底㈣部份 1296441 全皆為相同數目單層之厚度。 12.申請專利範圍項1之半導體元件，其中該些基底矽質部份之中的 至少某些係為不同數目單層之厚度。 13· —種半導體元件，其包含： 一超晶格，其包含複數個堆疊的層群組； 該超晶格的每一個層群組各包含有界定了一個基底矽質部份之複數 個堆疊矽單層，以及其上之一能帶修改層； > 該能帶修改層包含有限定於相鄰基底矽質部份的一晶體晶格内的至 少一個氧單層；且 該超晶格其中包含界定了至少一半導體接面的至少一對彼此直接觸 之對向摻雜區域，並。 H. t料利細項Π之半導體元件，其巾該至少—對對向換雜區 域被安排於垂直方向上，以使該至少—半導體接面以橫向方向延伸/ 舰請專圍項13之半導體元件，其中該至少一對對向摻雜區 域被知排為勤方向，以使得該至少—半導體接面於垂直方向延伸。 -單二層範圍項13之半導體元件，其中每—能帶修改層各係為 17·申請專利範圍項13之半導體元件， 小於八個單層的厚度。 18·申請專利範圍項13之半導體元件， 其中每一基底矽質部份各皆 其中該超晶格於一最頂部層 21 1296441 組之上更包含一基底半導體蓋層。 19. 申請專利範圍項13之半導體元件，其中所有的該些基底矽質部 份全皆為相同數目單層之厚度。 20. 申請專利範圍項13之半導體元件，其中該些基底矽質部份之中 的至少某些係為不同數目單層之厚度。
22
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CA2603477A1 (en) 2006-10-12
JP2008535265A (ja) 2008-08-28
US20050167653A1 (en) 2005-08-04
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EP1872404A1 (en) 2008-01-02
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