TWI292948B - - Google Patents
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- Publication number
- TWI292948B TWI292948B TW93134892A TW93134892A TWI292948B TW I292948 B TWI292948 B TW I292948B TW 93134892 A TW93134892 A TW 93134892A TW 93134892 A TW93134892 A TW 93134892A TW I292948 B TWI292948 B TW I292948B
- Authority
- TW
- Taiwan
- Prior art keywords
- electronic component
- layer
- metal
- circuit
- substrate
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Wire Bonding (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
1292948 九、發明說明： 【發明所屬之技術領域】 本發明係關於電路基板之構造與其製造方法及電子零 件之構裝方法，特別是構裝半導體裝置之電路基板。 【先前技術】 近年，對於行動電話等小型電子機器’搭載於電子機 為之構裝基板的細微化、高密度化之要求日益提高。隨此， ZC晶片等晶片零件構裝於基板的方法，亦漸漸往可更高密 度化之方法變遷。以習知正面朝上方式進行構裝之打線接 合，由於零件構裝所需面積大，因此為了更高密度地構裝， 以正面朝下方式進行構裝之覆晶構裝，已漸漸成為高密度 構裝基板之構裝方法的主流。 進行覆sa構裝時，係於1C晶片側形成焊料凸塊， 以覆晶接合器構裝於基板後，以熔焊（refl〇w)方式熔融焊 料，進行連接。以此時之焊料凸塊高度，來控制ic晶片盥 接合焊墊之間隙的量，亦即IC晶片之高度。以下，說明控 制1C晶片高度的理由。由於IC晶片與構裝基板之線熱膨 系數不同，因此為防止此應力施加於焊料而從構步美搞 =之接合烊墊剝落，需進行在IC晶片與構裝基板間注入被 稱為底層填料之熱硬化性樹脂的步驟。由於此熱硬化性樹 脂是利用毛細管現象，故需要控制IC晶片之高度。特別是， 近=普及之無鉛焊料其熔焊溫度亦較共晶焊料為高，因此 IC晶片高度之控制變得困難。 根據專利文獻1，最近。由於元件之多引腳化，焊料凸 1292948 塊及構裝基板之接合焊塾的間隔大幅變窄，高度亦變低。 因此’ IC曰曰曰片與接合焊墊之距離亦變窄，而產生熱硬化樹 脂之注入困難、有時甚至無法注入的問題，導致有無法確 保ic晶片與構裝基板間之接合可靠性的情形。對此問題， 於專利文獻1中揭示了在晶片側以電鑛方式形成炼焊無法 熔融之金屬凸塊。 “又於專利文獻2中揭示了在基板之接合焊墊側，以 電鍍方式形成熔焊無法熔融之金屬凸塊。然而，由於此等 方=之步驟數皆多且繁雜，且在10晶片或基板之接合焊墊 上施以電鍍’因此K：晶片之凸塊及接合焊墊之間隔的細微 化困難。 此外，於專利文獻3中雖揭示在基板之接合焊墊側， 以蝕刻形成熔焊亦無法熔融之金屬凸塊，但為確保π晶片 之尚度，金屬凸塊之高度、亦即所用材料之厚度會變厚， 匕名人以狹乍間隔來形成凸塊是非常困難，係一無法因應 基板之接合焊墊細微化的方法。 圖5，係顯示習知電路基板之製造方法及對電路基板之 片構破方法的製程圖，首先，如該圖之（1)所示，準備單 銅4層13之絕緣基材12，亦即準備單面銅積層板14。 接著’如該圖之（2)所示’對該單面銅積層板14之銅箔 層 13，德 曰 更用一般光加工方法之蝕刻方法，形成電路配線圖 :· 視需要設置防焊層、或以無電解鍍敷等方法來形成 U以作為表面處理層，再以模具沖廢等進行外形加 工’而得電路基板15。 1292948 圖2,係顯示本發明電子零件之構裝方法的製程圖，首 先，如该圖2之（1)所示，準備具有焊料凸塊9之IC；晶片 10，使用覆晶接合器，以正面朝下方式構裝於以圖i所示 衣莸製造之電路基板8上。之後，進行熔焊，使該IC晶片 10之焊料凸塊9熔融，將IC晶片1〇與電路基板8加以連 接。此時，藉由電路基板8上之金屬突起7，規定IC晶片 之高度。 接著，如該圖2之（2)所示，藉由IC晶片1〇與電路基 反8間注入熱硬化樹月旨…乍為底層填料，^IC晶片1〇 正面朝下於電路基板8之構裝。 圖 呀巫攸心得造的概念性截®傅力乂 二具有用來規定!。晶片高度之金屬突起7的電路基板8, 路^線圖案5埋人絕緣層6之構造。又，如圖4所示， 晶片10以正面朝下方式構裝於電路基板8時，心曰曰 離電路基板8之高度由金屬突起7加以規定。 L圖式簡單說明】 係顯示本發明電路基板之製造方法的製程圖。 二’係顯示本發明電子零件之構裝方法的製程圖。 圖。…係顯示本發明電路基板之構造的概念性截面構成 態之概念性截面構成圖 圖5係說明習知方法之電路基板之製诰f 件之構襄方法的圖。 i板之“方法及電子零 10 1292948 . 【主要元件代表符號】 1， 3 ： 銅 箔 2 鎳 箔 4 金 屬 基材 5 電 路 配線圖案 6 絕 緣 層 7 金 屬 突起 8，15 :電路基板 9 :焊料凸塊
10: 1C晶片 11 : 熱硬化樹脂 12 ： 絕緣基材 13 ： 銅箔層 14 : 單面銅積層板 11
Claims (1)
1292948 ώι 辱 ..太 ^利申職帛 93134892^¾¾¾¾¾^^、申請專利範面： 2007年5月 •一種電路基板之製造方法，其特徵在於·· 、準備出於第一導電層與第二導電層間具有異種金屬層 (作為蝕刻阻止層)的金屬箔，於該第一導電層以蝕刻形成 電路，線圖案’將黏著性絕緣樹脂黏著於該電路配線圖案 側藉由姓刻該第二導電層來形成突起，之後去除該作為 蝕刻阻止層之異種金屬層。 2·一種電子零件之構裝方法，其特徵在於·· θ準備電路基板，此電路基板係於第—導電層與由即使 在焊料熔融之溫度下亦不會溶融之金屬構成的第二導電層 間：準備具有作為餘刻阻止層之異種金屬層的金屬羯，於 该弟-導電層以蝕刻形成含電子零件接合焊墊之電路配線 圖案’將黏著性絕緣樹脂黏著於該電路配線圖案侧，藉由 :刻該第二導電層而於該電子零件接合焊墊附近形成金屬 ，之錢由去除該作為#刻m止層之異種金屬層來形 成該金屬突起；於該電路基板之電子零件接合焊塾上，將 :有焊料凸塊之電子零件’在使該焊料凸塊與該電子零件 合焊墊對位後搭載於該電子零件接合焊墊；之後，將搭 :該電子零件之該電路基板於以該焊料凸塊熔融之溫度 -焊之際，藉由該金屬突起’於該電路基板與該電子零 仵之間形成與該金屬突起等高度之間隙。 十一、明式： 如次頁。 12
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004080202A JP3946200B2 (ja) | 2004-03-19 | 2004-03-19 | 電子部品の実装方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200532879A TW200532879A (en) | 2005-10-01 |
| TWI292948B true TWI292948B (zh) | 2008-01-21 |
Family
ID=35050399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW93134892A TW200532879A (en) | 2004-03-19 | 2004-11-15 | Circuit substrate and method for mounting electronic element |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3946200B2 (zh) |
| CN (1) | CN100490610C (zh) |
| TW (1) | TW200532879A (zh) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080116587A1 (en) * | 2006-11-16 | 2008-05-22 | Chun Ho Fan | Conductor polymer composite carrier with isoproperty conductive columns |
| US20090115060A1 (en) | 2007-11-01 | 2009-05-07 | Infineon Technologies Ag | Integrated circuit device and method |
| TWI577260B (zh) * | 2010-03-16 | 2017-04-01 | Unitech Printed Circuit Board Corp | A multi - layer circuit board manufacturing method for embedded electronic components |
| US8710654B2 (en) | 2011-05-26 | 2014-04-29 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| KR101709468B1 (ko) * | 2015-06-19 | 2017-03-09 | 주식회사 심텍 | Pop 구조용 인쇄회로기판, 그 제조 방법 및 이를 이용하는 소자 패키지 |
-
2004
- 2004-03-19 JP JP2004080202A patent/JP3946200B2/ja not_active Expired - Fee Related
- 2004-11-15 TW TW93134892A patent/TW200532879A/zh not_active IP Right Cessation
-
2005
- 2005-03-21 CN CN 200510056005 patent/CN100490610C/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3946200B2 (ja) | 2007-07-18 |
| TW200532879A (en) | 2005-10-01 |
| CN100490610C (zh) | 2009-05-20 |
| CN1678173A (zh) | 2005-10-05 |
| JP2005268594A (ja) | 2005-09-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |