TWI291701B - Memory system, memory device, and output data strobe signal generating method - Google Patents

Memory system, memory device, and output data strobe signal generating method Download PDF

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Publication number
TWI291701B
TWI291701B TW094136509A TW94136509A TWI291701B TW I291701 B TWI291701 B TW I291701B TW 094136509 A TW094136509 A TW 094136509A TW 94136509 A TW94136509 A TW 94136509A TW I291701 B TWI291701 B TW I291701B
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TW
Taiwan
Prior art keywords
signal
read
command
cycles
output
Prior art date
Application number
TW094136509A
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English (en)
Chinese (zh)
Other versions
TW200625334A (en
Inventor
Kwang-Il Park
Seong-Jin Jang
Ho-Young Song
Original Assignee
Samsung Electronics Co Ltd
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Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200625334A publication Critical patent/TW200625334A/zh
Application granted granted Critical
Publication of TWI291701B publication Critical patent/TWI291701B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

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  • Dram (AREA)
TW094136509A 2004-10-19 2005-10-19 Memory system, memory device, and output data strobe signal generating method TWI291701B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040083745A KR100568546B1 (ko) 2004-10-19 2004-10-19 메모리 시스템, 반도체 메모리 장치, 및 이 시스템과장치의 출력 데이터 스트로우브 신호 발생 방법

Publications (2)

Publication Number Publication Date
TW200625334A TW200625334A (en) 2006-07-16
TWI291701B true TWI291701B (en) 2007-12-21

Family

ID=36129183

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094136509A TWI291701B (en) 2004-10-19 2005-10-19 Memory system, memory device, and output data strobe signal generating method

Country Status (6)

Country Link
US (3) US7362648B2 (enExample)
JP (1) JP4860231B2 (enExample)
KR (1) KR100568546B1 (enExample)
CN (1) CN100405327C (enExample)
DE (1) DE102005051206B4 (enExample)
TW (1) TWI291701B (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2311850A1 (en) * 2001-08-31 2011-04-20 BTG International Limited Anti-cancer cyclopenta[g]quinazoline compounds
US7916574B1 (en) * 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
KR100568546B1 (ko) * 2004-10-19 2006-04-07 삼성전자주식회사 메모리 시스템, 반도체 메모리 장치, 및 이 시스템과장치의 출력 데이터 스트로우브 신호 발생 방법
US7280417B2 (en) * 2005-04-26 2007-10-09 Micron Technology, Inc. System and method for capturing data signals using a data strobe signal
KR100755371B1 (ko) * 2005-05-03 2007-09-04 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 데이터 스트로우브 신호발생방법
US7701786B2 (en) * 2005-09-29 2010-04-20 Hynix Semiconductor, Inc. Semiconductor memory device
US8054928B2 (en) * 2005-11-14 2011-11-08 Ati Technologies, Inc. Programmable preamble system and method
JP4267002B2 (ja) * 2006-06-08 2009-05-27 エルピーダメモリ株式会社 コントローラ及びメモリを備えるシステム
KR100805004B1 (ko) * 2006-06-15 2008-02-20 주식회사 하이닉스반도체 조절 가능한 프리앰블 값에 기초하여 데이터 스트로브신호를 발생하는 데이터 스트로브 신호 발생기 및 이를포함하는 반도체 메모리 장치
WO2008079910A2 (en) 2006-12-20 2008-07-03 Rambus Inc. Strobe acquisition and tracking
US20080159454A1 (en) * 2006-12-27 2008-07-03 National Taiwan University Network on chip device and on-chip data transmission device
KR100883140B1 (ko) * 2007-11-02 2009-02-10 주식회사 하이닉스반도체 데이터 출력 제어회로, 반도체 메모리 장치 및 그의 동작방법
KR101529291B1 (ko) 2008-02-27 2015-06-17 삼성전자주식회사 플래시 메모리 장치 및 그것을 포함한 플래시 메모리시스템
KR101040242B1 (ko) 2008-10-13 2011-06-09 주식회사 하이닉스반도체 데이터 스트로브 신호 생성장치 및 이를 이용하는 반도체 메모리 장치
US8250287B1 (en) * 2008-12-31 2012-08-21 Micron Technology, Inc. Enhanced throughput for serial flash memory, including streaming mode operations
US9665507B2 (en) 2010-07-22 2017-05-30 Rambus Inc. Protocol including a command-specified timing reference signal
KR101780422B1 (ko) 2010-11-15 2017-09-22 삼성전자주식회사 불휘발성 메모리 장치, 그것의 읽기 방법, 그리고 그것을 포함하는 메모리 시스템
CN103312302B (zh) * 2013-06-24 2016-02-03 浙江禾川科技股份有限公司 单主站多从站结构的通信系统和多路扫描选通信号发生器
CN109343794B (zh) * 2018-09-12 2021-11-09 杭州晨晓科技股份有限公司 一种存储器的配置方法及配置装置
KR102787562B1 (ko) * 2019-11-21 2025-03-31 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
US11645155B2 (en) * 2021-02-22 2023-05-09 Nxp B.V. Safe-stating a system interconnect within a data processing system
US11816352B2 (en) * 2021-10-22 2023-11-14 Realtek Semiconductor Corporation Electronic device, data strobe gate signal generator circuit and data strobe gate signal generating method
US12223205B2 (en) * 2023-04-13 2025-02-11 Innogrit Technologies Co., Ltd. Systems, methods and devices for reading a memory of a storage device
US12499927B2 (en) 2023-12-26 2025-12-16 Nanya Technology Corporation Memory device with receiver circuit to suppress noise on data strobe signals

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003526B1 (ko) * 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
US6279116B1 (en) * 1992-10-02 2001-08-21 Samsung Electronics Co., Ltd. Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation
JP3979690B2 (ja) 1996-12-27 2007-09-19 富士通株式会社 半導体記憶装置システム及び半導体記憶装置
JP3445476B2 (ja) 1997-10-02 2003-09-08 株式会社東芝 半導体メモリシステム
KR100364127B1 (ko) * 1997-12-29 2003-04-11 주식회사 하이닉스반도체 칩-세트
US6557071B2 (en) 1998-06-22 2003-04-29 Intel Corporation Memory system including a memory controller having a data strobe generator and method for accesing a memory using a data storage
KR100303775B1 (ko) * 1998-10-28 2001-09-24 박종섭 디디알 에스디램에서 데이터스트로브신호를 제어하기 위한 방법및 장치
KR100333683B1 (ko) * 1998-12-30 2002-06-20 박종섭 반도체장치의데이터스트로브신호발생기
TW530207B (en) 2000-09-05 2003-05-01 Samsung Electronics Co Ltd Semiconductor memory device having altered clock frequency for address and/or command signals, and memory module and system having the same
JP2002169721A (ja) * 2000-11-30 2002-06-14 Hitachi Ltd 情報処理システム
JP2002216472A (ja) * 2001-01-22 2002-08-02 Nec Corp 半導体記憶装置
JP2002324398A (ja) 2001-04-25 2002-11-08 Mitsubishi Electric Corp 半導体記憶装置、メモリシステムおよびメモリモジュール
KR100416796B1 (ko) * 2001-07-20 2004-01-31 삼성전자주식회사 반도체 메모리 장치의 명령어 디코더 및 디코딩 방법
KR100507876B1 (ko) 2002-03-29 2005-08-17 주식회사 하이닉스반도체 로우 레이턴시 리드를 위한 데이터 스토로브 신호제어부를 포함하는 동기식 메모리장치
KR100480598B1 (ko) * 2002-05-25 2005-04-06 삼성전자주식회사 프리앰블 기능을 갖는 반도체 메모리 장치
US6819599B2 (en) * 2002-08-01 2004-11-16 Micron Technology, Inc. Programmable DQS preamble
KR100468776B1 (ko) * 2002-12-10 2005-01-29 삼성전자주식회사 클락 지터의 영향을 감소시킬 수 있는 동기식 반도체메모리장치
JP2004273008A (ja) * 2003-03-07 2004-09-30 Elpida Memory Inc クロック同期式半導体記憶装置
US6996016B2 (en) * 2003-09-30 2006-02-07 Infineon Technologies Ag Echo clock on memory system having wait information
US7716160B2 (en) * 2003-11-07 2010-05-11 Alien Technology Corporation Methods and apparatuses to identify devices
KR100568546B1 (ko) * 2004-10-19 2006-04-07 삼성전자주식회사 메모리 시스템, 반도체 메모리 장치, 및 이 시스템과장치의 출력 데이터 스트로우브 신호 발생 방법
KR100637098B1 (ko) * 2004-12-28 2006-10-23 주식회사 하이닉스반도체 데이터 스트로브 신호 생성 회로 및 데이터 스트로브 신호생성 방법

Also Published As

Publication number Publication date
DE102005051206A1 (de) 2006-04-27
JP4860231B2 (ja) 2012-01-25
US7733715B2 (en) 2010-06-08
JP2006120307A (ja) 2006-05-11
CN100405327C (zh) 2008-07-23
DE102005051206B4 (de) 2009-08-27
CN1783028A (zh) 2006-06-07
US8004911B2 (en) 2011-08-23
TW200625334A (en) 2006-07-16
US7362648B2 (en) 2008-04-22
US20060083081A1 (en) 2006-04-20
US20080144406A1 (en) 2008-06-19
KR100568546B1 (ko) 2006-04-07
US20100284231A1 (en) 2010-11-11

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