TWI291179B - Method for defining the initial state of static random access memory - Google Patents

Method for defining the initial state of static random access memory Download PDF

Info

Publication number
TWI291179B
TWI291179B TW092125647A TW92125647A TWI291179B TW I291179 B TWI291179 B TW I291179B TW 092125647 A TW092125647 A TW 092125647A TW 92125647 A TW92125647 A TW 92125647A TW I291179 B TWI291179 B TW I291179B
Authority
TW
Taiwan
Prior art keywords
initial state
memory
mosfets
memory unit
controlling
Prior art date
Application number
TW092125647A
Other languages
English (en)
Chinese (zh)
Other versions
TW200414224A (en
Inventor
Paul Arthur Layman
Samir Chaudhry
James Gary Norman
J Ross Thomson
Original Assignee
Agere Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Inc filed Critical Agere Systems Inc
Publication of TW200414224A publication Critical patent/TW200414224A/zh
Application granted granted Critical
Publication of TWI291179B publication Critical patent/TWI291179B/zh

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
TW092125647A 2002-09-30 2003-09-17 Method for defining the initial state of static random access memory TWI291179B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/262,631 US6906962B2 (en) 2002-09-30 2002-09-30 Method for defining the initial state of static random access memory

Publications (2)

Publication Number Publication Date
TW200414224A TW200414224A (en) 2004-08-01
TWI291179B true TWI291179B (en) 2007-12-11

Family

ID=28454433

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092125647A TWI291179B (en) 2002-09-30 2003-09-17 Method for defining the initial state of static random access memory

Country Status (5)

Country Link
US (1) US6906962B2 (https=)
JP (1) JP2004127499A (https=)
KR (1) KR101026335B1 (https=)
GB (1) GB2394338B (https=)
TW (1) TWI291179B (https=)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4169592B2 (ja) * 2002-12-19 2008-10-22 株式会社NSCore Cmis型半導体不揮発記憶回路
JP4532951B2 (ja) * 2004-03-24 2010-08-25 川崎マイクロエレクトロニクス株式会社 半導体集積回路の使用方法および半導体集積回路
JP2006127737A (ja) * 2004-09-30 2006-05-18 Nscore:Kk 不揮発性メモリ回路
US20060139995A1 (en) * 2004-12-28 2006-06-29 Ali Keshavarzi One time programmable memory
US7149104B1 (en) 2005-07-13 2006-12-12 Nscore Inc. Storage and recovery of data based on change in MIS transistor characteristics
US7193888B2 (en) * 2005-07-13 2007-03-20 Nscore Inc. Nonvolatile memory circuit based on change in MIS transistor characteristics
FR2891652A1 (fr) * 2005-10-03 2007-04-06 St Microelectronics Sa Cellule de memoire vive sram asymetrique a six transistors.
US7835196B2 (en) * 2005-10-03 2010-11-16 Nscore Inc. Nonvolatile memory device storing data based on change in transistor characteristics
US7321505B2 (en) * 2006-03-03 2008-01-22 Nscore, Inc. Nonvolatile memory utilizing asymmetric characteristics of hot-carrier effect
US7414903B2 (en) * 2006-04-28 2008-08-19 Nscore Inc. Nonvolatile memory device with test mechanism
US20080019162A1 (en) * 2006-07-21 2008-01-24 Taku Ogura Non-volatile semiconductor storage device
US20080037324A1 (en) * 2006-08-14 2008-02-14 Geoffrey Wen-Tai Shuy Electrical thin film memory
US7342821B1 (en) 2006-09-08 2008-03-11 Nscore Inc. Hot-carrier-based nonvolatile memory utilizing differing transistor structures
EP2109890A4 (en) * 2007-01-24 2010-02-10 Keystone Semiconductor Inc MOSFET CIRCUIT WITH RESIN LAYER AND APPLICATIONS
US7483290B2 (en) 2007-02-02 2009-01-27 Nscore Inc. Nonvolatile memory utilizing hot-carrier effect with data reversal function
US7813158B2 (en) 2007-05-14 2010-10-12 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Recordable electrical memory
JP5214328B2 (ja) * 2007-05-31 2013-06-19 株式会社東芝 半導体集積回路
EP2020658B1 (en) * 2007-06-29 2014-06-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and semiconductor device
US7518917B2 (en) * 2007-07-11 2009-04-14 Nscore Inc. Nonvolatile memory utilizing MIS memory transistors capable of multiple store operations
US7542341B2 (en) * 2007-08-20 2009-06-02 Nscore, Inc. MIS-transistor-based nonvolatile memory device with verify function
US7463519B1 (en) 2007-08-22 2008-12-09 Nscore Inc. MIS-transistor-based nonvolatile memory device for authentication
US7460400B1 (en) 2007-08-22 2008-12-02 Nscore Inc. Nonvolatile memory utilizing MIS memory transistors with bit mask function
US7511999B1 (en) 2007-11-06 2009-03-31 Nscore Inc. MIS-transistor-based nonvolatile memory with reliable data retention capability
US7630247B2 (en) * 2008-02-25 2009-12-08 Nscore Inc. MIS-transistor-based nonvolatile memory
US7639546B2 (en) * 2008-02-26 2009-12-29 Nscore Inc. Nonvolatile memory utilizing MIS memory transistors with function to correct data reversal
US7733714B2 (en) 2008-06-16 2010-06-08 Nscore Inc. MIS-transistor-based nonvolatile memory for multilevel data storage
US7821806B2 (en) * 2008-06-18 2010-10-26 Nscore Inc. Nonvolatile semiconductor memory circuit utilizing a MIS transistor as a memory cell
JP4908471B2 (ja) * 2008-08-25 2012-04-04 株式会社東芝 半導体記憶装置、及びそれを用いたトリミング方法
JP4908472B2 (ja) 2008-08-26 2012-04-04 株式会社東芝 半導体集積記憶回路及びラッチ回路のトリミング方法
US20100177556A1 (en) * 2009-01-09 2010-07-15 Vanguard International Semiconductor Corporation Asymmetric static random access memory
US7791927B1 (en) * 2009-02-18 2010-09-07 Nscore Inc. Mis-transistor-based nonvolatile memory circuit with stable and enhanced performance
US8213247B2 (en) * 2009-11-16 2012-07-03 Nscore Inc. Memory device with test mechanism
WO2011148898A1 (ja) * 2010-05-24 2011-12-01 国立大学法人東京大学 半導体記憶素子の電圧特性調整方法、半導体記憶装置の電圧特性調整方法およびチャージポンプ並びにチャージポンプの電圧調整方法
US8259505B2 (en) 2010-05-28 2012-09-04 Nscore Inc. Nonvolatile memory device with reduced current consumption
US8451657B2 (en) 2011-02-14 2013-05-28 Nscore, Inc. Nonvolatile semiconductor memory device using MIS transistor
US9059032B2 (en) * 2011-04-29 2015-06-16 Texas Instruments Incorporated SRAM cell parameter optimization
US20140119146A1 (en) * 2012-10-30 2014-05-01 Apple Inc. Clock Gated Storage Array
US9018975B2 (en) 2013-02-15 2015-04-28 Intel Corporation Methods and systems to stress-program an integrated circuit
US9391617B2 (en) 2013-03-15 2016-07-12 Intel Corporation Hardware-embedded key based on random variations of a stress-hardened inegrated circuit
US9159404B2 (en) 2014-02-26 2015-10-13 Nscore, Inc. Nonvolatile memory device
US9515835B2 (en) 2015-03-24 2016-12-06 Intel Corporation Stable probing-resilient physically unclonable function (PUF) circuit
US9484072B1 (en) 2015-10-06 2016-11-01 Nscore, Inc. MIS transistors configured to be placed in programmed state and erased state
US9966141B2 (en) 2016-02-19 2018-05-08 Nscore, Inc. Nonvolatile memory cell employing hot carrier effect for data storage
KR102626791B1 (ko) * 2017-08-28 2024-01-19 에이에스엠엘 네델란즈 비.브이. 미리 결정된 시동 값을 갖는 메모리 디바이스
US10777265B2 (en) 2017-11-13 2020-09-15 International Business Machines Corporation Enhanced FDSOI physically unclonable function
CN111431511A (zh) * 2019-05-21 2020-07-17 合肥晶合集成电路有限公司 锁存电路
US11417407B1 (en) 2021-04-01 2022-08-16 Globalfoundries U.S. Inc. Structures and methods of identifying unprogrammed bits for one-time-programmable-memory (OTPM)
US11961567B2 (en) * 2021-09-21 2024-04-16 PUFsecurity Corporation Key storage device and key generation method
US20230214270A1 (en) * 2021-12-31 2023-07-06 Western Digital Technologies, Inc. Readiness states for partitioned internal resources of a memory controller

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2000407B (en) * 1977-06-27 1982-01-27 Hughes Aircraft Co Volatile/non-volatile logic latch circuit
US4821233A (en) * 1985-09-19 1989-04-11 Xilinx, Incorporated 5-transistor memory cell with known state on power-up
US5325325A (en) * 1990-03-30 1994-06-28 Sharp Kabushiki Kaisha Semiconductor memory device capable of initializing storage data
US5285069A (en) * 1990-11-21 1994-02-08 Ricoh Company, Ltd. Array of field effect transistors of different threshold voltages in same semiconductor integrated circuit
JPH04289593A (ja) 1991-03-19 1992-10-14 Fujitsu Ltd 不揮発性半導体記憶装置
JPH0660667A (ja) * 1992-08-11 1994-03-04 Toshiba Corp 半導体記憶装置
JPH0676582A (ja) * 1992-08-27 1994-03-18 Hitachi Ltd 半導体装置
JPH06168591A (ja) * 1992-11-27 1994-06-14 Mitsubishi Electric Corp 半導体記憶装置
US5477176A (en) * 1994-06-02 1995-12-19 Motorola Inc. Power-on reset circuit for preventing multiple word line selections during power-up of an integrated circuit memory
US5703392A (en) * 1995-06-02 1997-12-30 Utron Technology Inc Minimum size integrated circuit static memory cell
US5650350A (en) * 1995-08-11 1997-07-22 Micron Technology, Inc. Semiconductor processing method of forming a static random access memory cell and static random access memory cell
JP3219236B2 (ja) * 1996-02-22 2001-10-15 シャープ株式会社 半導体記憶装置
US6341093B1 (en) * 2000-06-07 2002-01-22 International Business Machines Corporation SOI array sense and write margin qualification

Also Published As

Publication number Publication date
US6906962B2 (en) 2005-06-14
GB0319127D0 (en) 2003-09-17
GB2394338A (en) 2004-04-21
GB2394338B (en) 2007-04-25
TW200414224A (en) 2004-08-01
KR20040029260A (ko) 2004-04-06
US20040062083A1 (en) 2004-04-01
KR101026335B1 (ko) 2011-04-04
JP2004127499A (ja) 2004-04-22

Similar Documents

Publication Publication Date Title
TWI291179B (en) Method for defining the initial state of static random access memory
CN109493908B (zh) 非易失性存储器胞的编程方法
US9324381B2 (en) Antifuse OTP memory cell with performance improvement, and manufacturing method and operating method of memory
CN102150238B (zh) 在形成半导体构造期间利用微波辐射的方法
US20100080035A1 (en) Sram based one-time-programmable memory
US9362291B1 (en) Integrated circuit devices and methods
CN112635468B (zh) 一种反熔丝一次性可编程存储单元
CN112234061B (zh) 一种反熔丝一次性可编程存储单元
TW200814241A (en) Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits
US8050077B2 (en) Semiconductor device with transistor-based fuses and related programming method
US5239510A (en) Multiple voltage supplies for field programmable gate arrays and the like
KR100552841B1 (ko) 비휘발성 sram
TW202025451A (zh) 使用在非揮發性快閃記憶體裝置中之改良式電荷泵
US6525962B1 (en) High current and/or high speed electrically erasable memory cell for programmable logic devices
US8208312B1 (en) Non-volatile memory element integratable with standard CMOS circuitry
US9659944B2 (en) One time programmable memory with a twin gate structure
CN112234063B (zh) 一种反熔丝一次性可编程存储单元
US7521764B2 (en) One-time programmable memory device
US7697319B2 (en) Non-volatile memory device including bistable circuit with pre-load and set phases and related system and method
CN112234062B (zh) 一种反熔丝一次性可编程存储单元
US6459615B1 (en) Non-volatile memory cell array with shared erase device
CN101393932A (zh) 非易失性半导体存储装置
US10008267B2 (en) Method for operating flash memory
JP4071920B2 (ja) メモリセルを有する集積回路、およびその動作方法
CN212907739U (zh) 保险丝结构及存储单元

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees