TWI286326B - Semiconductor memory device with simplified data control signals - Google Patents

Semiconductor memory device with simplified data control signals Download PDF

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Publication number
TWI286326B
TWI286326B TW094100351A TW94100351A TWI286326B TW I286326 B TWI286326 B TW I286326B TW 094100351 A TW094100351 A TW 094100351A TW 94100351 A TW94100351 A TW 94100351A TW I286326 B TWI286326 B TW I286326B
Authority
TW
Taiwan
Prior art keywords
data
data input
dinstb
semiconductor memory
signal
Prior art date
Application number
TW094100351A
Other languages
English (en)
Chinese (zh)
Other versions
TW200614264A (en
Inventor
Chang-Hyuk Lee
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200614264A publication Critical patent/TW200614264A/zh
Application granted granted Critical
Publication of TWI286326B publication Critical patent/TWI286326B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
TW094100351A 2004-10-29 2005-01-06 Semiconductor memory device with simplified data control signals TWI286326B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040087326A KR100562645B1 (ko) 2004-10-29 2004-10-29 반도체 기억 소자

Publications (2)

Publication Number Publication Date
TW200614264A TW200614264A (en) 2006-05-01
TWI286326B true TWI286326B (en) 2007-09-01

Family

ID=36261629

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094100351A TWI286326B (en) 2004-10-29 2005-01-06 Semiconductor memory device with simplified data control signals

Country Status (5)

Country Link
US (1) US7317629B2 (ko)
JP (1) JP2006127726A (ko)
KR (1) KR100562645B1 (ko)
CN (1) CN100470672C (ko)
TW (1) TWI286326B (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100842743B1 (ko) * 2006-10-27 2008-07-01 주식회사 하이닉스반도체 고집적 반도체 장치
KR100837825B1 (ko) * 2007-05-14 2008-06-13 주식회사 하이닉스반도체 반도체 메모리 장치의 데이터 입력 회로 및 방법

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US5380574A (en) * 1991-12-18 1995-01-10 Mitsubishi Yuka Badische Co., Ltd. Mats and rugs and process for producing the same
DE4343970A1 (de) * 1993-12-22 1995-06-29 Stankiewicz Gmbh Modularer schalldämmender Belag
IT1283346B1 (it) * 1996-07-29 1998-04-17 Plantex S P A Apparecchiatura e metodo per la produzione di un tessuto antiscivolo,e relativo prodotto
KR100253564B1 (ko) * 1997-04-25 2000-05-01 김영환 고속 동작용 싱크로노스 디램
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KR100308119B1 (ko) * 1998-11-24 2001-10-20 김영환 카스(CAS)레이턴시(Latency)제어회로
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JP4008624B2 (ja) * 1999-06-15 2007-11-14 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
JP2001166989A (ja) 1999-12-07 2001-06-22 Hitachi Ltd プリフェッチ機構を有するメモリシステム及びその動作方法
JP3415586B2 (ja) 1999-12-16 2003-06-09 エヌイーシーマイクロシステム株式会社 同期型ｄｒａｍ
US6519188B2 (en) * 2000-12-18 2003-02-11 Hynix Semiconductor Inc. Circuit and method for controlling buffers in semiconductor memory device
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US6930932B2 (en) * 2003-08-27 2005-08-16 Hewlett-Packard Development Company, L.P. Data signal reception latch control using clock aligned relative to strobe signal

Also Published As

Publication number Publication date
US20060092714A1 (en) 2006-05-04
US7317629B2 (en) 2008-01-08
CN100470672C (zh) 2009-03-18
CN1767058A (zh) 2006-05-03
KR100562645B1 (ko) 2006-03-20
JP2006127726A (ja) 2006-05-18
TW200614264A (en) 2006-05-01

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