JP2007012270A - ダイナミック・ランダム・アクセス・メモリ・システム - Google Patents
ダイナミック・ランダム・アクセス・メモリ・システム Download PDFInfo
- Publication number
- JP2007012270A JP2007012270A JP2006243196A JP2006243196A JP2007012270A JP 2007012270 A JP2007012270 A JP 2007012270A JP 2006243196 A JP2006243196 A JP 2006243196A JP 2006243196 A JP2006243196 A JP 2006243196A JP 2007012270 A JP2007012270 A JP 2007012270A
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- Prior art keywords
- dram
- row
- write
- read
- data
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
Abstract
【解決手段】インタフェースにおける信号線の高パフォーマンスを活かすために、信号線の数を最小限にし、DRAMとインタフェースする信号線の帯域幅を最大限にすることが望ましい。本発明のDRAMメモリ・システムでは、アドレス線と制御線を統合し、情報を多重化して、DRAMピンの情報率が常にほぼ等しくなるようにする。
【選択図】なし
Description
上式において、
・ capはクロック・サイクルごとの受信アドレス・ビット数、
・ 上限は引き数以上の整数値を返す関数、
・ caは各読み書きサイクルで使用される列アドレス・ビット数、
・ fはrw/trの比を表す。
上式において、
・ cap=クロック・サイクルtClockCycleごとの受信アドレス・ビット数、
・ 上限=引き数以上の整数値を返す関数、
・ ca=読み書きサイクルtRead/Writeごとに使用される列アドレス・ビット数、
・ f=rw/tr、ここでrw=各読取り/書込みサイクルtraed/Write中に列増幅器との間で読み書きされるビット数、tr=各クロック・サイクルtClockCycle中にDRAMとの間で送受信されるビット数、
・ tRead/Write=f・tClockCycleである。
・ rw=8×9ビット
・ tr=9ビット
・ f=8
・ ra=10ビット(プラス15ビットの装置アドレス)
・ ca=8ビット
・ cap=1ビット
BusData[8:0]をデータ、制御、および行アドレス情報に使用する。ピンBusEnableは、多重クロック・サイクルの列アドレスを伝送するために使用し、BusCtrlピンをデータ線上のデータまたはアドレスを指定するために使用する。f=8であるため、BusCtrl線をどの信号の伝送にも使用していないときにいくらかのクロック・サイクルがあるので、BusCtrl線をデータまたはアドレスの指定以外の機能に使用することができる。したがって、ブロック・データの伝送を早期終了する時点を示すなどの機能を実現することができる。
Claims (1)
- メモリ・アレイを有するダイナミック・ランダム・アクセス・メモリ装置であって、
上記メモリ・アレイ中の行アドレスおよび列アドレスで指定される位置に書込むべきデータを指定する書込みコマンドを受信するインターフェースを備え、
書込みコマンドに応じてメモリ・アレイにデータを、書込みアクセス中に書込む複数の列増幅器を備え、クロック信号の単一クロック・サイクルにおいて列増幅器で書込めるデータのビット数は、受信されるデータのビット数の少なくとも2倍であり、
クロック信号の単一のクロック・サイクル中に行アドレスを受信し、他の単一のクロック・サイクル中に列アドレスを受信する複数のピンを備え、
列アドレスの受信から書込みアクセスの開始までに経過する、クロック信号のクロック・サイクル数を表す値を記憶する第1のレジスタを備え、
上記インターフェースおよび上記第1のレジスタに接続され、上記第1のレジスタ内の値に応じて書込みアクセスの開始を遅延させる遅延回路を備える、ことを特徴とするダイナミック・ランダム・アクセス・メモリ装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US7117793A | 1993-06-23 | 1993-06-23 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50087995A Division JP4077874B2 (ja) | 1993-06-02 | 1994-05-23 | ダイナミック・ランダム・アクセス・メモリ・システム |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010019553A Division JP2010135065A (ja) | 1993-06-02 | 2010-01-29 | ダイナミック・ランダム・アクセス・メモリ・システム |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007012270A true JP2007012270A (ja) | 2007-01-18 |
JP4615494B2 JP4615494B2 (ja) | 2011-01-19 |
Family
ID=22099750
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50087995A Expired - Fee Related JP4077874B2 (ja) | 1993-06-02 | 1994-05-23 | ダイナミック・ランダム・アクセス・メモリ・システム |
JP2006243196A Expired - Lifetime JP4615494B2 (ja) | 1993-06-02 | 2006-09-07 | ダイナミック・ランダム・アクセス・メモリ・システム |
JP2010019553A Pending JP2010135065A (ja) | 1993-06-02 | 2010-01-29 | ダイナミック・ランダム・アクセス・メモリ・システム |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50087995A Expired - Fee Related JP4077874B2 (ja) | 1993-06-02 | 1994-05-23 | ダイナミック・ランダム・アクセス・メモリ・システム |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010019553A Pending JP2010135065A (ja) | 1993-06-02 | 2010-01-29 | ダイナミック・ランダム・アクセス・メモリ・システム |
Country Status (4)
Country | Link |
---|---|
US (3) | US5430676A (ja) |
JP (3) | JP4077874B2 (ja) |
AU (1) | AU7043494A (ja) |
WO (1) | WO1994028550A1 (ja) |
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- 1994-05-23 WO PCT/US1994/005798 patent/WO1994028550A1/en active Application Filing
- 1994-05-23 JP JP50087995A patent/JP4077874B2/ja not_active Expired - Fee Related
- 1994-05-23 AU AU70434/94A patent/AU7043494A/en not_active Abandoned
- 1994-11-03 US US08/333,869 patent/US5434817A/en not_active Expired - Fee Related
-
2006
- 2006-09-07 JP JP2006243196A patent/JP4615494B2/ja not_active Expired - Lifetime
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2010
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JPH052873A (ja) * | 1990-10-15 | 1993-01-08 | Toshiba Corp | 半導体記憶装置 |
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Also Published As
Publication number | Publication date |
---|---|
JP4077874B2 (ja) | 2008-04-23 |
JP4615494B2 (ja) | 2011-01-19 |
JPH09500751A (ja) | 1997-01-21 |
US5434817A (en) | 1995-07-18 |
AU7043494A (en) | 1994-12-20 |
JP2010135065A (ja) | 2010-06-17 |
WO1994028550A1 (en) | 1994-12-08 |
US5511024A (en) | 1996-04-23 |
US5430676A (en) | 1995-07-04 |
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