TWI261885B - Method and apparatus for a dual substrate package - Google Patents

Method and apparatus for a dual substrate package Download PDF

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Publication number
TWI261885B
TWI261885B TW093129469A TW93129469A TWI261885B TW I261885 B TWI261885 B TW I261885B TW 093129469 A TW093129469 A TW 093129469A TW 93129469 A TW93129469 A TW 93129469A TW I261885 B TWI261885 B TW I261885B
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Taiwan
Prior art keywords
substrate
package
die
interconnects
semiconductor
Prior art date
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TW093129469A
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English (en)
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TW200525664A (en
Inventor
Christopher Rumer
Kuljeet Singh
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Intel Corp
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Publication of TW200525664A publication Critical patent/TW200525664A/zh
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Publication of TWI261885B publication Critical patent/TWI261885B/zh

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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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Description

1261885 (1) 九、發明說明 【發明所屬之技術領域】 本發明關於半導體封裝，尤其關於路由至半導體晶粒 之電源及信號。 【先前技術】 積體電路（I C s )，尤其是微處理器，變得越來越複 雜。在變得複雜的同時，微處理器更需越來越多的電源。 微處理器也需要額外的信號輸入以促進增加的處理效能。 半導體封裝可使用封裝基板來從電源供應器傳遞電源並從 封裝外部傳遞信號到半導體晶粒。封裝基板連接半導體晶 粒以增加往來半導體晶粒之信號的分佈區域。將封裝基板 連接至半導體晶粒之兩個現行方法包含銲線模塑矩陣陣列 封裝（W B - Μ M A P )及覆晶模塑矩陣陣列封裝（F C _ Μ M A P )° 圖1 A說明使用銲線模塑矩陣陣列封裝（w B - Μ M A P )來耦接至封裝基板之半導體晶粒。封裝1 0包含半導體 晶粒1 2，如微處理器、晶片組、記憶體裝置、特殊應用 積體電路（ASIC)等’其置於封裝基板14上。半導體晶 粒1 2使用一些銲線1 6與封裝基板1 4收發信號。銲線工6 一般爲銅或銘，並允許封裝基板〗4上的焊盤及半導體晶 粒1 2的裝置面間之電t通訊。封裝]〇經由互連裝置1 $ 連接外部元件，該互連裝置]8可爲如銲錫球和金屬塡充 聚合物的球狀栅格陣列（B G A )互連、如針腳的針腳柵格 (2) 1261885 陣列（P G A )互連、如基板的基板栅格陣列（l G A )互連 等。晶粒1 2及銲線1 6被封在如環氧樹脂的模製材料2 〇 內，以預防損害。 圖】Β說明覆晶模塑矩陣陣列封裝（F C - Μ M A Ρ )。封 裝基板30包含半導體晶粒32及封裝基板34。半導體晶 粒3 2經由銲錫凸塊3 6連接封裝基板2 4，可控制崩潰晶 片連接（C 4 )或其他傳導凸塊。在半導體晶粒3 2置於封 裝基板3 4上之前，銲錫凸塊3 6形成於半導體晶粒3 2作 用或裝置面之焊盤上。C 4凸塊3 6具傳導性，使得半導體 晶粒32之裝置面可與封裝基板34通訊。往來半導體晶粒 3 2之信號經由封裝基板3 4來路由，而在封裝之外使用互 連38。互連裝置38可以是銲錫球或金屬塡充聚合物，如 BGA互連、PGA互連等。晶粒32被封在模製材料40中 ，如環氧樹脂，以預防損壞。 圖1 C說明一般封裝基板。封裝基板5 0提供一個大區 域來從晶粒分配信號，同樣地對於晶粒提供物理防護。封 裝基板50包含幾個穿孔52及平面54。穿孔52幫助垂直 信號在基板5 0內行進，平面5 4允許基板5 0內之水平行 進。穿孔5 2可與銲線1 6或銲錫凸塊3 6連接。穿孔5 2之 底部可與互連1 8或3 8連接。圖I ϋ說明封裝基板之底視 圖。如圖1 D所示，穿孔5 2之底部遍佈封裝基板5 0之表 面。一般封裝基板50可包含數千個穿孔52。封裝基板50 之俯視會相似，除了焊盤會符合連接方法（銲線或覆晶） 及晶粒尺寸。 (3) (3)1261885 要求更多電源和更多信號互連之較新積體電路可能已 用盡如上述封裝基板1 4、3 4、5 0之單一封裝基板的容量 。結果’當爲了分配電源和信號而使用單一封裝基板時， 單一封裝基板會限制處理器速度。而且，由相對少量之信 號封裝基板導體表面所導致之電阻增加亦可造成較高之操 作溫度。 【發明內容及實施方式】 在此描述雙基板封裝設計之方法及裝置。在接下來的 描述中’將提到數個特定細節。然而，實施例可以不需要 這些特定細節來實施。例如，在此所提及之材料皆可用已 知之同等材料來替代，同樣地，在此所揭露之特定半導體 處理技術亦可用已知之同等技術來替代。在其他例子中， 爲了不模糊此說明，已知之結構和技術將不被詳細地描述 〇 依據本發明之實施例，揭露一雙基板封裝設計。第一 封裝基板銜接到半導體晶粒之背面，第二封裝基板銜接到 半導體晶粒之正面。在半導體晶粒背面鑽上通孔以形成晶 粒之作用正面及第一封裝基板間的連接。第二封裝基板銜 接到與晶粒正面的作用元件耦接之焊盤。第一及第二封裝 基板與基板球彼此耦接。 圖2A說明依據一實施例之雙基板半導體封裝。半導 體封裝]〇〇包含具有作用面104之半導體晶粒102。半導 體晶粒1 02可由單一液晶矽或其他半導體基板形成。作用 -6- (4) 1261885 面104含有執行1C操作之半導體裝置。作用（或裝置） 面1 04使用多種已知半導體處理技術來形成。作用面1 04 一般小於1 0微米（μπι )深。作用面1 04可包含任何電路 ，如使用於中央處理單元（CPUs )之電晶體、電容等， 晶片組、記憶體裝置、特殊應用積體電路（ASICs )等。 作用面104亦可包含金屬化，如與形成於表面上以產生外 部連接之晶片焊盤耦接之互連。 在半導體晶粒102之背面106上有幾個通孔108。通 孔1 0 8允許晶粒1 02之背面與晶粒1 04之作用裝置面電連 接。首先可藉由薄化晶粒1 02來形成通孔1 08。半導體晶 粒102 —般要求厚度介於700及8 00 μιη間以促進產生作 用面1 04之處理步驟。爲了產生晶粒；[04作用面與晶粒背 面之連接，晶粒之厚度必須使用硏磨、旋轉蝕刻、化學機 械硏磨法（CMP)等處理來薄化到近乎75-175μηι。一旦 晶粒1 02被薄化’通孔；[08可藉由任何已知技術來形成包 含深層反應離子鈾刻（RIE )再接著用電鍍技術以如銅之 導體塡滿鑽孔。 互連裝置1 10與通孔108耦接以產生與背面封裝基板 1 1 0之電連接。加入背面封裝基板丨丨2以增加可以傳遞電 源到晶粒〗02並傳輸信號往來晶粒丨〇2之導線數目。互連 裝置1 1 4亦形成於封裝基板〗〇 2之裝置面〗〇4上以允許半 導體晶粒1 02裝置面1 04及封裝基板1 1 6正面間之連接。 互連裝置11 〇及1 1 4可以爲如控制崩潰晶片連接（C4 )之 覆晶婷錫凸塊或其他互連。互連裝置η 〇及η 4可藉由模 (5) (5)1261885 板印刷、電鑛、凸塊、或其他已知技術來形成。 底膠層1 1 8及1 2 0提供互連1 1 〇及1 1 4之絕緣和防護 。底膠層118及120亦產生封裝基板112及116與半導體 晶粒1 02間之附著。基板球1 22允許背面封裝基板1 1 2與 正面封裝基板 Π 6間之通訊。基板球1 2 2圍住封裝基板 1 1 2及1 1 6，並允許兩者間之通訊。這顯示於圖2 B。圖 2B說明封裝100之俯視圖。所顯示的封裝100之背面基 板1 1 2被移除。如所示，基板球1 22圍住封裝基板1 1 6之 面緣並與封裝基板1 1 6之焊盤耦接。 圖3說明形成雙基板半導體封裝之處理。圖4A到 4M說明描述於圖3之處理。處理200從開始方塊202開 始。方塊204提供一半導體晶圓。圖4A說明具有作用裝 置面304及背面306之加工半導體晶圓302。裝置面304 含有包含電晶體、電阻等之半導體裝置以產生CPU、晶片 組、ASIC、記憶體等之電路。裝置面3 04使用已知技術 和處理來形成。背面3 06不含有任何作用元件，因此可在 不影響IC之功能下調整。爲了促進晶圓之處理，在一實 施例中，晶圓3 02之最初厚度介於700及8 00 μηι間。 在方塊2 06，薄化晶圓3 02以促進通孔。圖4Β說明 已薄化晶圓3 0 2。晶圓3 0 2之背面3 〇 6可使用如硏磨、旋 轉蝕刻、C Μ Ρ等處理來薄化。既然所有的微處理器或其 他IC之作用元件包含於裝置面3 〇 4內，晶圓3 0 2之背面 3 0 6可在不影響IC的功能下被薄化。在一實施例中，爲 了促進通孔，模製晶圓3 0 2以讓晶圓3 0 2裝置面3 0 4更接 -8- (6) (6)1261885 近晶圓3 Ο 2背面3 Ο 6。在一實施例中’薄化晶圓3 Ο 2厚度 到 7 5 - 1 7 5 μ m。 在方塊2 0 8，鑽孔並金屬化通孔。圖4 C說明內有通 孔3 0 8之晶圓3 0 2。通孔3 0 8提供背面3 0 6及作用或裝置 面3 04間之電連接。通孔3 0 8可使用反應離子蝕刻（RIE )或其他適當的處理來形成。藉由先光罩再鑽過晶圓3 02 之背面來在作用層304提供一通道到半導體裝置以形成通 孔308。通道可與作用面304之第一金屬層連接。在另一 實施例中，通道可與晶粒作用面之表面連接。一旦形成鑽 孔以促進通孔3 0 8，則金屬化通孔3 0 8以提供晶圓3 02背 面3 06及裝置面3 04間之電連接。通孔3 0 8可使用如電鍍 、無電鍍等之電鍍技術來金屬化。使用電鍍處理來在鑽孔 內沉澱如銅或鋁之導電材料，而形成通孔3 08。 在方塊2 1 0，以覆晶焊盤排列晶圓3 02之正面並凸起 晶圓。圖4D說明具有傳導凸塊之晶圓。覆晶焊盤形成於 晶圓302之作用面304上以促進與正面304之半導體裝置 電連接。一旦形成焊盤，銲錫或其他傳導凸塊3 1 0可排列 於焊盤上。凸塊3 1 0可導電並可連接焊盤及半導體裝置到 半導體晶圓3 0 2之外部。凸塊3 1 〇可使用模板印刷、電鍍 、凸塊、或其他已知處理來沉澱在覆晶焊盤上。凸塊3 ! 〇 可以是C4或其他覆晶凸塊。 在方塊2 1 2，晶圓3 0 2被切割。圖4 E說明切成幾個 半導體晶粒之晶圓。晶圓3 0 2可被切割或單一化成幾個半 導體晶粒3 1 2。半導體晶粒3 ] 2含有單一積體電路或微處 - 9- (7) 1261885 理器所需之半導體元件。晶圓3 0 2 —般含有幾打或 半導體晶粒3 1 2。爲了形成個別的1C，使用晶圓切 射等從更大晶圓3 02切割或單一化晶粒3 1 2。單一 ，形成幾個半導體晶粒3 1 2。 爲了分配往來半導體晶粒之信號和電源，一般 裝基板。如上所述，封裝基板包括幾個導線，並可 3 1 〇分配信號到半導體晶粒3 1 2之外部。封裝基板 電源和信號傳播到比起半導體晶粒3 1 2所涵蓋的區 。在方塊214，底膠材料被配送到正面基板上。圖 明底膠材料配送到封裝基板上。正面封裝基板3 1 4 來半導體晶粒3 1 2正面或作用面3 04之電源和信號 。分配如環氧樹脂之底膠材料3 1 6到封裝基板3 1 4 膠材料3 1 6可附著半導體晶粒3 1 2到封裝基板3 1 4 同樣地電子絕緣和提供凸塊3 1 0防護。底膠3 1 6亦 凸塊310受到晶粒312及凸塊310熱膨脹（CTE) 數之作用。在一實施例中，底膠材料3 1 6爲在銜接 3 1 2之前沉澱在基板3 1 4上之無流式底膠材料，在 施例中，毛細或其他底膠材料可在晶粒3 1 2銜接 3 1 4之後沉澱。然而，在一實施例中，最好使用無 膠材料，因爲可比起毛細底膠更容易配送。亦可使 型式之底膠。 在方塊2 1 6，正面基板3 1 4使用覆晶互連來銜 粒3 12正面3 04。圖4G說明半導體晶粒312並銜 裝基板3 1 4。底膠材料3 1 6將半導體晶粒3 1 2附著 更多之 割、雷 化之後 使用封 從凸塊 可以將 域更大 4F說 會將往 作分配 上。底 上，並 可防護 不同係 到晶粒 替代實 到基板 流式底 用其他 接到晶 接到封 到封裝 -10- (8) Ϊ261885 基板3 1 4。凸塊或互連3 1 0穿過底膠材料3〗6直到接觸封 裝基板3 1 4之焊盤。使用已知覆晶互連方法，互連3 1 〇可 使用熔爐或其他技術來加熱，以回銲銲錫或其他材料以產 生與封裝基板3 1 4上之焊盤的連接。在銲錫回銲之後，互 連3 1 〇將冷卻並形成半導體晶粒3 1 2晶片焊盤與封裝基板 3 1 4之連接以促進電源和信號之分配。 在方塊218’覆晶凸塊被印刷在晶粒312之背面上。 圖4Η說明背面3 06印有覆晶凸塊318之半導體晶粒312 。通孔3 0 8提供電連接到半導體晶粒3 1 2之裝置面3 04。 爲了連接半導體晶粒3 1 2外部之通孔，將如覆晶凸塊3 ；[ 8 之S連排列在晶粒3 1 2之背面上。覆晶凸塊3 1 8電耦接至 通孔3 0 8。覆晶凸塊318可藉此產生從晶粒312背面306 到裝置面3 04之電連接。 在方塊220，基板球被置於正面基板314上。圖41 顯示正面基板3 1 4有基板球3 2 0之半導體封裝。基板球 3 2 0可提供正面基板3 1 4與背面基板間之電連接，該背面 基板將稍後被加到封裝中。雖然厚度可依晶粒3 1 2尺寸等 而異，但基板球320可具有近乎225 μηι之厚度。基板球 3 2 0可連接到正面基板3丨4之焊盤，並圍住正面基板3 1 4 (見圖2 Β )。因此，信號和電源可從背面基板傳遞到正 面基板3 1 4。在一實施例中，只有正面基板3 1 4會被電耦 接至封裝3 0 0之外部。因此，假如背面基板不與封裝300 之外邰連接，可加入基板球3 2 0以傳遞信號於背面基板及 正面基板3 1 4間。在—實施例中，如圖41可見，基板球 -11 - (9) 1261885 ^ 2 〇貫質上大於凸塊3丨〇及3〗8。因此，即使可 3 2 〇較少’既然較大，但其可傳遞更多電流。在 例中’正面基板3 1 4及背面基板使用替代技術來 包含內插板型及引腳插入型附件。 在方塊222 ’配送底膠材料到晶粒之背面。 明上有底膠材料3 2 2配送之半導體晶粒3〗2。在 中’底膠材料3 22爲如環氧樹脂之無流式底膠材 材料3 22 ’如同底膠材料3〗6，可提供機械支援 護’並改良封裝可靠度。在一實施例中，無流式 3 2 2在加入背面基板之前，配送到晶粒3丨2上。 其他實施例中，一旦銜接背面基板，就有可能配 其他下溢材料。 在一替代實施例中，正面基板3 1 4在不使用 下銜接到晶粒3 1 2，而背面基板3 24在不使用底 銜接。在銜接正面和背面封裝基板3 1 4及3 2 4之 迫模製材料介於正面314及背面3 24基板之間以 驟塡充兩種基板。 在方塊2 2 4，背面基板被置於封裝3 0 0上， 凸塊3 1 8以形成背面互連。圖4 K說明有背面基: 接之半導體封裝3 00。背面基板3 24被置於封裝 之上。背面基板3 2 4分配往來半導體晶粒3 ] 2之 源。回銲覆晶凸塊3 1 8及銲錫球3 2 0以產生背面 之焊盤與各別凸塊3 1 8間之連接。在熔爐內回 3 2 0和覆晶凸塊3 ] 0及3 1 8以加熱金屬並使其結 能基板球 其他實施 電耦接， 圖4 J說 一實施例 料。底膠 、污染防 底膠材料 然而，在 送毛細或 底膠3 1 6 膠3 22下 後，可強 在同一步 回銲覆晶 扳3 24銜 組裝3 0 〇 信號和電 基板3 2 4 銲基板球 合到封裝 -12- (10) 1261885 基板3 1 4及3 2 4之焊盤上。藉由銜接背面基板3 2 4，形成 雙基板封裝。 在方塊2 2 6，對於簡化基板級互連，翻轉組裝且銜接 球狀柵格陣列（B G A )球。圖4 L說明有B G A球3 2 6銜接 之倒置半導體封裝，爲了允許晶粒3 0 0與封裝3 0 0外部之 裝置的通訊，電連接必須使用封裝基板3 1 4製成。B G A 球3 2 6可與正面基板3 1 4之底面銜接。B G A球可應用於 錫膏印刷機、球發射機等。如圖1D所示，BGA球3 26銜 接到形成於正面基板3 1 4底面之焊盤。在一實施例中，封 裝組裝3 00必須在銜接BGA球3 26之前翻轉。封裝元件 之組裝一般從封裝3 0 0之頂部發生。既然正面基板3 1 4在 封裝之底面，爲了銜接B G A球3 2 6，必須翻轉封裝基板 3 1 4。一旦封裝組裝3 0 0被翻轉，B G A球3 2 6可如上所述 被銜接。亦可使用如針腳柵格陣列（P G A )、平面柵格陣 列（LGA )等之其他已知互連技術。 處理2 0 0在結束方塊2 2 8結束。圖4 Μ說明完成之封 裝組裝3 00。爲了提供可用的1C或微處理器，一旦銜接 B G Α球3 2 6 ’則完成封裝組裝3 0 0且封裝處理可結束。 熟悉該項技藝之人會了解，在不偏離本發明的更大精 神下，可對在此所描述之實施例作幾個改變。例如，與其 正囬基板314，BGA互連326可置於背面基板324上。另 外，亦可使用不同技術、處理、材料。 本發明得由熟悉技藝之人任施匠思而爲諸般修飾，然 皆不脫如申請專利範圍所欲保護者。 -13- (11) 1261885 【圖式簡單說明】
0 1 Α δ兌明使用靜線模塑矩陣陣列封裝（w b _ μ M A P )來耦接至封裝基板之半導體晶粒。 圖1B說明覆晶模塑矩陣陣列封裝（fc_mmap )。 圖1 C說明一般封裝基板。 圖I D說明封裝基板之底視圖。
圖2A說明依據一實施例之雙基板半導體封裝。 圖2B說明封裝之俯視圖。 圖3說明形成雙基板半導體封裝之處理。 圖4 A說明具有作用裝置面之加工半導體晶圓。 圖4B說明已薄化晶圓。 圖4C說明內有通孔之晶圓。 圖4D說明具有傳導凸塊之晶圓。 圖4E說明切成幾個半導體晶粒之晶圓。
圖4F說明底膠材料配送到封裝基板上。 圖4G說明半導體晶粒並銜接到封裝基板。 圖4H說明背面印有覆晶凸塊之半導體晶粒。 圖41顯示正面基板有銲錫球之半導體封裝。 圖4J說明上有底膠材料配送之半導體晶粒。 圖4K說明有背面基板銜接之半導體封裝。 圖4L說明有BGA球銜接之倒置半導體封裝。 圖4M說明完成之封裝組裝。 -14- (12)1261885 【主要元件符號說明】 10 封裝 12 半導體晶粒 14 封裝基板 16 銲線 18 互連裝置 20 模製材料 30 封裝基板 32 半導體晶粒 34 封裝基板 36 銲錫凸塊 3 8 互連 40 模製材料 50 封裝基板 52 穿孔 54 平面 1 00 半導體封裝 1 02 半導體晶粒 104 作用面 1 06 背面 1 08 通孔 1 1 0 互連裝置 112 背面封裝基板 1 1 4 互連裝置 -15- 1261885 (13) 116 正 面 封 裝 基 板 118 底 膠 層 1 20 底 膠 層 1 22 基 板 球 3 00 封 裝 3 02 半 導 體 晶 圓 3 04 裝 置 面 306 背 面 308 通 孔 3 10 傳 導 凸 塊 3 12 半 導 體 晶 粒 3 14 正 面 封 裝 基 板 3 16 底 膠 材 料 3 18 覆 晶 凸 塊 320 基 板 球 322 底 膠 材 料 324 背 面 基 板 326 BGA 球
-16-

Claims (1)

  1. 1261885 (1) 十、申請專利範圍 附件2A : 第093 1 29469號專利申請案 中文申請專利範圍替換本 民國95年5月26日修正 1 · 一種雙基板封裝之裝置，包括： 一半導體晶粒，包括形成在正面上之主動電路，且具 有從正面至背面形成之許多導電通孔，該晶粒包括一 ·電力 需求及一外部信號需求； 許多第一互連，形成於該晶粒之正面上，及許多第二 互連，形成在該晶粒之背面上，該許多第二互連各別地耦 接至該許多通孔；及 一第一封裝基板，電耦接至該許多第一互連，及一第 二封裝基，電耦接至該許多第二互連， 其中該電力需求及該外部信號需求的至少其中之一的 一部份被供給經過該第一封裝基板，且該電力需求及該外 部信號需求的至少其中之一的餘留部份被供給經過該第二 封裝基板。 2 .如申請專利範圍第1項之裝置，進一步包括介於晶 粒正面與第一基板間之第一底膠層和介於晶粒背面與第二 基板間之第二底膠層。 3 ·如申請專利範圍第1項之裝置，進一步包括電耦接 於第一與第二基板間之基板球。 4.如申請專利範圍第1項之裝置，其中許多第一互連 及許多第二互連包括銲錫球。 (2) 1261885 5。如申請專利範圍第1項之裝置，其中半導體晶粒使 用選自由背面磨削處理、化學機械硏磨（C Μ P)處理、旋轉 蝕刻處理所組成的群組之一來薄化。 6 ·如申請專利範圍第2項之裝置，其中底膠層包括無 流式底膠材料。 I 一種雙基板封裝之方法，包括： 在半導體晶粒之背面形成許多導電通孔，該半導體晶 粒包括在正面上之主動電路，且將許多第一互連耦接至各 別的許多通孔； 將許多第二互連耦接至該晶粒的正面； 將許多第一互連電耦接至第一基板；及 將許多第二互連電耦接至第二基板， 其中晶粒的電力需求及晶粒的外部信號需求的至少其 中之一的一部份被供給經過該第一封裝基板，且該電力需 求及該外部信號需求的至少其中之一的餘留部份被供給經 過該第二封裝基板。 8 ·如申請專利範圍第7項之方法，其中許多通孔與裝 置面連接。 9 .如申請專利範圍第7項之方法，進一步包括： 將第一底膠層配送到第一封裝基板上；及 將第二底膠層配送到半導體晶粒之背面上。 1 〇.如申請專利範圍第9項之方法，進一步包括 將一基板球銜接到第一及第二封裝基板之間。 1 1 .如申請專利範圍第7項之方法，其中許多第一互 -2- 1261885 (3) 連及許多第二互連包括銲錫球。 1 2 .如申請專利範圍第7項之方法，進一步包括將 導體晶粒薄化。 1 3 .如申請專利範圍第7項之方法，其中第一及第 底膠層包括無流式底膠。
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US20050067714A1 (en) 2005-03-31
HK1093381A1 (en) 2007-03-02
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KR20060069502A (ko) 2006-06-21
TW200525664A (en) 2005-08-01
DE112004001678T5 (de) 2006-07-13
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CN100459111C (zh) 2009-02-04
WO2005034203A3 (en) 2005-10-27

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