TW202243110A - 半導體裝置及形成其的方法 - Google Patents
半導體裝置及形成其的方法 Download PDFInfo
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- TW202243110A TW202243110A TW110125059A TW110125059A TW202243110A TW 202243110 A TW202243110 A TW 202243110A TW 110125059 A TW110125059 A TW 110125059A TW 110125059 A TW110125059 A TW 110125059A TW 202243110 A TW202243110 A TW 202243110A
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Abstract
一種半導體裝置包括:第一多個晶粒,由包封體包封;中介層,位於所述第一多個晶粒之上;內連線結構,位於所述中介層之上且電連接到所述中介層;以及多個導電焊盤,位於所述內連線結構的與所述中介層相對的表面上。所述中介層包括多個嵌置式被動組件。所述第一多個晶粒中的每一晶粒電連接到所述中介層。所述內連線結構包括位於所述內連線結構的金屬化層中的螺線管電感器。
Description
本發明的實施例是有關於一種半導體裝置及形成其的方法。
隨著半導體技術持續演化,積體電路(integrated circuit,IC)晶粒變得越來越小。此外,更多的功能被集成到晶粒中。因此,晶粒所需要的輸入/輸出(input/output,I/O)焊盤的數目已增加,同時I/O焊盤可用的面積已減小。I/O焊盤的密度隨著時間迅速上升,從而增加了進行晶粒封裝的難度。
在一些封裝技術中,積體電路晶粒在其被封裝之前從晶圓單體化。此種封裝技術的有利特徵是可形成扇出型封裝(fan-out package),所述扇出型封裝使得晶粒上的I/O焊盤能夠被重佈線到更大的面積。因此晶粒的表面上的I/O焊盤的數目可增加。
本發明實施例提供一種半導體裝置,包括第一多個晶粒、中介層、內連線結構以及多個導電焊盤。第一多個晶粒由包封體包封。中介層位於第一多個晶粒之上。中介層包括多個嵌置式被動組件。第一多個晶粒中的每一晶粒電連接到中介層。內連線結構位於中介層之上且電連接到中介層。內連線結構包括位於內連線結構的金屬化層中的螺線管電感器。多個導電焊盤位於內連線結構的與中介層相對的表面上。
本發明實施例提供一種半導體裝置,包括第一模製化合物、中介層、導通孔、第三晶粒、第二模製化合物、內連線結構以及多個接觸焊盤。第一模製化合物圍繞第一晶粒及第二晶粒。中介層位於第一晶粒、第二晶粒及第一模製化合物之上。中介層包括靜態隨機存取記憶體(SRAM)電路系統。第一晶粒及第二晶粒各自電耦合到中介層。導通孔位於中介層上。第三晶粒接合到且電耦合到中介層。第二模製化合物圍繞導通孔及第三晶粒。內連線結構位於導通孔、第三晶粒及第二模製化合物之上。內連線結構包括螺線管電感器。多個接觸焊盤,與導通孔、第三晶粒及第二模製化合物相對地位於內連線結構上。
本發明實施例提供一種形成半導體裝置的方法,所述方法包括以下步驟。將第一多個晶粒接合到中介層,中介層包括多個導電特徵,第一多個晶粒中的每一晶粒接合到多個導電特徵中相應的導電特徵。利用包封體包封第一多個晶粒。在中介層的第一表面之上第一內連線,第一表面與第一多個晶粒相對。形成第一內連線包括,形成第一內連線的底部部分;在第一內連線的底部部分上放置磁芯;以及在第一內連線的底部部分以及磁芯之上形成第一內連線的頂部部分,其中形成頂部部分會形成包括磁芯的螺線管電感器。在第一內連線上與中介層相對地形成第一多個接觸焊盤。以及,將第一裝置貼合到第一內連線。第一裝置電耦合到第一多個接觸焊盤中的接觸焊盤。
以下公開內容提供用於實施本發明的不同特徵的許多不同實施例或實例。以下闡述組件及佈置的具體實例以簡化本公開內容。當然,這些僅為實例且並非旨在進行限制。舉例來說,以下說明中將第一特徵形成在第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且也可包括其中第一特徵與第二特徵之間可形成有附加特徵從而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外,本公開內容可能在各種實例中重複使用參考編號和/或字母。此種重複使用是出於簡潔及清晰的目的,而不是自身表示所論述的各種實施例和/或配置之間的關係。
此外,為易於說明,本文中可能使用例如「位於...下方(beneath)」、「位於...下面(below)」、「下部的(lower)」、「位於...上方(above)」、「上部的(upper)」及類似用語等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。裝置可具有其他取向(旋轉90度或處於其他取向),且本文中所使用的空間相對性闡述語可同樣相應地進行解釋。
根據一些實施例,超大型微系統(super large micro-system)是包括來自晶圓上晶片(chip-on-wafer,CoW)、前對前和/或前對後積體晶片上系統(system-on-integrated chip,SoIC)及矽製基底上晶圓上晶片(chip-on-wafer-on-substrate,CoWoS)的技術的晶圓上系統(SoW)組件(assembly)。SoW組件可具有小的形狀因數(form factor)且由於其緊湊的結構而表現出優越的電性能。晶圓級中介層可包括積體被動裝置(integrated passive device,IPD)(例如,電容器)或靜態隨機存取記憶體(SRAM)電路系統。SoW可使得能夠實現具有從系統單晶片(system-on-chip,SoC)晶粒到SRAM電路系統的短內連線的異構集成(heterogeneous integration),使得能夠實現可減少小組件翹曲的對稱模製結構,且使得能夠將電壓調節器模組(voltage regulator module,VRM)小型化為重佈線結構中的嵌置式螺線管電感器。直接將用於電源管理的脈波寬度調變(Pulse Width Modulation,PWM)電路與金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor,MOSFET)加以組合的積體扇出型(integrated fan-out,InFO)封裝可通過重佈線結構貼合到VRM。與傳統的印刷電路板(printed circuit board,PCB)系統相比,晶圓級中介層及重佈線結構的晶圓級圖案化可使得超大型微系統能夠具有高性能計算能力。可利用在單層中進行圖像移位曝光(image shift exposure)或多遮罩曝光(multi-mask exposure)來執行晶圓級圖案化。中介層及InFO封裝可具有精細重佈線層節距,此可在晶粒到晶粒內連線之間提供高頻寬。
圖1示出根據一些實施例的晶圓上系統100。積體電路(IC)晶粒50(標記為50A、50B及50C)由包封體112包封。在一些實施例中,IC晶粒50A是輸入/輸出(I/O)晶粒,IC晶粒50B是記憶體晶粒,且IC晶粒50C是系統單晶片(SoC)晶粒。在一些實施例中,IC晶粒50B可利用各自包括多個記憶體晶粒的堆疊式高頻寬記憶體(high bandwidth memory,HBM)裝置來替換。晶圓級中介層102接合在IC晶粒50A、50B、50C及包封體112之上。導電焊盤108及絕緣的接合層110位於中介層102的面對IC晶粒50的一側上,此使得IC晶粒50能夠通過例如混合接合(hybrid bonding)接合到中介層102。中介層102可包括具有主動組件及被動組件的塊狀矽晶圓,例如包括形成在中介層102中的通過金屬化層而連接的電晶體、電容器、電感器、二極體、電阻器及類似物(未示出)的靜態隨機存取記憶體(SRAM)電路系統。中介層還包括位於與IC晶粒50相對的表面上的導電焊盤114,且導電焊盤114實體耦合到且電耦合到中介層102中的基底穿孔(through substrate via,TSV)104,以用於將中介層102的電路系統(例如,SRAM電路系統)連接到晶粒150及介電穿孔(through dielectric via,TDV)118。晶粒150及TDV 118位於中介層102上且由包封體122包封。晶粒150可為包括例如(比如)電阻器、電感器、電容器或類似物等被動裝置的積體被動裝置(IPD)晶粒。重佈線結構124(也稱為內連線結構124)位於晶粒150及TDV 118上,且將晶粒150及TDV 118與位於重佈線結構124的頂側上的組件160及外部連接件170實體耦合且電耦合。重佈線結構124包括螺線管電感器146,螺線管電感器146可用作小型化電壓調節器模組(VRM)以提供提高的電性能。組件160可為晶粒、晶片或封裝(例如積體扇出型(InFO)封裝)。在一些實施例中,組件160包括脈波寬度調變(PWM)電路,脈波寬度調變(PWM)電路包括用於電源管理的金屬氧化物半導體場效電晶體(MOSFET)、邏輯電路、其組合或類似物。外部連接件170可為用於晶圓上系統100與例如光學連接件(參見下文,圖37)等外部系統之間的電界面及實體界面。
圖2示出根據一些實施例的積體電路晶粒50的剖視圖。積體電路晶粒50將在後續的處理中被封裝以形成晶圓上系統,例如圖1及圖21中所示晶圓上系統100及400。積體電路晶粒50可為邏輯晶粒(例如,中央處理器(central processing unit,CPU)、圖形處理單元(graphics processing unit,GPU)、系統單晶片(system-on-chip,SoC)、應用處理器(application processor,AP)、微控制器等)、記憶體晶粒(例如,動態隨機存取記憶體(dynamic random access memory,DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒等)、電源管理晶粒(例如,電源管理積體電路(power management integrated circuit,PMIC)晶粒)、射頻(radio frequency,RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system,MEMS)晶粒、信號處理晶粒(例如,數位訊號處理(digital signal processing,DSP)晶粒)、前端晶粒(例如,類比前端(analog front-end,AFE)晶粒)、應用專用晶粒(例如,應用專用積體電路(application-specific integrated circuit,ASIC)、現場可程式閘陣列(field-programmable gate array,FPGA)等)、類似晶粒、或其組合。
積體電路晶粒50可形成在晶圓中,所述晶圓可包括不同的裝置區,所述裝置區在後續步驟中被單體化以形成多個積體電路晶粒。可根據適用的製造製程對積體電路晶粒50進行處理以形成積體電路。舉例來說,積體電路晶粒50包括半導體基底52,例如經摻雜的或未經摻雜的矽、或者絕緣體上半導體(semiconductor-on-insulator,SOI)基底的主動層。半導體基底52可包含:其他半導體材料,例如鍺;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦;合金半導體,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或其組合。也可使用其他基底,例如多層式基底(multi-layered substrate)或梯度基底(gradient substrate)。半導體基底52具有有時被稱為前側的有效表面(例如,圖1中面朝上的表面)以及有時被稱為後側的非有效表面(例如,圖1中面朝下的表面)。可在半導體基底52的前表面處形成裝置。所述裝置可為主動裝置(例如,電晶體、二極體等)或被動裝置(例如,電容器、電阻器、電感器等)。
內連線結構54位於半導體基底52之上,且對所述裝置進行內連以形成積體電路。內連線結構54可通過例如半導體基底52上的介電層中的金屬化圖案形成。金屬化圖案包括形成在一個或多個低介電常數(low-k)介電層中的金屬線及金屬通孔。內連線結構54的金屬化圖案電耦合到半導體基底52的所述裝置。積體電路晶粒50還包括進行外部連接的焊盤(例如,鋁焊盤)。焊盤位於積體電路晶粒50的有效側上,例如位於內連線結構54中和/或內連線結構54上。一個或多個鈍化膜可位於積體電路晶粒50上(例如內連線結構54的部分上)。晶粒連接件56(例如導電支柱(例如由例如銅等金屬形成))實體耦合到且電耦合到內連線結構54。晶粒連接件56可通過例如鍍覆或類似製程形成。晶粒連接件56對積體電路晶粒50的相應的積體電路進行電耦合。
可選地,可在內連線結構54的焊盤上設置焊料區(例如,焊料球或焊料凸塊)。焊料球可用于對積體電路晶粒50執行晶片探針(chip probe,CP)測試。可對積體電路晶粒50執行CP測試以確定積體電路晶粒50是否是已知良好晶粒(known good die,KGD)。因此,只有作為KGD的積體電路晶粒50會經歷後續處理及封裝,而未通過CP測試的晶粒不會被封裝。在測試之後,焊料區可在後續的處理步驟中被移除。
介電層58可位於(或可不位於)積體電路晶粒50的有效側上,例如鈍化膜及晶粒連接件56上。介電層58在側向上包封晶粒連接件56,且介電層58在側向上與積體電路晶粒50相接。在開始時,介電層58可隱埋晶粒連接件56,使得介電層58的最頂表面位於晶粒連接件56的最頂表面上方。在其中晶粒連接件56上設置有焊料區的一些實施例中,介電層58也可隱埋焊料區。作為另外一種選擇,焊料區可在形成介電層58之前被移除。
介電層58可為:聚合物,例如聚苯並噁唑(polybenzoxazole,PBO)、聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobutene,BCB)或類似物;氮化物,例如氮化矽或類似物;氧化物,例如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass,BPSG)或類似物;類似材料;或者其組合。介電層58可例如通過旋轉塗布(spin coating)、疊層(lamination)、化學氣相沉積(chemical vapor deposition,CVD)或類似製程形成。在一些實施例中,晶粒連接件56在積體電路晶粒50的形成期間通過介電層58被暴露出。在一些實施例中,晶粒連接件56保持被隱埋且在用於封裝積體電路晶粒50的後續製程期間被暴露出。暴露出晶粒連接件56可移除晶粒連接件56上可能存在的任何焊料區。
在一些實施例中,積體電路晶粒50是包括多個半導體基底52的堆疊裝置。舉例來說,積體電路晶粒50可為記憶體裝置,例如混合記憶體立方體(hybrid memory cube,HMC)裝置、高頻寬記憶體(HBM)裝置或包括多個記憶體晶粒的類似裝置。在此種實施例中,積體電路晶粒50包括由基底穿孔(TSV)進行內連的多個半導體基底52。半導體基底52中的每一者可具有(或可不具有)內連線結構54。
圖3到圖20示出根據一些實施例在用於形成如以上在圖1中所示的晶圓上系統100的製程期間的中間步驟的剖視圖。因此,晶圓上系統100是大的。舉例來說,晶圓上系統100可具有超過10,000 mm
2的表面積。
在圖3中,在晶圓級中介層102上形成導電焊盤108及接合層110。中介層102可包括塊狀矽晶圓。在一些實施例中,中介層102可包括任何半導體基底、陶瓷基底、石英基底或類似物。在一些實施例中,中介層102包括絕緣體上矽(SOI)或其他複合晶圓。在一些實施例中,可在中介層102中形成主動組件及被動組件,例如電晶體、二極體、電阻器及類似物(未示出)。在一些實施例中,在中介層102內嵌置形成SRAM電路系統的電晶體以及導電線及導通孔。舉例來說,可在半導體基底上形成主動裝置,且可在主動裝置之上形成導電特徵106。導電特徵106對主動裝置進行電連接以形成一個或多個SRAM陣列。
嵌置在中介層102內的是各種金屬內連線特徵,例如基底穿孔(TSV)104及導電特徵106。在中介層102的頂表面上設置鈍化層62,且在鈍化層62的頂表面處暴露出輸入/輸出(I/O)焊盤60。將I/O焊盤60實體耦合到且電耦合到導電特徵106,且I/O焊盤60可包含例如(比如)銅、鈦、鎢、鋁或類似物等導電材料。鈍化層62可為:聚合物,例如PBO、聚醯亞胺、BCB或類似物;氮化物,例如氮化矽或類似物;氧化物,例如氧化矽、PSG、BSG、BPSG或類似物;類似材料;或者其組合。可例如通過旋轉塗布、疊層、化學氣相沉積(CVD)或類似製程形成鈍化層62。
仍然參照圖3,在I/O焊盤60上形成導電焊盤108,以用於將嵌置在中介層102內的TSV 104、導電特徵106及SRAM電路系統連接到後續貼合的IC晶粒(參見下文,圖4)。在I/O焊盤60的頂表面上形成導電焊盤108。導電焊盤108可表現出在約10 μm到約100 μm範圍內的精細節距,此可在後續貼合的IC晶粒50(參見下文,圖5)與中介層102中的嵌置式SRAM電路系統組件60之間提供高頻寬。
在一些實施例中,利用晶種層及鍍覆製程形成導電焊盤108。在中介層102之上形成晶種層。在一些實施例中,晶種層是金屬層,其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於鈦層之上的銅層。可使用例如物理氣相沉積(physical vapor deposition,PVD)或類似製程形成晶種層。然後在晶種層上形成光阻並對所述光阻進行圖案化。可利用在單層中進行圖像移位曝光或多遮罩曝光來執行對光阻的晶圓級圖案化。可通過旋轉塗布或類似製程形成光阻,且可將所述光阻暴露於光以供圖案化。光阻的圖案對應於導電焊盤108。所述圖案化穿過光阻形成開口以暴露出晶種層。然後在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可通過鍍覆(例如電鍍或無電鍍覆)或類似製程來形成所述導電材料。所述導電材料可包括金屬,如銅、鈦、鎢、鋁或類似物。所述導電材料與晶種層的下伏部分的組合會形成導電焊盤108。移除光阻以及晶種層的上面未形成有導電材料的部分。可通過例如使用氧電漿或類似物的可接受的灰化製程(ashing process)或剝除製程(stripping process)來移除光阻。一旦光阻被移除,便例如使用可接受的蝕刻製程(例如通過濕式蝕刻或乾式蝕刻)來移除晶種層的被暴露出的部分。
在一些實施例中,利用鑲嵌製程形成導電焊盤108,在所述鑲嵌製程中,利用光刻技術對作為介電層的接合層110進行圖案化及蝕刻以形成對應於導電焊盤的所期望圖案的溝槽。可沉積可選的擴散障壁層和/或可選的粘合層,且可利用導電材料填充溝槽。用於障壁層的適合材料包括鈦、氮化鈦、氧化鈦、鉭、氮化鉭、氧化鈦或其他替代物,且用於導電材料的適合材料包括銅、銀、金、鎢、鋁、其組合或類似物。在實施例中,可通過沉積由銅或銅合金構成的晶種層並通過電鍍填充溝槽來形成導電焊盤108。可使用化學機械拋光(chemical mechanical polish,CMP)製程或類似製程來從接合層110的表面移除過量的導電材料以及對所述表面進行平坦化以供後續處理。
圖3還示出在中介層102之上在導電焊盤108之間形成的接合層110。接合層110可為介電材料,例如氧化物(例如,氧化矽)或類似物。可例如通過旋轉塗布、疊層、化學氣相沉積(CVD)或類似製程形成接合層110。然而,可使用任何適合的方法或材料。在形成接合層110之後,對接合層110執行平坦化製程以暴露出導電焊盤108。在平坦化製程之後,接合層110的頂表面與導電焊盤108的頂表面可在製程變動內實質上共面。平坦化製程可為例如化學機械拋光(chemical-mechanical polish,CMP)、研磨製程(grinding process)或類似製程。
在圖4中,使用適合的接合方法將積體電路(IC)晶粒50(標記為50A、50B及50C)貼合到導電焊盤108,從而形成具有中介層102的晶圓上晶片(CoW)結構100。在一些實施例中,利用混合接合將IC晶粒50貼合到中介層102,所述混合接合包括晶粒連接件56之間的金屬-金屬接合(例如,Cu-Cu接合或Al-Al接合)以及接合層110與內連線結構54的介電層之間的氧化物-氧化物接合。利用金屬-金屬接合或混合接合而不是焊料接頭來貼合IC晶粒50(例如(比如)HBM晶粒)可降低插入損耗(insertion loss)。
作為IC晶粒50與中介層102之間的混合接合的實例,混合接合製程開始于將IC晶粒50與中介層102對準並接合。接合可包括對介電層58或接合層110中的一個或多個進行表面處置(surface treatment)。表面處置可包括電漿處置。可在真空環境中執行電漿處置。在電漿處置之後,表面處置可還包括可對介電層58或接合層110中的一個或多個施加的清潔製程(例如,利用去離子水或類似物進行清洗)。混合接合製程可然後繼續進行以將晶粒連接件56與導電焊盤108對準。當IC晶粒50與中介層102對準時,晶粒連接件56可與對應的導電焊盤108交疊。接下來,混合接合包括預接合步驟,在所述預接合步驟期間,使每一IC晶粒50與中介層102接觸。可在室溫下(例如,在約21℃與約25℃之間)執行預接合。混合接合製程繼續進行,例如在約150℃與約400℃之間的溫度下執行退火達約0.5小時與約3小時之間的持續時間,以使晶粒連接件56中的金屬(例如,銅)與導電焊盤108的金屬(例如,銅)彼此相互擴散,且因此形成直接金屬對金屬接合(direct metal-to-metal bonding)。
將所期望類型及數量的積體電路晶粒50(標記為50A、50B及50C)貼合到中介層102。在一些實施例中,IC晶粒50A是第一類型的IC晶粒,IC晶粒50B是第二類型的IC晶粒,且IC晶粒50C是第三類型的晶粒,例如(比如)邏輯晶粒(例如,中央處理器(CPU)、圖形處理單元(GPU)、系統單晶片(SoC)、應用處理器(AP)、微控制器等)、記憶體晶粒(例如,動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒、高頻寬記憶體(HBM)晶粒等)、電源管理晶片(例如,電源管理積體電路(PMIC)晶粒)、射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、信號處理晶粒(例如,數位訊號處理(DSP)晶粒)、前端晶粒(例如,類比前端(AFE)晶粒)、應用專用晶粒(例如,應用專用積體電路(ASIC)、現場可程式閘陣列(FPGA)等)、輸入/輸出(I/O)晶粒或類似晶粒。在一些實施例中,IC晶粒50A是I/O晶粒,IC晶粒50B是HBM晶粒,且IC晶粒50C是SoC晶粒。已知良好晶粒(KGD)可用于IC晶粒50A、50B及50C,以提供良好的系統良率。
在圖5中,在各種組件上及周圍形成包封體112。在形成之後,包封體112包封積體電路晶粒50。包封體112可為模製化合物、環氧樹脂或類似物,且可通過壓縮模製(compression molding)、轉移模製(transfer molding)或類似製程來施加包封體112。可以液體或半液體形式施加包封體112,且然後隨後進行固化。在一些實施例中,在中介層102之上形成包封體112,使得積體電路晶粒50被隱埋或覆蓋,且然後對包封體112執行平坦化製程以暴露出積體電路晶粒50。在平坦化製程之後,包封體112的最頂表面與IC晶粒50的最頂表面共面。平坦化製程可為例如化學機械拋光(CMP)。
在圖6中,將中介層102及經包封的IC晶粒50翻轉並放置在載體基底66上。在一些實施例中,粘合層108位於載體基底66上。載體基底66可為玻璃載體基底、陶瓷載體基底或類似物。載體基底66可為晶圓,使得可在載體基底66上同時形成多個封裝。可將粘合層108與載體基底66一起從將在後續步驟中形成的上覆結構移除。在一些實施例中,粘合層108是任何適合的粘合劑、環氧樹脂、晶粒貼合膜(die attach film,DAF)或類似物,且被施加在載體基底66的表面之上。
在圖7中,對中介層102的後側(背離載體基底66的一側)進行平坦化以暴露出基底穿孔(TSV)104的頂表面。平坦化製程可為例如研磨和/或化學機械拋光(CMP)。
在圖8中,形成導電焊盤114、接合層116及介電穿孔(TDV)118以用於將TSV 104連接到後續形成的重佈線結構124(參見下文,圖11到圖13)。在TSV 104的頂表面上形成導電焊盤114。作為形成導電焊盤114的實例,在中介層102之上形成晶種層。在一些實施例中,晶種層是金屬層,其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於鈦層之上的銅層。可使用例如物理氣相沉積(PVD)或類似製程形成晶種層。然後在晶種層上形成光阻並對所述光阻進行圖案化。可通過旋轉塗布或類似製程形成光阻,且可將所述光阻暴露於光以供圖案化。光阻的圖案對應於導電焊盤114。所述圖案化穿過光阻形成開口以暴露出晶種層。然後在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可通過鍍覆(例如電鍍或無電鍍覆)或類似製程形成所述導電材料。所述導電材料可包括金屬,如銅、鈦、鎢、鋁或類似物。所述導電材料與晶種層的下伏部分的組合會形成導電焊盤114。移除光阻以及晶種層的上面未形成有導電材料的部分。可通過例如使用氧電漿或類似物的可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除,便例如使用可接受的蝕刻製程(例如通過濕式蝕刻或乾式蝕刻)來移除晶種層的被暴露出的部分。
圖8還示出在中介層102之上在導電焊盤114之間形成的接合層116。可使用與如以上參照圖3所述的接合層110實質上相似的方法及材料形成接合層116。然而,可使用任何適合的方法或材料。在形成接合層116之後,對接合層116執行平坦化製程以暴露出導電焊盤114。在平坦化製程之後,接合層116的頂表面與導電焊盤114的頂表面可在製程變動內實質上共面。平坦化製程可為例如化學機械拋光(CMP)、研磨製程或類似製程。
仍然參照圖8,在導電焊盤114中的一些導電焊盤114上形成介電穿孔(TDV)118。作為形成介電穿孔118的實例,在導電焊盤114上形成光阻(photoresist)並對所述光阻進行圖案化。可通過旋轉塗布或類似製程形成光阻,且可將所述光阻暴露於光以供圖案化。光阻的圖案對應于後續形成的TDV 118。所述圖案化穿過光阻形成開口,以暴露出導電焊盤114。通過在光阻的開口中及在導電焊盤114上形成導電材料來形成TDV 118。可通過鍍覆(例如電鍍或無電鍍覆)或類似製程形成TDV 118的導電材料。所述導電材料可包括金屬,如銅、鈦、鎢、鋁或類似物。例如通過例如使用氧電漿或類似物的可接受的灰化製程或剝除製程來移除光阻,留下從導電焊盤114延伸的TDV 118。
在圖9中,將晶粒150貼合到與TDV 118相鄰的導電焊盤114,從而形成包括中介層102的晶圓上晶片(CoW)結構,中介層102在中介層102的兩側上具有晶片(例如,晶粒150)。在一些實施例中,晶粒150是積體被動裝置(IPD)晶粒,積體被動裝置(IPD)晶粒包括例如(比如)電阻器、電感器、電容器或類似物等被動裝置。晶粒150可具有與參照圖2闡述的IC晶粒50實質上相似的配置,但包括例如電阻器、電感器、電容器等被動裝置且不包括例如(比如)電晶體等任何主動裝置。然而,晶粒150可為另一種適合類型的晶粒,例如,如以上參照圖4闡述的IC晶粒。在一些實施例中,利用混合接合將晶粒150貼合到中介層102,所述混合接合包括晶粒150的晶粒連接件56與導電焊盤114之間的金屬-金屬接合(例如,Cu-Cu接合或Al-Al接合)以及接合層110與晶粒150的內連線結構54的介電層之間的氧化物-氧化物接合。混合接合製程可實質上相似於以上參照圖4闡述的混合接合。將所期望類型及數量的晶粒150貼合到中介層102。在一些實施例中,晶粒150包括延伸到晶粒150的最頂表面的基底穿孔(TSV)120。
在圖10中,在各種組件上及周圍形成包封體122。在形成之後,包封體122包封晶粒150及TDV 118。包封體122可為模製化合物、聚合物、環氧樹脂、氧化矽填充體材料、類似物或其組合,且可通過壓縮模製、轉移模製或類似製程來施加包封體122。可以液體或半液體形式施加包封體122,且然後隨後進行固化。在一些實施例中,將包封體122形成為使得晶粒150及TDV 118被隱埋或覆蓋,且然後對包封體122執行平坦化製程以暴露出晶粒150的TSV 120以及TDV 118。在平坦化製程之後,包封體122的最頂表面、TSV 120的最頂表面及TDV 118的最頂表面共面。平坦化製程可為例如化學機械拋光(CMP)。
圖11示出重佈線結構124的底部部分124A的形成。底部部分124A包括介電層126及130以及金屬化圖案128及132。在一些實施例中,介電層126與130由相同的介電材料形成,且被形成為相同的厚度。類似地,在一些實施例中,金屬化圖案128與132的導電特徵由相同的導電材料形成,且被形成為相同的厚度。重佈線結構124的金屬化圖案128的底部部分可具有在約1 μm到約50 μm範圍內的精細節距,此可在IC晶粒50的內連線之間提供高頻寬。
作為形成底部部分124A的一個實例,在包封體122、晶粒150及TDV 118上沉積介電層126。在一些實施例中,介電層126由例如PBO、聚醯亞胺、BCB或類似物等可使用光刻遮罩來圖案化的感光性材料形成。可通過旋轉塗布、疊層、CVD、類似製程或其組合來形成介電層126。然後對介電層126進行圖案化。可通過可接受的製程(例如當介電層126是感光性材料時通過將介電層126暴露於光,或者通過使用例如各向異性蝕刻進行蝕刻)來執行圖案化。如果介電層126是感光性材料,則介電層126可在曝光之後顯影。
然後形成金屬化圖案128。金屬化圖案128具有位於介電層126的主表面上且沿所述主表面延伸的線部分(也稱為導電線或導電跡線),且具有延伸穿過介電層126以對TDV 118與TSV 120進行實體耦合及電耦合的通孔部分(也稱為導通孔)。作為形成金屬化圖案128的實例,在介電層126之上及在延伸穿過介電層126的開口中形成晶種層。在一些實施例中,晶種層是金屬層,其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於鈦層之上的銅層。可使用例如物理氣相沉積(PVD)或類似製程形成晶種層。然後在晶種層上形成光阻並對所述光阻進行圖案化。可通過旋轉塗布或類似製程形成光阻,且可將所述光阻暴露於光以供圖案化。光阻的圖案對應於金屬化圖案128。所述圖案化穿過光阻形成開口以暴露出晶種層。然後在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可通過鍍覆(例如電鍍或無電鍍覆)或類似製程形成所述導電材料。所述導電材料可包括金屬,如銅、鈦、鎢、鋁或類似物。所述導電材料與晶種層的下伏部分的組合會形成金屬化圖案128。移除光阻以及晶種層的上面未形成有導電材料的部分。可通過例如使用氧電漿或類似物的可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除,便例如使用可接受的蝕刻製程(例如通過濕式蝕刻或乾式蝕刻)來移除晶種層的被暴露出的部分。
然後在金屬化圖案128及介電層126上沉積介電層130。可以與介電層126相似的方式及相似的材料形成介電層130。然後形成金屬化圖案132。金屬化圖案132具有位於介電層130的主表面上且沿所述主表面延伸的線部分,且具有延伸穿過介電層130以對金屬化圖案128進行實體耦合及電耦合的通孔部分。可以與金屬化圖案128相似的方式及相似的材料形成金屬化圖案132。
在圖12中,在介電層130上放置磁晶片材134,以便在重佈線結構124中形成嵌置式螺線管電感器。為在重佈線結構124中形成小型化電壓調節器模組(VRM),在重佈線結構124中形成嵌置式螺線管電感器可為有用的,此可由於更緊湊的結構而提供提高的電性能。磁晶片材134包含例如金屬(如銅、鈦、鎢、鋁或類似物)等導電材料。磁晶片材134可具有在約1 μm到約10 μm範圍內的高度、在約1 mm到約10 mm範圍內的寬度及在約1 mm到約10 mm範圍內的長度。在一些實施例中,磁晶片材134是銅線圈。
在圖13中,在底部部分124A之上形成重佈線結構124的頂部部分124B,從而在磁晶片材134周圍完成螺線管電感器146。嵌置式螺線管電感器146的對稱模製結構可防止螺線管電感器146中的小組件(例如磁晶片材134)的翹曲。頂部部分124B包括介電層138及142以及金屬化圖案140及144。在一些實施例中,介電層138與142由相同的介電材料形成,且被形成為相同的厚度。類似地,在一些實施例中,金屬化圖案140與144的導電特徵由相同的導電材料形成,且被形成為相同的厚度。
在金屬化圖案132、介電層130及磁晶片材134上沉積介電層138。可以與介電層126相似的方式及相似的材料形成介電層138。然後形成金屬化圖案140。金屬化圖案140具有位於介電層138的主表面上且沿所述主表面延伸的線部分,且具有延伸穿過介電層138以對金屬化圖案132進行實體耦合及電耦合的通孔部分。可以與金屬化圖案128相似的方式及相似的材料形成金屬化圖案140。
然後在金屬化圖案140及介電層138上沉積介電層142。可以與介電層126相似的方式及相似的材料形成介電層142。然後形成金屬化圖案144。金屬化圖案144具有位於介電層142的主表面上且沿所述主表面延伸的線部分,且具有延伸穿過介電層142以對金屬化圖案140進行實體耦合及電耦合的通孔部分。可以與金屬化圖案128相似的方式及相似的材料形成金屬化圖案144。
螺線管電感器146由磁晶片材134及金屬化圖案128、132、140及144的周圍部分形成。將螺線管電感器146形成為嵌置在重佈線結構124中。此對於在重佈線結構124中形成小型化電壓調節器模組(VRM)可為有用的。嵌置式螺線管電感器146的緊湊結構可提供提高的電性能。
在圖14中,形成電耦合到且實體耦合到金屬化圖案144的凸塊下金屬(under-bump metallurgy,UBM)148,以用於與重佈線結構124進行外部連接。UBM 148具有位於介電層142的主表面上且沿所述主表面延伸的凸塊部分。在一些實施例(未示出)中,UBM 148具有延伸穿過介電層142以對金屬化圖案144進行實體耦合及電耦合的通孔部分。因此,UBM 148電耦合到晶粒150、TDV 118及螺線管電感器146。可以與金屬化圖案128相似的方式及相似的材料形成UBM 148。在一些實施例中,UBM 148具有與金屬化圖案128、132、140及144不同的大小。
在圖15中,將所述結構翻轉並放置在膠帶142上,且執行載體基底剝離以將載體基底66從包封體112及積體電路晶粒50拆離(或「剝離」)。在一些實施例中,剝離包括通過例如研磨或平坦化製程(例如CMP)來移除載體基底66及粘合層108。在移除之後,積體電路晶粒50的後側表面被暴露出,且包封體112的後側表面與積體電路晶粒50的後側表面齊平。可執行清潔以移除粘合層108的殘留物。
在圖16中,再次將所述結構翻轉,且在UBM 148上形成導電連接件152。導電連接件152可為球柵陣列(ball grid array,BGA)連接件、焊料球、金屬支柱、受控塌陷晶片連接(controlled collapse chip connection,C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸塊或類似物。導電連接件152可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或其組合等導電材料。在一些實施例中,通過透過蒸鍍、電鍍、印刷、焊料轉移、植球或類似製程最初形成焊料層或焊料膏層來形成導電連接件152。一旦已在所述結構上形成焊料層,便可執行回焊(reflow),以便將材料造型成所期望的凸塊形狀。
在圖17中,將組件160及外部連接件170貼合到重佈線結構124。組件160可為晶粒、晶片或例如積體扇出型(InFO)封裝等封裝。在一些實施例中,組件160包括脈波寬度調變(PWM)電路,脈波寬度調變(PWM)電路包括用於電源管理的金屬氧化物半導體場效電晶體(MOSFET)。外部連接件170可包括用於晶圓上系統100與外部系統之間的電界面及實體界面。舉例來說,當晶圓上系統100被安裝為例如數據中心等較大外部系統的一部分時,外部連接件170可用於將晶圓上系統100耦合到外部系統。外部連接件170的實例包括光學連接件(參見下文,圖37)、帶狀纜線接納器、柔性印刷電路或類似物。
在圖18中,可形成底部填充膠154來填充組件160及外部連接件170與重佈線結構124之間的間隙。可在貼合組件160及外部連接件170之後通過毛細流動製程(capillary flow process)形成底部填充膠154,或者可在貼合組件160及外部連接件170之前通過適合的沉積方法形成底部填充膠154。
在圖19中,穿過晶圓上系統100形成螺栓孔156。可通過例如雷射鑽孔、機械鑽孔或類似製程等鑽孔製程形成螺栓孔156。可通過利用鑽孔製程鑽出螺栓孔156的輪廓且然後移除通過所述輪廓分隔開的材料來形成螺栓孔156。在一些實施例中,更早地(例如在形成圖16中的導電連接件之前)形成螺栓孔156。然而,可在製程的任何適合的步驟處形成螺栓孔156。
圖20示出根據一些實施例的晶圓上系統組件的剖視圖。晶圓上系統組件是通過將晶圓上系統100固定在熱模組200與機械支架300之間而形成。熱模組200可為散熱件(heat sink)、散熱器(heat spreader)、冷板(cold plate)或類似物。機械支架300是可由例如金屬(例如,鋼、鈦、鈷或類似物)等具有高剛度的材料形成的剛性支撐件。機械支架300實體嚙合重佈線結構124的部分。通過將晶圓上系統100夾持在熱模組200與機械支架300之間,可減少例如由載體基底剝離引起的晶圓上系統100的翹曲。為易於模組安裝,機械支架300可為具有暴露出組件160及外部連接件170的開口的格柵(grid)。
晶圓上系統100被從膠帶142移除,且利用螺栓202緊固在熱模組200與機械支架300之間。將螺栓202擰過晶圓上系統100的螺栓孔156、擰過熱模組200中對應的螺栓孔且擰過機械支架300中對應的螺栓孔。將緊固件204擰到螺栓202上並擰緊,以將晶圓上系統100夾持在熱模組200與機械支架300之間。緊固件204可為例如擰到螺栓202的螺母。緊固件204在晶圓上系統組件的兩側處(例如,在具有熱模組200的一側(有時稱為後側)及具有機械支架300的一側(有時稱為前側)處)貼合到螺栓202。在被貼合之後,機械支架300的部分設置在組件160和/或外部連接件170之間。
在將各種組件緊固在一起之前,可在晶圓上系統100的後側上分配熱界面材料(thermal interface material,TIM)208,從而將熱模組200實體耦合到且熱耦合到積體電路晶粒50。在一些實施例中,TIM 206由包含銦及HM03型材料的膜形成。在緊固期間,緊固件204被擰緊,從而增大由熱模組200及機械支架300施加到晶圓上系統100的機械力。緊固件204被擰緊,直到熱模組200在TIM 206上施予所期望量的壓力為止。
圖21示出根據一些替代實施例的晶圓上系統400。晶圓上系統400可相似於以上參照圖1及圖4到圖19闡述的晶圓上系統100,其中相同的參考編號指示使用相同的製程形成的相同元件。積體電路(IC)晶粒50(標記為50A及50B)及封裝450由包封體112包封。在一些實施例中,IC晶粒50A是輸入/輸出(I/O)晶粒,IC晶粒50B是堆疊的各自包括多個記憶體晶粒的高頻寬記憶體(HBM)裝置,且IC晶粒50E是包括SoC電路系統、SRAM電路系統及基底穿孔(TSV)的混合SRAM/SoC晶粒,所述基底穿孔(TSV)可將IC晶粒50E電耦合到位於IC晶粒50A、50B及50E以及包封體112之上的晶圓級中介層102。導電焊盤408及接合層410位於中介層402的面對IC晶粒50的一側上。中介層402可包括具有主動組件和/或被動組件(例如(比如)形成在中介層402中的二極體、電容器、電感器、電阻器及類似物(未示出))的塊狀矽晶圓。導電焊盤408實體耦合到且電耦合到基底穿孔(TSV)404,以用於將IPD電路系統連接到位於中介層402上的重佈線結構424(也稱為內連線結構424)。重佈線結構424將中介層402與位於重佈線結構124的頂側上的組件160及外部連接件170實體耦合及電耦合。重佈線結構424包括螺線管電感器446,其可用作小型化電壓調節器模組(VRM),以提供提高的電性能。組件160可為包括例如用於電源管理的PWM電路以及MOSFET的InFO封裝。外部連接件170可為晶圓上系統400與例如光學連接件(參見下文,圖37)等外部系統之間的電界面及實體界面。
圖22示出根據一些實施例的封裝450的剖視圖。封裝450包括堆疊在另一IC晶粒470上且接合到所述另一IC晶粒470的IC晶粒460。IC晶粒460可為記憶體晶粒(例如,動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒等)、電源管理晶粒(例如,電源管理積體電路(PMIC)晶粒),且IC晶粒470可為邏輯晶粒(例如中央處理器(CPU)、圖形處理單元(GPU)、系統單晶片(SoC)、應用處理器(AP)、微控制器等)。在一些實施例中,IC晶粒460是SRAM晶粒,且IC晶粒470是SoC晶粒。
在一些實施例中,IC晶粒460及470具有與以上參照圖2闡述的IC晶粒50相似的結構及材料。IC晶粒460具有半導體基底462、位於半導體基底462之上的內連線結構464、實體耦合到且電耦合到內連線結構464的晶粒連接件466以及位於內連線結構464之上且在側向上包封晶粒連接件466的介電層468。IC晶粒460也可具有延伸穿過半導體基底462且對內連線結構464進行實體耦合及電耦合的基底穿孔(TSV)463。IC晶粒470具有半導體基底472、位於半導體基底472之上的內連線結構474、實體耦合到且電耦合到內連線結構474的晶粒連接件476以及位於內連線結構474之上且在側向上包封晶粒連接件476的介電層478。
可通過相應的介電層468及478與相應的晶粒連接件466及476之間的適合的接合方法(例如混合接合)來對IC晶粒460與IC晶粒470進行接合。可以與如以上參照圖4闡述的IC晶粒50與中介層102之間的混合接合相似的方式來執行混合接合。
在將晶粒460接合到IC晶粒470之後,在晶粒連接件476上形成介電穿孔(TDV)454。TDV 454可以與如以上參照圖8闡述的TDV 118相似的方式形成。然後通過包封體452來包封IC晶粒460及TDV 454,包封體452可以與如以上參照圖5闡述的包封體112相似的方式形成。在一些實施例中,在IC晶粒460及TDV 454之上形成包封體452,使得IC晶粒460及TDV 454被隱埋或覆蓋,且然後對包封體452執行平坦化製程以暴露出IC晶粒460的TDV 454及TSV 463。在平坦化製程之後,包封體452的頂表面、TDV 454的頂表面、半導體基底462的頂表面及TSV 463的頂表面共面。平坦化製程可為例如化學機械拋光(CMP)。
然後,在TDV 454及TSV 463的頂表面之上形成導電焊盤456,且在包封體452及半導體基底462之上在導電焊盤456之間形成接合層。可使用與如以上參照圖3闡述的導電焊盤108及接合層110實質上相似的方法及材料來形成導電焊盤456及接合層458。然而,可使用任何適合的方法或材料。導電焊盤456及接合層458可使得包括IC晶粒460及470的封裝450能夠混合接合到例如如以下參照圖24闡述的中介層402。導電焊盤456可電連接到TDV 454以及IC晶粒460及470構成的電路系統。
圖23到圖35示出根據一些實施例在用於形成如以上在圖21中所示的晶圓上系統400的製程期間的中間步驟的剖視圖。因此,晶圓上系統400是大的。舉例來說,晶圓上系統400可具有超過10,000 mm
2的表面積。
在圖23中,在晶圓級中介層402上形成導電焊盤408及接合層410。中介層402可為半導體基底或晶圓。中介層402可包括塊狀矽晶圓。在一些實施例中,中介層402可包括任何半導體基底、陶瓷基底、石英基底或類似物。在一些實施例中,中介層102包括絕緣體上矽(SOI)或其他複合晶圓。在一些實施例中,在中介層402中嵌置例如基底穿孔(TSV)404及導電特徵406等各種金屬內連線特徵。導電特徵406可包括例如電阻器、電感器、電容器及類似物(未示出)等嵌置式被動組件。在一些實施例中,中介層402可不具有例如電晶體或類似物等任何主動組件。
進一步參照圖23,在中介層402的頂表面上設置鈍化層72,且在鈍化層72的頂表面處暴露出輸入/輸出(I/O)焊盤70。將I/O焊盤70實體耦合到且電耦合到導電特徵406,且I/O焊盤70可包含例如(比如)銅、鈦、鎢、鋁或類似物等導電材料。鈍化層72可為:聚合物,例如PBO、聚醯亞胺、BCB或類似物;氮化物,例如氮化矽或類似物;氧化物,例如氧化矽、PSG、BSG、BPSG或類似物;類似材料;或者其組合。可例如通過旋轉塗布、疊層、化學氣相沉積(CVD)或類似製程形成鈍化層72。
仍然參照圖23,在I/O焊盤70上形成導電焊盤408,以用於將導電特徵406連接到後續貼合的IC晶粒(參見下文,圖24)。導電焊盤108可表現出精細節距,此可在後續貼合的IC晶粒50(參見下文,圖24)與嵌置在中介層102中的被動裝置(例如(比如)電容器)之間提供高頻寬。可利用與如以上參照圖4闡述的導電焊盤108實質上相似的方法及材料來形成導電焊盤408。
圖23還示出在中介層402之上在導電焊盤408之間形成的接合層410。可利用與如以上參照圖4闡述的接合層110實質上相似的方法及材料來形成接合層410。然而,可使用任何適合的方法或材料。在形成接合層410之後,對接合層410執行平坦化製程以暴露出導電焊盤408。在平坦化製程之後,接合層410的頂表面與導電焊盤408的頂表面可在製程變動內實質上共面。平坦化製程可為例如化學機械拋光(CMP)、研磨製程或類似製程。
在圖24中,使用適合的接合方法將積體電路(IC)晶粒50(標記為50A及50B)及封裝450(參見上文,圖22)貼合到導電焊盤408,從而形成具有中介層402的晶圓上晶片(CoW)結構400。在一些實施例中,利用混合接合將IC晶粒50及封裝450貼合到中介層402,所述混合接合包括晶粒連接件56與導電焊盤408之間以及導電焊盤456與導電焊盤408之間的金屬-金屬接合(例如,Cu-Cu接合或Al-Al接合)、接合層110與IC晶粒50的介電層58之間以及接合層110與封裝450的接合層458之間的氧化物-氧化物接合。利用金屬-金屬接合或混合接合而不是焊料接頭來貼合IC晶粒50(例如(比如)HBM晶粒)及封裝450可減少插入損耗。混合接合製程可與以上參照圖4闡述的混合接合實質上相似。將所期望類型及數量的積體電路晶粒50及封裝450貼合到中介層402。在一些實施例中,IC晶粒50A是第一類型的IC晶粒,且IC晶粒50B是第二類型的IC晶粒,例如(比如)邏輯晶粒(例如,中央處理器(CPU)、圖形處理單元(GPU)、系統單晶片(SoC)、應用處理器(AP)、微控制器等)、記憶體晶粒(例如,動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒、高頻寬記憶體(HBM)晶粒等)、電源管理晶粒(例如,電源管理積體電路(PMIC)晶粒)、射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、信號處理晶粒(例如,數位訊號處理(DSP)晶粒)、前端晶粒(例如,類比前端(AFE)晶粒)、應用專用晶粒(例如,應用專用積體電路(ASIC)、現場可程式閘陣列(FPGA)等)、輸入/輸出(I/O)晶粒、積體被動裝置(IPD)晶粒或類似晶粒。在一些實施例中,IC晶粒50A是I/O晶粒,且IC晶粒50B是HBM晶粒。已知良好晶粒(KGD)可用于IC晶粒50A及50B,以提供良好的系統良率。
在圖25中,在各種組件上及周圍形成包封體112。在形成後,包封體112包封積體電路晶粒50及封裝450。包封體112可為模製化合物、環氧樹脂或類似物,且可通過壓縮模製、轉移模製或類似製程來施加包封體112。可以液體或半液體形式施加包封體112,且然後隨後進行固化。在一些實施例中,在中介層402之上形成包封體112,使得積體電路晶粒50及封裝450被隱埋或覆蓋,且然後對包封體112執行平坦化製程以暴露出積體電路晶粒50及封裝450。在平坦化製程之後,包封體112的最頂表面、IC晶粒50的最頂表面及封裝450的最頂表面共面。平坦化製程可為例如化學機械拋光(CMP)。
在圖26中,將中介層402及經封裝的IC晶粒50及封裝450翻轉並放置在載體基底66上。在一些實施例中,粘合層108位於載體基底66上。載體基底66可為玻璃載體基底、陶瓷載體基底或類似物。載體基底66可為晶圓,使得可在載體基底66上同時形成多個封裝。可將粘合層108與載體基底66一起從將在後續步驟中形成的上覆結構移除。在一些實施例中,粘合層108是任何適合的粘合劑、環氧樹脂、晶粒貼合膜(DAF)或類似物,且被施加在載體基底66的表面之上。
在圖27中,對中介層402的後側(背離載體基底66的一側)進行平坦化以暴露出基底穿孔(TSV)404的頂表面。平坦化製程可為例如研磨和/或化學機械拋光(CMP)。
圖28示出重佈線結構424的底部部分424A的形成。底部部分424A包括介電層414、426及430以及金屬化圖案416、428及432。在一些實施例中,介電層414、426及430由相同的介電材料形成,且被形成為相同的厚度。類似地,在一些實施例中,金屬化圖案416、428及432的導電特徵由相同的導電材料形成,且被形成為相同的厚度。重佈線結構424的金屬化圖案416的底部部分可具有在約10 μm到約100 μm範圍內的精細節距,此可在IC晶粒50的內連線之間提供高頻寬。
作為形成底部部分424A的實例,在中介層402的後側上沉積介電層414。在一些實施例中,介電層414由例如PBO、聚醯亞胺、BCB或類似物等可使用光刻遮罩來圖案化的感光性材料形成。可通過旋轉塗布、疊層、CVD、類似製程或其組合來形成介電層414。然後對介電層414進行圖案化。可通過可接受的製程(例如當介電層414是感光性材料時通過將介電層414暴露於光,或者通過使用例如各向異性蝕刻進行蝕刻)來執行圖案化。如果介電層414是感光性材料,則介電層414可在曝光之後顯影。
然後形成金屬化圖案416。金屬化圖案416具有位於介電層414的主表面上且沿所述主表面延伸的線部分(也稱為導電線或導電跡線),且具有延伸穿過介電層414以對TSV 404進行實體耦合及電耦合的通孔部分(也稱為導通孔)。作為形成金屬化圖案416的實例,在介電層414之上及在穿過介電層414延伸到TSV 404的頂表面的開口中形成晶種層。在一些實施例中,晶種層是金屬層,其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於鈦層之上的銅層。可使用例如物理氣相沉積(PVD)或類似製程形成晶種層。然後在晶種層上形成光阻並對所述光阻進行圖案化。可通過旋轉塗布或類似製程形成光阻,且可將所述光阻暴露於光以供圖案化。光阻的圖案對應於金屬化圖案416。所述圖案化穿過光阻形成開口以暴露出晶種層。然後在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可通過鍍覆(例如電鍍或無電鍍覆)或類似製程形成所述導電材料。所述導電材料可包括金屬,如銅、鈦、鎢、鋁或類似物。所述導電材料與晶種層的下伏部分的組合會形成金屬化圖案416。移除光阻以及晶種層的上面未形成有導電材料的部分。可通過例如使用氧電漿或類似物的可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除,便例如使用可接受的蝕刻製程(例如通過濕式蝕刻或乾式蝕刻)來移除晶種層的被暴露出的部分。
然後在金屬化圖案416及介電層414上沉積介電層426。可以與介電層414相似的方式及相似的材料形成介電層426。然後形成金屬化圖案428。金屬化圖案428具有位於介電層426的主表面上且沿所述主表面延伸的線部分,且具有延伸穿過介電層426以對金屬化圖案416進行實體耦合及電耦合的通孔部分。可以與金屬化圖案416相似的方式及相似的材料形成金屬化圖案428。
然後在金屬化圖案428及介電層426上沉積介電層430。可以與介電層414相似的方式及相似的材料形成介電層430。然後形成金屬化圖案432。金屬化圖案432具有位於介電層430的主表面上且沿所述主表面延伸的線部分,且具有延伸穿過介電層430以對金屬化圖案428進行實體耦合及電耦合的通孔部分。可以與金屬化圖案416相似的方式及相似的材料形成金屬化圖案432。
在圖29中,在介電層430上放置磁晶片材434,以便在重佈線結構424中形成嵌置式螺線管電感器。為在重佈線結構424中形成小型化電壓調節器模組(VRM),在重佈線結構424中形成嵌置式螺線管電感器可為有用的,此可由於更緊湊的結構而提供提高的電性能。磁晶片材434包含例如金屬(如銅、鈦、鎢、鋁或類似物)等導電材料。磁晶片材434可具有在約1 μm到約10 μm範圍內的高度、在約1 mm到約10 mm範圍內的寬度以及在約1 mm到約10 mm範圍內的長度。在一些實施例中,磁晶片材434是銅線圈。
在圖30中,在底部部分424A之上形成重佈線結構424的頂部部分424B,從而在磁晶片材434周圍完成螺線管電感器446,且在重佈線結構424上形成UBM 448。嵌置式螺線管電感器446的對稱模製結構可防止螺線管電感器446中的小組件(例如磁晶片材434)的翹曲。頂部部分424B包括介電層438及442以及金屬化圖案440及444。在一些實施例中,介電層438與442由相同的介電材料形成,且被形成為彼此相同的厚度(例如在約1 μm到約50 μm範圍內)。類似地,在一些實施例中,金屬化圖案440與444的導電特徵由相同的導電材料形成,且被形成為彼此相同的厚度(例如在約1 μm到約30 μm範圍內)。
在金屬化圖案432、介電層430及磁晶片材434上沉積介電層438。可以與介電層414相似的方式及相似的材料形成介電層438。然後形成金屬化圖案440。金屬化圖案440具有位於介電層438的主表面上且沿所述主表面延伸的線部分,且具有延伸穿過介電層438以對金屬化圖案432進行實體耦合及電耦合的通孔部分。可以與金屬化圖案416相似的方式及相似的材料形成金屬化圖案440。
然後在金屬化圖案440及介電層438上沉積介電層442。可以與介電層414相似的方式及相似的材料形成介電層142。然後形成金屬化圖案444。金屬化圖案444具有位於介電層442的主表面上且沿所述主表面延伸的線部分,且具有延伸穿過介電層442以對金屬化圖案440進行實體耦合及電耦合的通孔部分。可以與金屬化圖案416相似的方式及相似的材料形成金屬化圖案444。
螺線管電感器446由磁晶片材434以及金屬化圖案428、432、440及444的周圍部分形成。將螺線管電感器446形成為嵌置在重佈線結構424中。此對於在重佈線結構424中形成小型化電壓調節器模組(VRM)可為有用的。嵌置式螺線管電感器446的緊湊結構可提供提高的電性能。
進一步參照圖30,形成電耦合到且實體耦合到金屬化圖案444的UBM 148,以用於與重佈線結構424進行外部連接。UBM 448具有位於介電層442的主表面上且沿所述主表面延伸的凸塊部分。在一些實施例(未示出)中,UBM 448具有延伸穿過介電層442以對金屬化圖案444進行實體耦合及電耦合的通孔部分。因此,UBM 448電耦合到螺線管電感器446及中介層402。可以與金屬化圖案416相似的方式及相似的材料形成UBM 448。在一些實施例中,UBM 448具有與金屬化圖案416、428、432、440及444不同的大小。
在圖31中,將所述結構翻轉並放置在膠帶142上,且執行載體基底剝離以將載體基底66從包封體112及積體電路晶粒50拆離(或「剝離」)。在一些實施例中,剝離包括通過例如研磨或平坦化製程(例如CMP)來移除載體基底66及粘合層108。在移除之後,積體電路晶粒50的後側表面被暴露出,且包封體112的後側表面與積體電路晶粒50的後側表面齊平。可執行清潔以移除粘合層108的殘留物。
在圖32中,再次將所述結構翻轉,且在UBM 148上形成導電連接件152。導電連接件152可為球柵陣列(BGA)連接件、焊料球、金屬支柱、受控塌陷晶片連接(C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(ENEPIG)形成的凸塊或類似物。導電連接件152可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合等導電材料。在一些實施例中,通過透過蒸鍍、電鍍、印刷、焊料轉移、植球或類似製程最初形成焊料層或焊料膏層來形成導電連接件152。一旦已在所述結構上形成焊料層,便可執行回焊,以便將材料造型成所期望的凸塊形狀。
在圖33中,將組件160及外部連接件170貼合到重佈線結構424。組件160可為晶粒、晶片或例如積體扇出型(InFO)封裝等封裝。在一些實施例中,組件160包括脈波寬度調變(PWM)電路,脈波寬度調變(PWM)電路包括用於電源管理的金屬氧化物半導體場效電晶體(MOSFET)。外部連接件170是用於晶圓上系統100與外部系統之間的電界面及實體界面。舉例來說,當晶圓上系統100被安裝為例如數據中心等較大外部系統的一部分時,可使用外部連接件170將晶圓上系統400耦合到外部系統。外部連接件170的實例包括光學連接件(參見下文,圖38)、帶狀纜線接納器、柔性印刷電路或類似物。
在圖34中,可形成底部填充膠154來填充組件160及外部連接件170與重佈線結構124之間的間隙。可在貼合組件160及外部連接件170之後通過毛細流動製程形成底部填充膠154,或者可在貼合組件160及外部連接件170之前通過適合的沉積方法形成底部填充膠154。
在圖35中,穿過晶圓上系統400形成螺栓孔156。可通過例如雷射鑽孔、機械鑽孔或類似製程等鑽孔製程形成螺栓孔156。可通過利用鑽孔製程鑽出螺栓孔156的輪廓且然後移除通過所述輪廓分隔開的材料來形成螺栓孔156。在一些實施例中,更早地(例如在形成圖32中的導電連接件之前)形成螺栓孔156。然而,可在製程的任何適合的步驟處形成螺栓孔156。
圖36示出根據一些實施例的晶圓上系統組件的剖視圖。晶圓上系統組件是通過將晶圓上系統400固定在熱模組200與機械支架300之間而形成。熱模組200可為散熱件、散熱器、冷板或類似物。機械支架300是可由例如金屬(例如,鋼、鈦、鈷或類似物)等具有高剛度的材料形成的剛性支撐件。機械支架300實體嚙合重佈線結構424的部分。通過將晶圓上系統400夾持在熱模組200與機械支架300之間,可減少例如由載體基底剝離引起的晶圓上系統400的翹曲。為易於模組安裝,機械支架300可為具有暴露出組件160及外部連接件170的開口的格柵。
將晶圓上系統400從膠帶142移除,且利用螺栓202緊固在熱模組200與機械支架300之間。將螺栓202擰過晶圓上系統100的螺栓孔156、擰過熱模組200中對應的螺栓孔且擰過機械支架300中對應的螺栓孔。將緊固件204擰到螺栓202上並擰緊,以將晶圓上系統100夾持在熱模組200與機械支架300之間。緊固件204可為例如擰到螺栓202的螺母。緊固件204在晶圓上系統組件的兩側處(例如,在具有熱模組200的一側(有時稱為後側)及具有機械支架300的一側(有時稱為前側)處)貼合到螺栓202。在被貼合之後,機械支架300的部分設置在組件160和/或外部連接件170之間。
在將各種組件緊固在一起之前,可在晶圓上系統400的後側上分配熱界面材料(TIM)208,從而將熱模組200實體耦合到且熱耦合到積體電路晶粒50。在一些實施例中,TIM 206由包含銦及HM03型材料的膜形成。在緊固期間,緊固件204被擰緊,從而增大由熱模組200及機械支架300施加到晶圓上系統400的機械力。緊固件204被擰緊,直到熱模組200在TIM 206上施予所期望量的壓力為止。
圖37示出根據一些實施例的晶圓上系統500。晶圓上系統500可相似於以上參照圖33闡述的晶圓上系統400,其中相同的參考編號指示使用相同的製程形成的相同的元件,但具有替代IC晶粒50A貼合到中介層402的底側且由包封體112包封並且貼合到重佈線結構424的頂部的光學連接件600(如下文參照圖39所述)。在一些實施例中,IC晶粒50A的功能與封裝450的功能被組合在如下文參照圖38闡述的封裝550中,封裝550被混合接合到中介層402。將I/O電路系統與SRAM電路系統一起放置在封裝550中可在SRAM與I/O電路系統之間提供最小距離,此可導致提高的系統效率。將光學連接件600貼合在晶圓上系統500的兩側上可使得能夠與外部裝置進行高頻寬連接。
圖38示出根據一些實施例的封裝550的剖視圖,封裝550可為如以上由圖37例示的晶圓上系統500的一部分。封裝550包括堆疊在封裝580上的IC晶粒590,且封裝580包括IC晶粒460及470。在一些實施例中,封裝580相似於以上參照圖22闡述的封裝450,其中相同的參考編號指示使用相同的製程形成的相同的元件。IC晶粒460可為記憶體晶粒(例如,動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒等)、電源管理晶粒(例如,電源管理積體電路(PMIC)晶粒),IC晶粒470可為邏輯晶粒(例如中央處理器(CPU)、圖形處理單元(GPU)、系統單晶片(SoC)、應用處理器(AP)、微控制器等),且IC晶粒590可為輸入/輸出(I/O)晶粒。在一些實施例中,IC晶粒460是SRAM晶粒,IC晶粒470是SoC晶粒,且IC晶粒590是I/O晶粒。
在一些實施例中,IC晶粒590具有與以上參照圖2闡述的IC晶粒50相似的結構及材料。IC晶粒590具有半導體基底592、位於半導體基底592之上的內連線結構594、實體耦合到且電耦合到內連線結構594的晶粒連接件596以及位於內連線結構594之上且在側向上包封晶粒連接件596的介電層598。IC晶粒590還可具有延伸穿過半導體基底592且對內連線結構594進行實體耦合及電耦合的基底穿孔(TSV)555。
可通過接合層458與介電層468之間以及導電焊盤456與晶粒連接件596之間的適合的接合方法(例如混合接合)來對封裝580與IC晶粒590進行接合。可以與如以上參照圖4闡述的IC晶粒50與中介層102之間的混合接合相似的方式來執行混合接合。
然後在TSV 555的頂表面之上形成導電焊盤556,且在半導體基底592之上在導電焊盤456之間形成接合層558。可使用與如以上參照圖3闡述的導電焊盤108及接合層110實質上相似的方法及材料來形成導電焊盤556及接合層558。然而,可使用任何適合的方法或材料。導電焊盤556及接合層558可使得包括IC晶粒460、470及590的封裝550能夠混合接合到例如如以上參照圖37闡述的中介層402。
圖39示出根據一些實施例的光學連接件600的實例的詳細圖。例如光學連接件600等光學連接件可替代外部連接件170積體到以上示出的晶圓上系統中的任一個中,例如積體在晶圓上系統500(參見上文,圖37)中或者積體在晶圓上系統100(參見上文,圖1)或晶圓上系統400(參見上文,圖21)中。光學連接件600包括光柵耦合器607A,光柵耦合器607A被配置成光學耦合到光纖650。光纖650可使用光學膠652或類似物裝設到光學連接件600。光纖650可相對於垂直軸線以一定角度進行裝設,或者可相對於光柵耦合器607A在側向上偏移。光柵耦合器607A可位於在光學連接件600的邊緣附近或遠離光學連接件600的邊緣的光子路由結構610中。在垂直裝設的光纖650與光柵耦合器607A之間傳輸的光信號和/或光功率經由介電層608、內連線結構620中的介電層615及形成在光柵耦合器607A之上的介電材料626進行傳輸。舉例來說,光信號可從光纖650傳輸到光柵耦合器607A並進入波導604中,其中光信號可由光電檢測器606A檢測且作為電信號經由導電特徵614傳輸到電子晶粒622中。由調製器606B在波導604內產生的光信號可相似地從光柵耦合器607A傳輸到垂直裝設的光纖650。導電焊盤628可實體耦合到且電耦合到晶圓上系統500(參見上文,圖37)中相應的導電焊盤508或導電連接件152。延伸穿過光子路由結構610且穿過基底602的通孔612對導電焊盤628與導電特徵614進行實體耦合及電耦合,以便對電子晶粒622與晶圓上系統500進行電連接。
各實施例可實現多種優點。晶圓上系統(SoW)組件可具有小的形狀因數,從而使得能夠實現緊湊的結構以表現出優越的電性能。積體被動裝置(IPD)(例如,電容器)或靜態隨機存取記憶體(SRAM)電路系統可嵌置到晶圓級中介層中。SoW結構中可包括具有從系統單晶片(SoC)晶粒到SRAM電路系統的短內連線的異構積體。對稱模製結構可減少小組件翹曲。嵌置式螺線管電感器可使得能夠實現對電壓調節器模組(VRM)的重佈線結構小型化。由於對晶圓級中介層及重佈線結構的晶圓級圖案化,與傳統的印刷電路板(PCB)系統相比,超大型微系統可具有高性能計算能力。可利用在單層中進行多遮罩曝光或圖像移位曝光來執行晶圓級圖案化。中介層及InFO封裝的精細重佈線層節距可提供晶粒到晶粒內連線之間的高頻寬。
根據一個實施例,一種半導體裝置包括:第一多個晶粒,由包封體包封;中介層,位於所述第一多個晶粒之上,所述中介層包括多個嵌置式被動組件,所述第一多個晶粒中的每一晶粒電連接到所述中介層;內連線結構,位於所述中介層之上且電連接到所述中介層,所述內連線結構包括位於所述內連線結構的金屬化層中的螺線管電感器;以及多個導電焊盤,位於所述內連線結構的與所述中介層相對的表面上。在實施例中,所述半導體裝置還包括由所述包封體包封的第一封裝,所述第一封裝電連接到所述中介層,所述第一封裝包括靜態隨機存取記憶體(SRAM)電路系統。在實施例中,所述SRAM電路系統位於所述第一封裝的第一晶粒中,且所述第一封裝的第二晶粒包括系統晶片。在實施例中,所述第一封裝的第三晶粒包括輸入/輸出裝置。在實施例中,第一組件貼合到所述多個導電焊盤中的導電焊盤,所述第一組件包括脈波寬度調變(PWM)控制器。在實施例中,所述第一組件電耦合到所述螺線管電感器,所述螺線管電感器是用於所述第一組件的電壓調節器模組。在實施例中,第一連接件貼合到所述多個導電焊盤中的導電焊盤。在實施例中,所述第一連接件是第一光學連接件。在實施例中,第二光學連接件電耦合到所述中介層的所述多個嵌置式被動組件中相應的嵌置式被動組件,所述第二光學連接件位於所述中介層的與所述第一光學連接件相對的一側上。在實施例中,所述第二光學連接件由所述包封體包封。
根據另一實施例,一種半導體裝置包括:第一模製化合物,圍繞第一晶粒及第二晶粒;中介層,位於所述第一晶粒、所述第二晶粒及所述第一模製化合物之上,所述中介層包括靜態隨機存取記憶體(SRAM)電路系統,所述第一晶粒及所述第二晶粒各自電耦合到所述中介層;導通孔,位於所述中介層上;第三晶粒,接合到且電耦合到所述中介層;第二模製化合物,圍繞所述導通孔及所述第三晶粒;內連線結構,位於所述導通孔、所述第三晶粒及所述第二模製化合物之上,所述內連線結構包括螺線管電感器;以及多個接觸焊盤,與所述導通孔、所述第三晶粒及所述第二模製化合物相對地位於所述內連線結構上。在實施例中,所述中介層是晶圓,所述晶圓包含矽。在實施例中,所述第三晶粒是積體被動裝置。在實施例中,所述第一晶粒利用金屬-金屬接合電耦合到所述中介層。
根據又一實施例,一種形成半導體裝置的方法包括:將第一多個晶粒接合到中介層,所述中介層包括多個導電特徵,所述第一多個晶粒中的每一晶粒接合到所述多個導電特徵中相應的導電特徵;利用包封體包封所述第一多個晶粒;在所述中介層的第一表面之上形成第一內連線,所述第一表面與所述第一多個晶粒相對;在所述第一內連線上與所述中介層相對地形成第一多個接觸焊盤;以及將第一裝置貼合到所述第一內連線,所述第一裝置電耦合到所述第一多個接觸焊盤中的接觸焊盤。形成所述第一內連線包括:形成所述第一內連線的底部部分;在所述第一內連線的所述底部部分上放置磁芯;以及在所述第一內連線的所述底部部分以及所述磁芯之上形成所述第一內連線的頂部部分,其中形成所述頂部部分會形成包括所述磁芯的螺線管電感器。在實施例中,將所述第一多個晶粒接合到所述中介層包括形成金屬-金屬接合及形成氧化物-氧化物接合。在實施例中,所述第一多個晶粒中的晶粒包括靜態隨機存取記憶體(SRAM)電路系統。在實施例中,所述中介層包括多個嵌置式被動組件。在實施例中,所述中介層包括靜態隨機存取記憶體(SRAM)電路系統。在實施例中,所述方法還包括:在所述中介層上形成導通孔;將積體被動裝置(IPD)晶粒接合到所述中介層;以及利用第二包封體包封所述導通孔及所述IPD晶粒。
以上概述了若干實施例的特徵,以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解,他們可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到,此種等效構造並不背離本公開的精神及範圍,而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
50, 50A, 50B, 50C, 470, 590:積體電路(IC)晶粒
52, 462, 472, 592:半導體基底
54, 464, 474, 594, 620:內連線結構
56, 466, 476, 596:晶粒連接件
58, 126, 130, 138, 414, 426, 430, 438, 442, 468, 478, 598, 608, 615:介電層
60:嵌置式SRAM電路系統組件
62, 72:鈍化層
66:載體基底
70:輸入/輸出(I/O)焊盤
100, 400:晶圓上晶片(CoW)結構
102, 402:中介層
104, 120, 404, 463, 555:基底穿孔(TSV)
106, 406, 614:導電特徵
108:導電焊盤
110, 116, 410, 458, 558:接合層
112, 122, 452:包封體
114, 408, 456, 556, 628:導電焊盤
118, 454:介電穿孔(TDV)
124, 424:重佈線結構/內連線結構
124A, 424A:底部部分
124B, 424B:頂部部分
128, 132, 140, 144, 416, 428, 432, 444:金屬化圖案
134, 434:磁晶片材
142:介電層/膠帶
146, 446:螺線管電感器/嵌置式螺線管電感器
148, 448:凸塊下金屬(UBM)
150:晶粒
152:導電連接件
154:底部填充膠
156:螺栓孔
160:組件
170:外部連接件
200:熱模組
202:螺栓
204:緊固件
208:熱界面材料(TIM)
300:機械支架
450, 550, 580:封裝
460:晶粒
500:晶圓上系統
600:光學連接件
604:波導
606A:光電檢測器
606B:調製器
607A:光柵耦合器
610:光子路由結構
612:通孔
622:電子晶粒
626:介電材料
650:光纖
652:光學膠
結合附圖閱讀以下詳細說明,會最好地理解本公開的各個方面。應注意,根據工業中的標準慣例,各種特徵並非按比例繪製。事實上,為論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1示出根據一些實施例的晶圓上系統(system-on-wafer,SoW)的剖視圖。
圖2示出根據一些實施例的積體電路晶粒的剖視圖。
圖3到圖19示出根據一些實施例在用於形成晶圓上系統的製程期間的中間步驟的剖視圖。
圖20示出根據一些實施例的晶圓上系統組件的剖視圖。
圖21示出根據一些實施例的另一晶圓上系統的剖視圖。
圖22示出根據一些實施例的封裝的剖視圖。
圖23到圖35示出根據一些實施例在用於形成晶圓上系統的製程期間的中間步驟的剖視圖。
圖36示出根據一些實施例的另一晶圓上系統組件的剖視圖。
圖37示出根據一些實施例的另一晶圓上系統的剖視圖。
圖38示出根據一些實施例的另一封裝的剖視圖。
圖39示出根據一些實施例的光學連接件的剖視圖。
50A,50B,50C:積體電路(IC)晶粒
54:內連線結構
56:晶粒連接件
58:介電層
100:晶圓上晶片(CoW)結構
102:中介層
104:基底穿孔(TSV)
108:導電焊盤
110:接合層
112,122:包封體
114:導電焊盤
118:介電穿孔(TDV)
124:重佈線結構/內連線結構
142:介電層/膠帶
146:螺線管電感器/嵌置式螺線管電感器
148:凸塊下金屬(UBM)
150:晶粒
152:導電連接件
154:底部填充膠
160:組件
170:外部連接件
Claims (1)
- 一種半導體裝置,包括: 第一多個晶粒,由包封體包封; 中介層,位於所述第一多個晶粒之上,所述中介層包括多個嵌置式被動組件,所述第一多個晶粒中的每一晶粒電連接到所述中介層; 內連線結構,位於所述中介層之上且電連接到所述中介層,所述內連線結構包括位於所述內連線結構的金屬化層中的螺線管電感器;以及 多個導電焊盤,位於所述內連線結構的與所述中介層相對的表面上。
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US17/241,715 | 2021-04-27 | ||
US17/241,715 US11764171B2 (en) | 2021-04-27 | 2021-04-27 | Integrated circuit structure and method |
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CN (1) | CN114937663A (zh) |
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US11227812B2 (en) * | 2019-08-28 | 2022-01-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package and manufacturing method thereof |
US20220367310A1 (en) * | 2021-05-13 | 2022-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package system and manufacturing method thereof |
US11715731B2 (en) * | 2021-08-29 | 2023-08-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of forming the same |
US20230215810A1 (en) * | 2021-12-30 | 2023-07-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200525869A (en) * | 2004-01-28 | 2005-08-01 | Renesas Tech Corp | Switching power supply and semiconductor IC |
JP2008117864A (ja) * | 2006-11-01 | 2008-05-22 | Nec Electronics Corp | 半導体装置 |
US8797057B2 (en) | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
US9443783B2 (en) | 2012-06-27 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC stacking device and method of manufacture |
US9299649B2 (en) | 2013-02-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US8993380B2 (en) | 2013-03-08 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for 3D IC package |
US9281254B2 (en) | 2014-02-13 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuit package |
US9693461B2 (en) * | 2014-04-16 | 2017-06-27 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Magnetic-core three-dimensional (3D) inductors and packaging integration |
US9425126B2 (en) | 2014-05-29 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy structure for chip-on-wafer-on-substrate |
US9496189B2 (en) | 2014-06-13 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor devices and methods of forming same |
US9263373B2 (en) * | 2014-06-18 | 2016-02-16 | Dyi-chung Hu | Thin film RDL for nanochip package |
US9612401B2 (en) * | 2015-02-18 | 2017-04-04 | Ciena Corporation | Method and system for providing optical connections |
US9461018B1 (en) | 2015-04-17 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out PoP structure with inconsecutive polymer layer |
US9666502B2 (en) | 2015-04-17 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Discrete polymer in fan-out packages |
US9559081B1 (en) * | 2015-08-21 | 2017-01-31 | Apple Inc. | Independent 3D stacking |
US10321575B2 (en) * | 2015-09-01 | 2019-06-11 | Qualcomm Incorporated | Integrated circuit (IC) module comprising an integrated circuit (IC) package and an interposer with embedded passive components |
US9735131B2 (en) | 2015-11-10 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-stack package-on-package structures |
US10236245B2 (en) * | 2016-03-23 | 2019-03-19 | Dyi-chung Hu | Package substrate with embedded circuit |
US11581237B2 (en) * | 2018-06-19 | 2023-02-14 | Intel Corporation | Cooling apparatuses for microelectronic assemblies |
US11515291B2 (en) * | 2018-08-28 | 2022-11-29 | Adeia Semiconductor Inc. | Integrated voltage regulator and passive components |
US10867879B2 (en) | 2018-09-28 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
EP3864696A4 (en) * | 2018-10-26 | 2021-12-08 | Huawei Technologies Co., Ltd. | DESIGN FOR EMBEDDED THIN FILM MAGNETIC INDUCER FOR APPLICATIONS WITH INTEGRATED VOLTAGE REGULATOR (IVR) |
US10971485B2 (en) * | 2018-10-31 | 2021-04-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Solenoid inductors within a multi-chip package |
KR102596759B1 (ko) * | 2019-03-18 | 2023-11-02 | 삼성전자주식회사 | 반도체 패키지 |
US11296062B2 (en) * | 2019-06-25 | 2022-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimension large system integration |
JP7268544B2 (ja) | 2019-08-30 | 2023-05-08 | 富士通株式会社 | 電気チップ及び光モジュール |
US11715728B2 (en) | 2019-09-19 | 2023-08-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Photonic semiconductor device and method of manufacture |
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US20220344287A1 (en) | 2022-10-27 |
CN114937663A (zh) | 2022-08-23 |
US11764171B2 (en) | 2023-09-19 |
US20230369254A1 (en) | 2023-11-16 |
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