CN1853271A - 用于双衬底封装的方法和装置 - Google Patents

用于双衬底封装的方法和装置 Download PDF

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Publication number
CN1853271A
CN1853271A CNA2004800271421A CN200480027142A CN1853271A CN 1853271 A CN1853271 A CN 1853271A CN A2004800271421 A CNA2004800271421 A CN A2004800271421A CN 200480027142 A CN200480027142 A CN 200480027142A CN 1853271 A CN1853271 A CN 1853271A
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substrate
semiconductor element
package substrate
interconnection
channel
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CNA2004800271421A
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CN100459111C (zh
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C·鲁马
K·辛格
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Intel Corp
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Intel Corp
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Abstract

揭示了具有在其内部形成的直通通道的半导体管芯。第一导电层在所述管芯的正面形成而耦合至所述直通通道的第二导电层在所述管芯的背面形成。第一封装衬底电气耦合至所述第一导电层，而第二封装衬底电气耦合至所述第二导电层。在另一个实施例中，衬底球电气耦合至所述第一和第二封装衬底。在又一个实施例中，倒转凸起可附在所述第二封装衬底上。

Description

用于双衬底封装的方法和装置
技术领域
本发明大致涉及半导体封装，尤其涉及传输至半导体管芯的功率和信号。
背景技术
集成电路(IC)，尤其是微处理器正在变得越来越复杂。由于变得越来越复杂，所以微处理器也要求更多的功率。微处理器还要求额外的信号输入以促进其日益增加的处理能力。半导体封装使用封装衬底将来自电源的功率以及来自封装外部的信号传递给半导体管芯。封装衬底连接至该半导体管芯以增加信号输入和输出该半导体管芯的配线区。当前连接半导体衬底和半导体管芯的两种方法包括引线键合成型阵列封装(WB-MMAP)和倒装芯片成型阵列封装(FC-MMAP)。
图1示出了一种使用引线键合成型的阵列封装(WB-MMAP)耦合至封装衬底的半导体管芯。封装10包括安装在封装衬底14上的半导体管芯12，诸如微处理器、芯片组、存储器设备、专用集成电路(ASIC)等等。半导体管芯12使用各种键合线16将信号发送至封装衬底14并从中获取信号。键合线16通常是铜或铝并且允许封装衬底14上焊盘和半导体管芯12侧面的器件之间的电气通信。封装10通过互连器件18连接至外部组件，所述互连器件可以是诸如焊料球和金属填充聚合体的球栅阵列(BGA)互连、诸如管脚的针栅阵列(PGA)互连以及诸如连接盘的网格栅阵列(LGA)互连等等。管芯12和键合线16可密封在诸如环氧树脂的成型材料20中以避免损坏。
图1B示出了一种倒装芯片成型阵列封装(FC-MMAP)。封装衬底30包括半导体管芯32和封装衬底34。半导体管芯32通过焊接凸起36与封装衬底24相连接，其中焊接凸起36可以是可控塌陷芯片连接(C4)或其他导电凸起。焊料凸起36可以在将半导体管芯32安装在封装衬底34之前，在半导体管芯32的有源侧或器件侧的焊盘上形成。C4凸起36是导电的，使得半导体管芯侧面的器件能够与封装衬底34通信。馈送至半导体管芯32和来自其的信号通过管芯封装34传输并且使用互连38馈送出所述封装。互连器件38可以是焊料球或金属填充聚合体，诸如BGA互连、PGA互连等等。管芯32被密封在诸如环氧树脂的模制材料40中以避免损坏。
图1C示出了典型的封装衬底。封装衬底50具有较大区域，用于分配来自管芯的信号，并为该管芯提供物理保护。封装衬底50包括若干通道52和平面54。通道52方便信号在衬底50内垂直传送，而平面54允许信号在衬底50内的水平传送。通道52能够连接键合线16或焊料凸起36。通道52的底部可以连接至互连18或38。图1D示出了封装衬底50的底视图。如图1D中可见，通道52的底部可分布在封装衬底50的整个表面上。典型的封装衬底50可以包括数千通道52。除了焊盘符合连接方法(引线键合或倒装芯片)且和管芯尺寸大小一致，封装衬底50的顶视图也是类似的。
新近的IC需要更高功率和更多信号互连，它已经耗尽了诸如上述封装衬底14、34和50的单个封装衬底的能力。因此，当使用单个封装衬底用于功率和信号分配时，这种单个封装衬底就会限制处理器的速度。此外，单个封装衬底内相对较小的有效导电表面所引起的增加电阻还会导致更高的工作温度。
附图说明
图1A示出了使用引线键合成型的阵列封装(WB-MMAP)耦合至封装衬底的半导体管芯。
图1B示出了倒装芯片成型的阵列封装(FC-MMAP)。
图1C示出了一种典型的封装衬底。
图1D示出了一种封装衬底的底视图。
图2A示出了根据一个实施例的双衬底半导体封装。
图2B示出了该封装的俯视图。
图3示出了形成双衬底半导体封装的过程。
图4A示出了经处理的具有有源器件侧面的半导体晶片。
图4B示出了已被薄化的晶片。
图4C示出了在其中形成有直通通道的晶片。
图4D示出了具有导电凸起的晶片。
图4E示出了被切割成若干半导体管芯的晶片。
图4F示出了分布在封装衬底上的底层填料材料。
图4G示出了附在封装衬底上的半导体管芯。
图4H示出了具有印制在其背面的倒装芯片凸起的半导体管芯。
图4I示出了在正面衬底上具有焊料球的半导体封装。
图4J示出了其上分布有底层填料材料的半导体管芯。
图4K示出了具有附加背面衬底的半导体封装。
图4L示出了具有附加BGA球衬底的半导体封装。
图4M示出了完成的封装组件。
具体实施方式
在此描述了用于双衬底半导体封装设计的方法和装置。在随后的描述中将阐明大量的细节。然而本领域普通技术人员显而易见就算没有这些细节也能够实现本发明。例如，已知的等效材料可代替在此描述的材料，而且也可类似地使用已知的等效技术来代替在此揭示的具体半导体材料技术。在其他实例中，已知的组件和设备是以框图形式而非细节形式示出，从而避免淡化发明主题。
根据本发明的一个实施例，揭示了双衬底封装设计。第一封装衬底附在半导体管芯的背面，而第二封装衬底则附在该半导体管芯的正面。直通通道通入半导体管芯的背面，以便于在该管芯的有源正面和所述第一封装衬底之间形成连接。第二封装衬底附于耦合至管芯正面内有源元件的焊盘。第一和第二封装衬底用衬底球相互耦合。
图2A示出了根据一个实施例的双衬底半导体封装。半导体封装100包括具有有源侧面104的半导体管芯102。半导体管芯102可由单晶硅或其他半导体衬底形成。有源侧面104包括执行IC操作的半导体器件。使用各种已知的半导体处理技术来形成有源(或器件)侧面104。有源侧面104通常小于10微米(μm)深。有源侧面104可以包括在中央处理单元(CPU)、芯片组、存储器设备、专用集成电路(ASIC)等等内所使用的诸如晶体管、电容等的任何电路。有源侧面104还包括金属化，诸如，与在其表面上形成的键合焊盘耦合以创建外部连接的互连。
半导体管芯102具有其中形成若干直通通道108的背面106。直通通道108允许管芯102的背面与管芯104的有源器件侧面的电气连接。直通通道108可以通过首先薄化管芯102而形成。半导体管芯102通常要求700到800μm的厚度以方便创建所述有源侧面104的处理步骤。为了创建通过管芯104的背面与该管芯有源侧面的连接，就应使用后研磨、旋转蚀刻、化学机械抛光(CMP)等工艺来薄化所述管芯至约75-175μm的厚度。一旦管芯102被薄化之后，就可使用任何已知的技术来形成直通通道108，诸如使用电镀技术之后的深度反应离子蚀刻(RIE)来使用诸如铜的导电材料填充钻孔。
互连器件110耦合至直通通道108以创建与背面封装衬底112的电气连接。添加背面封装衬底112以增加传递给管芯102的功率以及将信号传入并传出管芯102的有效导电线路的数量。同样也在封装衬底102的器件侧面104上形成互连器件114以允许在半导体管芯102的器件侧面104和所述正面封装衬底116之间的连接。互连器件110和114可以是诸如可控塌陷芯片连接(C4)或其他互连的倒装芯片焊料凸起。可以使用丝网印刷、电镀、柱状球焊(stud bumping)或其他已知的技术来形成互连器件110和114。
底层填料层118和120为互连110和114提供绝缘和保护。底层填料层118和120还在封装衬底112和116与半导体管芯102之间创建粘结。衬底球112允许背面封装衬底112和前面封装衬底116之间的通信。衬底球122围绕着封装衬底112和116，并且允许两者间的通信。这在图2B中示出。图2B示出了封装100的俯视图。示出的封装100是移除了背面衬底112的。由图可见，衬底球122围绕着封装衬底116的边缘并且耦合至封装衬底116的焊盘。
图3示出了形成双衬底半导体封装的过程。图4A到4M示出了图3所描述的过程。过程200在起始框202处开始。在框204内提供半导体晶片。图4A示出了具有有源器件侧面304和背面306的经处理后的半导体晶片302。器件侧面304包含有包括了晶体管、电阻等的半导体器件以创建用于CPU、芯片组、ASIC、存储器等等的电路。使用已知的技术和工艺来形成器件侧面304。背侧306不包含任何有源元件，因此可以被修改而不影响IC的功能。在一个实施例中，晶片302具有在700到800μm之间的原始厚度以方便晶片的处理。
在框206中，薄化晶片302以方便直通通道。图4B示出了已被薄化的晶片302。可以使用后研磨、旋转蚀刻、CMP等过程来薄化晶片302的背面306。因为微处理器或其他IC的所有有源元件都包含在器件侧面304之内，所以就可薄化晶片302的背面306而不影响IC的功能。在一个实施例中，将晶片302接地以使得晶片302的器件侧面304更接近晶片302的背面306以方便所述直通通道。在一个实施例中，晶片302可薄化至75-175μm的厚度。
在框208中，钻孔并金属化直通通道。图4C示出了在其中具有直通通道308的晶片302。所述直通通道308提供了背面306和有源或器件侧面304之间的电气连接。可以使用反应离子蚀刻(RIE)或其他合适的过程来形成直通通道308。通过首先掩模并在随后钻通晶片302的背面以提供连接有源层304内半导体器件的通道来形成直通通道308。该通道可以连接有源侧面304中的第一金属层。在另一个实施例中，该通道可以连接所述管芯的有源侧面的表面。一旦形成一钻孔以方便该直通通道308，就金属化该直通通道308以提供晶片302的背面306和器件侧面304之间的电气连接。可以使用诸如电镀、化学喷镀等喷镀技术来金属化该直通通道308。使用电镀工艺在所述钻孔中沉积诸如铜或铝的导电材料，从而形成直通通道308。
在框210中，使用倒装芯片焊盘以图案化晶片302的正面并将其隆起。图4D示出了具有导电凸起的晶片。在晶片302的有源侧面304上形成倒装芯片焊盘以方便对在正面304上所发现的半导体器件的电气连接。一旦形成了所述焊盘，就可在焊盘上形成互连或其他导电凸起310的图案。凸起310可以是导电的并且能够连接焊盘，即由此将所述半导体器件连接至所述半导体晶片302之外。可以使用丝网印刷、电镀、柱状球焊或其他已知的技术以使得凸起310沉积在倒装芯片焊盘上。凸起310可以是C4或其他倒装芯片凸起。
在框212内，所述晶片302被切割。图E示出了被切割成若干半导体管芯的晶片。晶片302可以被切割或分成若干独立的半导体管芯312。半导体管芯312包含单个集成电路或微处理器所需的半导体元件。晶片302通常含有几十个或者更多的半导体管芯312。为了形成独立的IC，使用晶片锯、激光等将较大的晶片302切换成或分割为管芯312。在分割后，就形成了若干半导体管芯312。
为了分布送入和来自半导体管芯的信号和功率，通常使用封装衬底。如上所述，封装衬底包括若干导电线路，并且能够将信号从凸起310分配至半导体管芯312之外。封装衬底可以将所述功率和信号传播到比半导体管芯312包围区域更大的区域。在框214内，在正面衬底上分布底层填料材料。图4F示出了分布到封装衬底上的底层填料材料。所述正面封装衬底314可以分布送入和来自半导体管芯312的正面或有源侧面304的功率和信号。诸如环氧树脂的底层填料材料316可以分布到封装衬底上。底层填料材料316能够将半导体管芯312粘合至封装衬底314并且电气绝缘凸起310以为其提供保护。底层填料材料316还可以保护凸起310不受管芯312和凸起310的不同的热膨胀系数(CTE)的影响。在一个实施例中，底层填料材料316是在附加管芯312之前沉积在衬底314上的不流动底层填料材料316。在可选实施例中，可以在管芯312附在衬底314上之后沉积毛细管或其他底层填料材料。然而在一个实施例中，使用不流动底层填料材料具有优势是因为它比毛细管底层填料更容易分布。应该理解也可使用其他类型的底层填料。
在框216中，使用倒装芯片互连将正面衬底314附于管芯312的正面304。图4G示出了附在封装衬底314上的半导体管芯312。底层填料材料316粘合半导体管芯312和封装衬底314。凸起或互连310透过底层填料材料316直到它们接触到封装衬底314上的焊盘。使用已知的倒装芯片互连方法，可使用加热炉或其他技术加热互连310使之回流焊料或其他材料以创建与封装衬底314上焊盘的连接。在回流所述焊料之后，就冷却所述互连310并在半导体管芯312上的键合焊盘与封装衬底314之间形成连接以方便功率和信号的分布。
在框218中，将倒装芯片凸起印刷在管芯312的背面。图4H示出了具有印制在其背面306的倒装芯片凸起318的半导体管芯312。直通通道308提供与半导体管芯312的器件侧面304的电气连接。为了将直通通道连接到半导体管芯312之外，就在管芯312的背面上形成诸如倒装芯片凸起318的互连的图案。倒装芯片凸起318电气耦合至直通通道308。倒装芯片凸起318由此创建了从管芯312背面306到器件侧面304的电气连接。
在框220内，将衬底球放置在正面衬底314上。图4I示出了在正面衬底314上具有焊料球320的半导体封装。衬底球320提供正面衬底314和随后附加至该封装的背面衬底之间的电气连接。衬底球320的厚度约为225μm，虽然该厚度依赖于管芯312等的大小可以发生变化。衬底球320可以连接至正面衬底314内的焊盘，并且将会围绕着正面衬底314(参见图2B)。由此，送入和来自背面衬底的信号和功率就可传送给正面衬底314。在一个实施例中，只有正面衬底314可被电气耦合到封装300之外。因此，如果背面衬底没有连接至封装300外部，就能够附加衬底球320用于传送背面衬底和正面衬底314之间的信号。在一个实施例中，由图4I可见，衬底球320要充分大于凸起310和318。因此既使衬底球较少，但是因为它们较大所以它们可以传送更多的电流。在其他的实施例中，可以使用包括插入物和管脚/过孔附属的可选技术来耦合正面衬底314和背面衬底。
在框222中，将底层填料材料分布到管芯的背面上。图4J示出了其上分布有底层填料材料的半导体管芯。在一个实施例中，底层填料材料322是诸如环氧树脂的不流动底层填料材料。类似于底层填料材料316，底层填料材料322也提供机械支持、污染保护并改善封装的可靠性。在一个实施例中，不流动底层填料材料322在附加背面衬底之前就被部分在管芯312上。然而在其他实施例中，可以在附加了背面衬底之后分布毛细管或其他底层填料材料。
在一个可选实施例中，可将正面衬底314附在管芯312上而不使用底层填料316，并且可附加背面衬底324而不使用底层填料322。在附加了正面和背面封装衬底314和324之后，随后就可在正面314和背面324衬底之间强制使用模制材料以在单个步骤内底层填充两个衬底。
在框224中，将背面衬底放置在封装300上并且回流倒装芯片凸起318以形成背面互连。图4K示出了具有附加背面衬底324的半导体封装300。背面衬底324放置在封装组件300的顶部。背面衬底324分布送入和来自半导体管芯312的信号和功率。回流倒装芯片凸起318和焊料球320以创建背面衬底324上的焊球与各自凸起318之间的连接。在炉中回流衬底球320和倒装芯片凸起310与318以加热金属并使其键合封装衬底314和324上的焊盘。通过附加背面衬底324就形成了双衬底封装。
在框226中，倒转该组件并附加球栅阵列(BGA)球用于板级互连。图4L示出了具有附加BGA球326衬底的反向半导体封装。为了允许管芯300与封装300外的器件通信，就必须建立与封装衬底314的电气连接。BGA球326可以附加至正面衬底314的底面。可使用丝网印刷机、球枪等等来施加BGA球。诸如图1D所示，BGA球326附至在前面板衬底314的底面上形成的焊盘。在一个实施例中，封装组件300必须在附加BGA球326之前被施加。封装元件的组件通常出现自封装300的顶部。因为正面衬底314是在封装的底面，所以为了附加BGA球326，就必须翻转封装衬底314。一旦翻转了封装组件300，就可如上所述附加BGA球326。应该理解也可以使用诸如针栅阵列(PGA)、网格栅阵列(LGA)等的其他已知的互连技术。
过程200在终止框228结束。图4M示出了完成封装组件300。一旦附加了BGA球326，就完成了封装组件并且可以结束该封装过程以提供运转的IC或微处理器。
本领域普通技术人员应该认识到可对在此描述的实施例做出若干变化而不背离本发明的广义精神。例如BGA互连326可以安装在背面衬底324而非正面衬底314上。同样地，也可使用其他的技术、过程和材料。
在此参考了其中的具体典型实施例描述了本发明。但对从本揭示中获益的人来说显而易见的是，可以做出各种修改和变化而不背离本发明的广义精神和范围。因此应该认为本说明书和附图是出于示例性而非限制性的意义。

Claims (21)

1.一种装置，包括：
具有其中形成直通通道的半导体管芯；
在所述管芯的正面形成的第一互连以及耦合至所述直通通道的所述管芯背面上形成的第二互连；以及
电气耦合至所述第一互连的第一封装衬底以及电气耦合至所述第二互连的第二封装衬底。
2.如权利要求1所述的装置，其特征在于，还包括在所述管芯的正面和所述第一衬底之间的第一底层填料层以及在所述管芯的背面和所述第二衬底之间的第二底层填料层。
3.如权利要求1所述的装置，其特征在于，还包括在所述第一和第二衬底之间电气耦合的衬底球。
4.如权利要求1所述的装置，其特征在于，所述第一和第二互连包括焊料球。
5.如权利要求1所述的装置，其特征在于，所述半导体管芯从后研磨工艺、化学机械抛光(CMP)工艺和旋转蚀刻工艺中选择一种工艺进行薄化。
6.如权利要求2所述的装置，其特征在于，所述底层填料层包括不流动底层填料材料。
7.如权利要求1所述的装置，其特征在于，所述管芯的正面包括所述管芯的有源侧面。
8.如权利要求1所述的装置，其特征在于，所述衬底是将分配信号送入和送出所述半导体管芯的封装衬底。
9.如权利要求8所述的装置，其特征在于，信号包括输入/输出(I/O)信号和功率信号。
10.一种方法，包括：
在半导体管芯的背面内形成直通通道并将第一互连附于所述直通通道；
将第二互连附于所述管芯的器件侧面；
将所述第一互连电气耦合至第一衬底；以及
将所述第二互连电气耦合至第二衬底。
11.如权利要求10所述的方法，其特征在于，所述直通通道连接所述器件侧面。
12.如权利要求10所述的方法，其特征在于，还包括：
在所述第一封装衬底上分布第一底层填料层；以及
在所述半导体管芯的背面上分布第二底层填料层。
13.如权利要求12所述的方法，其特征在于，还包括：
在所述第一和第二封装衬底之间附上衬底球。
14.如权利要求10所述的方法，其特征在于，所述第一和第二互连包括焊料球。
15.如权利要求10所述的方法，其特征在于，还包括薄化所述半导体管芯。
16.如权利要求10所述的方法，其特征在于，所述第一和第二底层填料层包括不流动底层填料。
17.如权利要求10所述的方法，其特征在于，所述第一和第二衬底包括将信号分配给所述半导体管芯的第一和第二封装衬底。
18.一种装置。包括：
具有在所述管芯背面内所形成的直通通道的半导体管芯，所述直通通道提供到所述管芯器件侧面的路径；
耦合至所述直通通道的第一焊料球以及耦合至所述器件侧面的第二焊料球；
电气耦合至所述第一焊料球的第一封装衬底，用以将信号分配至所述直通通道和所述管芯的背面；以及
电气耦合至所述第二焊料球的第二封装衬底，用以将信号分配至所述管芯的器件侧面。
19.如权利要求18所述的装置，其特征在于，所述半导体管芯被薄化以形成所述直通通道。
20.如权利要求18所述的装置，其特征在于，所述第一和第二焊料球是受控塌陷芯片连接(C4)附件。
21.如权利要求18所述的装置，其特征在于，还包括电气耦合所述第一和第二封装衬底的衬底球。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543967A (zh) * 2010-12-21 2012-07-04 三星电机株式会社 封装及该封装的制造方法
CN107924899A (zh) * 2015-08-27 2018-04-17 英特尔公司 多管芯封装

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7122906B2 (en) * 2004-01-29 2006-10-17 Micron Technology, Inc. Die-wafer package and method of fabricating same
DE102004037826B4 (de) * 2004-08-04 2006-06-14 Infineon Technologies Ag Halbleitervorrichtung mit miteinander verbundenen Halbleiterbauelementen
JP4478049B2 (ja) * 2005-03-15 2010-06-09 三菱電機株式会社 半導体装置
US20070202680A1 (en) * 2006-02-28 2007-08-30 Aminuddin Ismail Semiconductor packaging method
TWI341000B (en) * 2007-03-01 2011-04-21 Touch Micro System Tech Method of fabricating optical device caps
US7579215B2 (en) * 2007-03-30 2009-08-25 Motorola, Inc. Method for fabricating a low cost integrated circuit (IC) package
US8421244B2 (en) 2007-05-08 2013-04-16 Samsung Electronics Co., Ltd. Semiconductor package and method of forming the same
US7767486B2 (en) * 2007-11-21 2010-08-03 Intel Corporation High-volume on-wafer heterogeneous packaging of optical interconnects
US8310051B2 (en) 2008-05-27 2012-11-13 Mediatek Inc. Package-on-package with fan-out WLCSP
US8803330B2 (en) * 2008-09-27 2014-08-12 Stats Chippac Ltd. Integrated circuit package system with mounting structure
US20100237481A1 (en) * 2009-03-20 2010-09-23 Chi Heejo Integrated circuit packaging system with dual sided connection and method of manufacture thereof
US8097489B2 (en) * 2009-03-23 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of mounting pre-fabricated shielding frame over semiconductor die
US20100314149A1 (en) * 2009-06-10 2010-12-16 Medtronic, Inc. Hermetically-sealed electrical circuit apparatus
US8172760B2 (en) 2009-06-18 2012-05-08 Medtronic, Inc. Medical device encapsulated within bonded dies
US9324672B2 (en) * 2009-08-21 2016-04-26 Stats Chippac, Ltd. Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip scale package
US8508954B2 (en) 2009-12-17 2013-08-13 Samsung Electronics Co., Ltd. Systems employing a stacked semiconductor package
KR20110088234A (ko) 2010-01-28 2011-08-03 삼성전자주식회사 적층 반도체 패키지의 제조 방법
TWI419302B (zh) * 2010-02-11 2013-12-11 Advanced Semiconductor Eng 封裝製程
US8080445B1 (en) 2010-09-07 2011-12-20 Stats Chippac, Ltd. Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers
US8666505B2 (en) 2010-10-26 2014-03-04 Medtronic, Inc. Wafer-scale package including power source
JP5927756B2 (ja) * 2010-12-17 2016-06-01 ソニー株式会社 半導体装置及び半導体装置の製造方法
TWI445155B (zh) * 2011-01-06 2014-07-11 Advanced Semiconductor Eng 堆疊式封裝結構及其製造方法
US8424388B2 (en) 2011-01-28 2013-04-23 Medtronic, Inc. Implantable capacitive pressure sensor apparatus and methods regarding same
WO2013001171A1 (en) * 2011-06-30 2013-01-03 Murata Electronics Oy A method of making a system-in-package device, and a system-in-package device
US9105552B2 (en) 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US8823180B2 (en) * 2011-12-28 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US8587132B2 (en) * 2012-02-21 2013-11-19 Broadcom Corporation Semiconductor package including an organic substrate and interposer having through-semiconductor vias
US9171790B2 (en) 2012-05-30 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US20150014852A1 (en) * 2013-07-12 2015-01-15 Yueli Liu Package assembly configurations for multiple dies and associated techniques
US9349709B2 (en) * 2013-12-04 2016-05-24 Infineon Technologies Ag Electronic component with sheet-like redistribution structure
US10038259B2 (en) * 2014-02-06 2018-07-31 Xilinx, Inc. Low insertion loss package pin structure and method
DE102017207329A1 (de) * 2017-05-02 2018-11-08 Siemens Aktiengesellschaft Elektronische Baugruppe mit einem zwischen zwei Substraten eingebauten Bauelement und Verfahren zu dessen Herstellung
US11735552B2 (en) * 2019-06-25 2023-08-22 Intel Corporation Microelectronic package with solder array thermal interface material (SA-TIM)
US11984377B2 (en) 2020-03-26 2024-05-14 Intel Corporation IC die and heat spreaders with solderable thermal interface structures for assemblies including solder array thermal interconnects

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5424245A (en) 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
KR100209782B1 (ko) * 1994-08-30 1999-07-15 가나이 쓰도무 반도체 장치
US5855821A (en) * 1995-12-22 1999-01-05 Johnson Matthey, Inc. Materials for semiconductor device assemblies
US5973396A (en) 1996-02-16 1999-10-26 Micron Technology, Inc. Surface mount IC using silicon vias in an area array format or same size as die array
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US6281042B1 (en) * 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6175160B1 (en) 1999-01-08 2001-01-16 Intel Corporation Flip-chip having an on-chip cache memory
US6429509B1 (en) 1999-05-03 2002-08-06 United Microelectronics Corporation Integrated circuit with improved interconnect structure and process for making same
US6624501B2 (en) 2001-01-26 2003-09-23 Fujitsu Limited Capacitor and semiconductor device
US6589180B2 (en) * 2001-06-20 2003-07-08 Bae Systems Information And Electronic Systems Integration, Inc Acoustical array with multilayer substrate integrated circuits
JP2003060153A (ja) * 2001-07-27 2003-02-28 Nokia Corp 半導体パッケージ
US6548376B2 (en) * 2001-08-30 2003-04-15 Micron Technology, Inc. Methods of thinning microelectronic workpieces
TW504819B (en) * 2001-12-04 2002-10-01 Advanced Semiconductor Eng Packaging process of ultra-thin flip chip electronic device
DE10161043B4 (de) 2001-12-12 2005-12-15 Infineon Technologies Ag Chipanordnung
US6765152B2 (en) * 2002-09-27 2004-07-20 International Business Machines Corporation Multichip module having chips on two sides

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543967A (zh) * 2010-12-21 2012-07-04 三星电机株式会社 封装及该封装的制造方法
CN107924899A (zh) * 2015-08-27 2018-04-17 英特尔公司 多管芯封装
CN107924899B (zh) * 2015-08-27 2023-05-02 英特尔公司 多管芯封装

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DE112004001678T5 (de) 2006-07-13
KR20060069502A (ko) 2006-06-21
US20050067714A1 (en) 2005-03-31
WO2005034203A2 (en) 2005-04-14
CN100459111C (zh) 2009-02-04
US7247517B2 (en) 2007-07-24
HK1093381A1 (en) 2007-03-02
WO2005034203A3 (en) 2005-10-27

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