WO2005034203A3 - Method and apparatus for a dual substrate package - Google Patents
Method and apparatus for a dual substrate package Download PDFInfo
- Publication number
- WO2005034203A3 WO2005034203A3 PCT/US2004/032451 US2004032451W WO2005034203A3 WO 2005034203 A3 WO2005034203 A3 WO 2005034203A3 US 2004032451 W US2004032451 W US 2004032451W WO 2005034203 A3 WO2005034203 A3 WO 2005034203A3
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- WO
- WIPO (PCT)
- Prior art keywords
- conductive layer
- die
- substrate package
- package substrate
- dual substrate
- Prior art date
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Dicing (AREA)
Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE112004001678T DE112004001678T5 (en) | 2003-09-30 | 2004-09-29 | Method and apparatus for a package with two substrates |
KR1020067006139A KR100886517B1 (en) | 2003-09-30 | 2004-09-29 | Method and apparatus for a dual substrate package |
HK07100011.8A HK1093381A1 (en) | 2003-09-30 | 2007-01-02 | Method and apparatus for a dual substrate package |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/676,883 US7247517B2 (en) | 2003-09-30 | 2003-09-30 | Method and apparatus for a dual substrate package |
US10/676,883 | 2003-09-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005034203A2 WO2005034203A2 (en) | 2005-04-14 |
WO2005034203A3 true WO2005034203A3 (en) | 2005-10-27 |
Family
ID=34377478
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/032451 WO2005034203A2 (en) | 2003-09-30 | 2004-09-29 | Method and apparatus for a dual substrate package |
Country Status (7)
Country | Link |
---|---|
US (1) | US7247517B2 (en) |
KR (1) | KR100886517B1 (en) |
CN (1) | CN100459111C (en) |
DE (1) | DE112004001678T5 (en) |
HK (1) | HK1093381A1 (en) |
TW (1) | TWI261885B (en) |
WO (1) | WO2005034203A2 (en) |
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US20070202680A1 (en) * | 2006-02-28 | 2007-08-30 | Aminuddin Ismail | Semiconductor packaging method |
TWI341000B (en) * | 2007-03-01 | 2011-04-21 | Touch Micro System Tech | Method of fabricating optical device caps |
US7579215B2 (en) * | 2007-03-30 | 2009-08-25 | Motorola, Inc. | Method for fabricating a low cost integrated circuit (IC) package |
US8421244B2 (en) * | 2007-05-08 | 2013-04-16 | Samsung Electronics Co., Ltd. | Semiconductor package and method of forming the same |
US7767486B2 (en) * | 2007-11-21 | 2010-08-03 | Intel Corporation | High-volume on-wafer heterogeneous packaging of optical interconnects |
US8310051B2 (en) | 2008-05-27 | 2012-11-13 | Mediatek Inc. | Package-on-package with fan-out WLCSP |
US8803330B2 (en) * | 2008-09-27 | 2014-08-12 | Stats Chippac Ltd. | Integrated circuit package system with mounting structure |
US20100237481A1 (en) * | 2009-03-20 | 2010-09-23 | Chi Heejo | Integrated circuit packaging system with dual sided connection and method of manufacture thereof |
US8097489B2 (en) * | 2009-03-23 | 2012-01-17 | Stats Chippac, Ltd. | Semiconductor device and method of mounting pre-fabricated shielding frame over semiconductor die |
US8072056B2 (en) | 2009-06-10 | 2011-12-06 | Medtronic, Inc. | Apparatus for restricting moisture ingress |
US8172760B2 (en) | 2009-06-18 | 2012-05-08 | Medtronic, Inc. | Medical device encapsulated within bonded dies |
US9324672B2 (en) * | 2009-08-21 | 2016-04-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip scale package |
US8508954B2 (en) | 2009-12-17 | 2013-08-13 | Samsung Electronics Co., Ltd. | Systems employing a stacked semiconductor package |
KR20110088234A (en) | 2010-01-28 | 2011-08-03 | 삼성전자주식회사 | Method for fabricating of stacked semiconductor package |
TWI419302B (en) * | 2010-02-11 | 2013-12-11 | Advanced Semiconductor Eng | Package process |
US8080445B1 (en) | 2010-09-07 | 2011-12-20 | Stats Chippac, Ltd. | Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers |
US8666505B2 (en) | 2010-10-26 | 2014-03-04 | Medtronic, Inc. | Wafer-scale package including power source |
JP5927756B2 (en) * | 2010-12-17 | 2016-06-01 | ソニー株式会社 | Semiconductor device and manufacturing method of semiconductor device |
KR101321170B1 (en) * | 2010-12-21 | 2013-10-23 | 삼성전기주식회사 | Package and Method for manufacturing the same |
TWI445155B (en) * | 2011-01-06 | 2014-07-11 | Advanced Semiconductor Eng | Stacked semiconductor package and method for making the same |
US8424388B2 (en) | 2011-01-28 | 2013-04-23 | Medtronic, Inc. | Implantable capacitive pressure sensor apparatus and methods regarding same |
CN103765579B (en) * | 2011-06-30 | 2017-10-31 | 村田电子有限公司 | The manufacture method and system in package device of system in package device |
US9105552B2 (en) | 2011-10-31 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US8823180B2 (en) * | 2011-12-28 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US8587132B2 (en) * | 2012-02-21 | 2013-11-19 | Broadcom Corporation | Semiconductor package including an organic substrate and interposer having through-semiconductor vias |
US9171790B2 (en) | 2012-05-30 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US20150014852A1 (en) * | 2013-07-12 | 2015-01-15 | Yueli Liu | Package assembly configurations for multiple dies and associated techniques |
US9349709B2 (en) * | 2013-12-04 | 2016-05-24 | Infineon Technologies Ag | Electronic component with sheet-like redistribution structure |
US10038259B2 (en) * | 2014-02-06 | 2018-07-31 | Xilinx, Inc. | Low insertion loss package pin structure and method |
WO2017034589A1 (en) * | 2015-08-27 | 2017-03-02 | Intel Corporation | Multi-die package |
DE102017207329A1 (en) * | 2017-05-02 | 2018-11-08 | Siemens Aktiengesellschaft | Electronic assembly with a built between two substrates component and method for its preparation |
US11735552B2 (en) * | 2019-06-25 | 2023-08-22 | Intel Corporation | Microelectronic package with solder array thermal interface material (SA-TIM) |
US11984377B2 (en) | 2020-03-26 | 2024-05-14 | Intel Corporation | IC die and heat spreaders with solderable thermal interface structures for assemblies including solder array thermal interconnects |
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WO2003050850A2 (en) * | 2001-12-12 | 2003-06-19 | Infineon Technologies Ag | Contacting of a semiconductor chip on a substrate using flip-chip-like technology |
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KR100209782B1 (en) * | 1994-08-30 | 1999-07-15 | 가나이 쓰도무 | Semiconductor device |
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-
2003
- 2003-09-30 US US10/676,883 patent/US7247517B2/en not_active Expired - Lifetime
-
2004
- 2004-09-29 WO PCT/US2004/032451 patent/WO2005034203A2/en active Application Filing
- 2004-09-29 CN CNB2004800271421A patent/CN100459111C/en not_active Expired - Fee Related
- 2004-09-29 TW TW093129469A patent/TWI261885B/en not_active IP Right Cessation
- 2004-09-29 DE DE112004001678T patent/DE112004001678T5/en not_active Ceased
- 2004-09-29 KR KR1020067006139A patent/KR100886517B1/en active IP Right Grant
-
2007
- 2007-01-02 HK HK07100011.8A patent/HK1093381A1/en not_active IP Right Cessation
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US5424245A (en) * | 1994-01-04 | 1995-06-13 | Motorola, Inc. | Method of forming vias through two-sided substrate |
US6168969B1 (en) * | 1996-02-16 | 2001-01-02 | Micron Technology, Inc. | Surface mount IC using silicon vias in an area array format or same size as die array |
US5977640A (en) * | 1998-06-26 | 1999-11-02 | International Business Machines Corporation | Highly integrated chip-on-chip packaging |
US6175160B1 (en) * | 1999-01-08 | 2001-01-16 | Intel Corporation | Flip-chip having an on-chip cache memory |
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EP1280203A2 (en) * | 2001-07-27 | 2003-01-29 | Nokia Corporation | 3D-Semiconductor Package |
WO2003050850A2 (en) * | 2001-12-12 | 2003-06-19 | Infineon Technologies Ag | Contacting of a semiconductor chip on a substrate using flip-chip-like technology |
Also Published As
Publication number | Publication date |
---|---|
TW200525664A (en) | 2005-08-01 |
US20050067714A1 (en) | 2005-03-31 |
TWI261885B (en) | 2006-09-11 |
KR20060069502A (en) | 2006-06-21 |
KR100886517B1 (en) | 2009-03-02 |
WO2005034203A2 (en) | 2005-04-14 |
DE112004001678T5 (en) | 2006-07-13 |
HK1093381A1 (en) | 2007-03-02 |
CN100459111C (en) | 2009-02-04 |
CN1853271A (en) | 2006-10-25 |
US7247517B2 (en) | 2007-07-24 |
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