WO2005034203A3 - Method and apparatus for a dual substrate package - Google Patents

Method and apparatus for a dual substrate package Download PDF

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Publication number
WO2005034203A3
WO2005034203A3 PCT/US2004/032451 US2004032451W WO2005034203A3 WO 2005034203 A3 WO2005034203 A3 WO 2005034203A3 US 2004032451 W US2004032451 W US 2004032451W WO 2005034203 A3 WO2005034203 A3 WO 2005034203A3
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Prior art keywords
conductive layer
apparatus
method
formed
die
Prior art date
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PCT/US2004/032451
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French (fr)
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WO2005034203A2 (en )
Inventor
Christopher Rumer
Kuljeet Singh
Original Assignee
Intel Corp
Christopher Rumer
Kuljeet Singh
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    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1433Application-specific integrated circuit [ASIC]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor

Abstract

A semiconductor die having a through via formed therein is disclosed. A first conductive layer is formed on the front side of the die and a second conductive layer is formed on the backside of the die, and coupled with the through via. A first package substrate is electrically coupled with the first conductive layer, and a second package substrate is electrically coupled with the second conductive layer. In another embodiment, a substrate ball electrically couples the first and second package substrates. In a further embodiment, a flip chip bump is attached to the first package substrate.
PCT/US2004/032451 2003-09-30 2004-09-29 Method and apparatus for a dual substrate package WO2005034203A3 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/676,883 2003-09-30
US10676883 US7247517B2 (en) 2003-09-30 2003-09-30 Method and apparatus for a dual substrate package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20067006139A KR100886517B1 (en) 2003-09-30 2004-09-29 Method and apparatus for a dual substrate package
DE200411001678 DE112004001678T5 (en) 2003-09-30 2004-09-29 Method and apparatus for a package with two substrates

Publications (2)

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WO2005034203A2 true WO2005034203A2 (en) 2005-04-14
WO2005034203A3 true true WO2005034203A3 (en) 2005-10-27

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US (1) US7247517B2 (en)
KR (1) KR100886517B1 (en)
CN (1) CN100459111C (en)
DE (1) DE112004001678T5 (en)
WO (1) WO2005034203A3 (en)

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Also Published As

Publication number Publication date Type
KR100886517B1 (en) 2009-03-02 grant
CN1853271A (en) 2006-10-25 application
DE112004001678T5 (en) 2006-07-13 application
KR20060069502A (en) 2006-06-21 application
CN100459111C (en) 2009-02-04 grant
WO2005034203A2 (en) 2005-04-14 application
US20050067714A1 (en) 2005-03-31 application
US7247517B2 (en) 2007-07-24 grant

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