HK1093381A1 - Method and apparatus for a dual substrate package - Google Patents
Method and apparatus for a dual substrate packageInfo
- Publication number
- HK1093381A1 HK1093381A1 HK07100011.8A HK07100011A HK1093381A1 HK 1093381 A1 HK1093381 A1 HK 1093381A1 HK 07100011 A HK07100011 A HK 07100011A HK 1093381 A1 HK1093381 A1 HK 1093381A1
- Authority
- HK
- Hong Kong
- Prior art keywords
- conductive layer
- die
- substrate package
- package substrate
- dual substrate
- Prior art date
Links
Classifications
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Dicing (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/676,883 US7247517B2 (en) | 2003-09-30 | 2003-09-30 | Method and apparatus for a dual substrate package |
PCT/US2004/032451 WO2005034203A2 (en) | 2003-09-30 | 2004-09-29 | Method and apparatus for a dual substrate package |
Publications (1)
Publication Number | Publication Date |
---|---|
HK1093381A1 true HK1093381A1 (en) | 2007-03-02 |
Family
ID=34377478
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
HK07100011.8A HK1093381A1 (en) | 2003-09-30 | 2007-01-02 | Method and apparatus for a dual substrate package |
Country Status (7)
Country | Link |
---|---|
US (1) | US7247517B2 (zh) |
KR (1) | KR100886517B1 (zh) |
CN (1) | CN100459111C (zh) |
DE (1) | DE112004001678T5 (zh) |
HK (1) | HK1093381A1 (zh) |
TW (1) | TWI261885B (zh) |
WO (1) | WO2005034203A2 (zh) |
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JP4478049B2 (ja) * | 2005-03-15 | 2010-06-09 | 三菱電機株式会社 | 半導体装置 |
US20070202680A1 (en) * | 2006-02-28 | 2007-08-30 | Aminuddin Ismail | Semiconductor packaging method |
TWI341000B (en) * | 2007-03-01 | 2011-04-21 | Touch Micro System Tech | Method of fabricating optical device caps |
US7579215B2 (en) * | 2007-03-30 | 2009-08-25 | Motorola, Inc. | Method for fabricating a low cost integrated circuit (IC) package |
US8421244B2 (en) | 2007-05-08 | 2013-04-16 | Samsung Electronics Co., Ltd. | Semiconductor package and method of forming the same |
US7767486B2 (en) * | 2007-11-21 | 2010-08-03 | Intel Corporation | High-volume on-wafer heterogeneous packaging of optical interconnects |
US8310051B2 (en) | 2008-05-27 | 2012-11-13 | Mediatek Inc. | Package-on-package with fan-out WLCSP |
US8803330B2 (en) * | 2008-09-27 | 2014-08-12 | Stats Chippac Ltd. | Integrated circuit package system with mounting structure |
US20100237481A1 (en) * | 2009-03-20 | 2010-09-23 | Chi Heejo | Integrated circuit packaging system with dual sided connection and method of manufacture thereof |
US8097489B2 (en) * | 2009-03-23 | 2012-01-17 | Stats Chippac, Ltd. | Semiconductor device and method of mounting pre-fabricated shielding frame over semiconductor die |
US7902851B2 (en) * | 2009-06-10 | 2011-03-08 | Medtronic, Inc. | Hermeticity testing |
US8172760B2 (en) | 2009-06-18 | 2012-05-08 | Medtronic, Inc. | Medical device encapsulated within bonded dies |
US9324672B2 (en) * | 2009-08-21 | 2016-04-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip scale package |
US8508954B2 (en) | 2009-12-17 | 2013-08-13 | Samsung Electronics Co., Ltd. | Systems employing a stacked semiconductor package |
KR20110088234A (ko) | 2010-01-28 | 2011-08-03 | 삼성전자주식회사 | 적층 반도체 패키지의 제조 방법 |
TWI419302B (zh) * | 2010-02-11 | 2013-12-11 | Advanced Semiconductor Eng | 封裝製程 |
US8080445B1 (en) | 2010-09-07 | 2011-12-20 | Stats Chippac, Ltd. | Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers |
US8666505B2 (en) | 2010-10-26 | 2014-03-04 | Medtronic, Inc. | Wafer-scale package including power source |
JP5927756B2 (ja) * | 2010-12-17 | 2016-06-01 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法 |
KR101321170B1 (ko) * | 2010-12-21 | 2013-10-23 | 삼성전기주식회사 | 패키지 및 이의 제조 방법 |
TWI445155B (zh) * | 2011-01-06 | 2014-07-11 | Advanced Semiconductor Eng | 堆疊式封裝結構及其製造方法 |
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CN107720689A (zh) * | 2011-06-30 | 2018-02-23 | 村田电子有限公司 | 系统级封装器件的制造方法和系统级封装器件 |
US9105552B2 (en) | 2011-10-31 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US8823180B2 (en) * | 2011-12-28 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US8587132B2 (en) * | 2012-02-21 | 2013-11-19 | Broadcom Corporation | Semiconductor package including an organic substrate and interposer having through-semiconductor vias |
US9171790B2 (en) | 2012-05-30 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US20150014852A1 (en) * | 2013-07-12 | 2015-01-15 | Yueli Liu | Package assembly configurations for multiple dies and associated techniques |
US9349709B2 (en) * | 2013-12-04 | 2016-05-24 | Infineon Technologies Ag | Electronic component with sheet-like redistribution structure |
US10038259B2 (en) * | 2014-02-06 | 2018-07-31 | Xilinx, Inc. | Low insertion loss package pin structure and method |
US10304769B2 (en) * | 2015-08-27 | 2019-05-28 | Intel Corporation | Multi-die package |
DE102017207329A1 (de) * | 2017-05-02 | 2018-11-08 | Siemens Aktiengesellschaft | Elektronische Baugruppe mit einem zwischen zwei Substraten eingebauten Bauelement und Verfahren zu dessen Herstellung |
US11735552B2 (en) * | 2019-06-25 | 2023-08-22 | Intel Corporation | Microelectronic package with solder array thermal interface material (SA-TIM) |
US11984377B2 (en) | 2020-03-26 | 2024-05-14 | Intel Corporation | IC die and heat spreaders with solderable thermal interface structures for assemblies including solder array thermal interconnects |
CN117832099A (zh) * | 2024-01-05 | 2024-04-05 | 成都电科星拓科技有限公司 | 一种能够实现双面焊接的bga封装方法 |
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KR100209782B1 (ko) * | 1994-08-30 | 1999-07-15 | 가나이 쓰도무 | 반도체 장치 |
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JP2003060153A (ja) * | 2001-07-27 | 2003-02-28 | Nokia Corp | 半導体パッケージ |
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TW504819B (en) * | 2001-12-04 | 2002-10-01 | Advanced Semiconductor Eng | Packaging process of ultra-thin flip chip electronic device |
DE10161043B4 (de) | 2001-12-12 | 2005-12-15 | Infineon Technologies Ag | Chipanordnung |
US6765152B2 (en) * | 2002-09-27 | 2004-07-20 | International Business Machines Corporation | Multichip module having chips on two sides |
-
2003
- 2003-09-30 US US10/676,883 patent/US7247517B2/en not_active Expired - Lifetime
-
2004
- 2004-09-29 KR KR1020067006139A patent/KR100886517B1/ko active IP Right Grant
- 2004-09-29 DE DE112004001678T patent/DE112004001678T5/de not_active Ceased
- 2004-09-29 CN CNB2004800271421A patent/CN100459111C/zh not_active Expired - Fee Related
- 2004-09-29 WO PCT/US2004/032451 patent/WO2005034203A2/en active Application Filing
- 2004-09-29 TW TW093129469A patent/TWI261885B/zh not_active IP Right Cessation
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2007
- 2007-01-02 HK HK07100011.8A patent/HK1093381A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
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TWI261885B (en) | 2006-09-11 |
WO2005034203A2 (en) | 2005-04-14 |
KR100886517B1 (ko) | 2009-03-02 |
US20050067714A1 (en) | 2005-03-31 |
US7247517B2 (en) | 2007-07-24 |
TW200525664A (en) | 2005-08-01 |
CN1853271A (zh) | 2006-10-25 |
DE112004001678T5 (de) | 2006-07-13 |
WO2005034203A3 (en) | 2005-10-27 |
CN100459111C (zh) | 2009-02-04 |
KR20060069502A (ko) | 2006-06-21 |
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Legal Events
Date | Code | Title | Description |
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PC | Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee) |
Effective date: 20210928 |