TWI252490B - Memory module - Google Patents

Memory module Download PDF

Info

Publication number
TWI252490B
TWI252490B TW93124423A TW93124423A TWI252490B TW I252490 B TWI252490 B TW I252490B TW 93124423 A TW93124423 A TW 93124423A TW 93124423 A TW93124423 A TW 93124423A TW I252490 B TWI252490 B TW I252490B
Authority
TW
Taiwan
Prior art keywords
circuit board
buffer
memory
memory module
memory chips
Prior art date
Application number
TW93124423A
Other languages
English (en)
Chinese (zh)
Other versions
TW200519958A (en
Inventor
Byung-Se So
Jeong-Hyeob Cho
Jung-Joon Lee
Jae-Jun Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020030056012A external-priority patent/KR100585099B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200519958A publication Critical patent/TW200519958A/zh
Application granted granted Critical
Publication of TWI252490B publication Critical patent/TWI252490B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Combinations Of Printed Boards (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
TW93124423A 2003-08-13 2004-08-13 Memory module TWI252490B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030056012A KR100585099B1 (ko) 2003-08-13 2003-08-13 적층형 메모리 모듈 및 메모리 시스템.
US10/853,353 US7072201B2 (en) 2003-08-13 2004-05-26 Memory module

Publications (2)

Publication Number Publication Date
TW200519958A TW200519958A (en) 2005-06-16
TWI252490B true TWI252490B (en) 2006-04-01

Family

ID=34228056

Family Applications (1)

Application Number Title Priority Date Filing Date
TW93124423A TWI252490B (en) 2003-08-13 2004-08-13 Memory module

Country Status (4)

Country Link
JP (1) JP4695361B2 (de)
CN (1) CN100557699C (de)
DE (1) DE102004039806B4 (de)
TW (1) TWI252490B (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7405949B2 (en) 2005-12-09 2008-07-29 Samsung Electronics Co., Ltd. Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices
DE102006051514B4 (de) 2006-10-31 2010-01-21 Qimonda Ag Speichermodul und Verfahren zum Betreiben eines Speichermoduls
US7715200B2 (en) 2007-09-28 2010-05-11 Samsung Electronics Co., Ltd. Stacked semiconductor module, method of fabricating the same, and electronic system using the same
CN103809674B (zh) * 2012-11-11 2017-06-23 北京忆恒创源科技有限公司 存储设备

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999000734A1 (fr) * 1997-06-27 1999-01-07 Hitachi, Ltd. Module memoire et systeme de traitement de donnees
US5949657A (en) * 1997-12-01 1999-09-07 Karabatsos; Chris Bottom or top jumpered foldable electronic assembly
US6222739B1 (en) * 1998-01-20 2001-04-24 Viking Components High-density computer module with stacked parallel-plane packaging
US6487102B1 (en) * 2000-09-18 2002-11-26 Intel Corporation Memory module having buffer for isolating stacked memory devices
US6553450B1 (en) * 2000-09-18 2003-04-22 Intel Corporation Buffer to multiply memory interface
US6877079B2 (en) * 2001-03-06 2005-04-05 Samsung Electronics Co., Ltd. Memory system having point-to-point bus configuration
JP4094370B2 (ja) * 2002-07-31 2008-06-04 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム

Also Published As

Publication number Publication date
JP2005063448A (ja) 2005-03-10
TW200519958A (en) 2005-06-16
DE102004039806B4 (de) 2009-05-07
JP4695361B2 (ja) 2011-06-08
CN100557699C (zh) 2009-11-04
DE102004039806A1 (de) 2005-03-31
CN1604227A (zh) 2005-04-06

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees