TW558807B - Low profile, high density memory system - Google Patents

Abstract

The present invention provides a low profile, high density electronic package for high speed, high performance semiconductors, such as memory devices. It includes a plurality of modules having high speed, impedance-controlled transmission line buses, short interconnections between modules and, optionally, driver line terminators built into one of the modules, for maintaining high electrical performance. Suitable applications include microprocessor data buses and memory buses such as RAMBUS and DDR. The modules may be formed on conventional printed circuit cards with unpacked or packed memory chips attached directly to the memory module. Thermal control structures may be included to maintain the high density modules within a reliable range of operating temperatures.

Description

558807 V. Description of the invention (1) [Related patent applications] This invention patent application is related to the US Patent No. 6, 1 7 2, 8 9 5 filed by Brown et al. High-Speed Memory Modules for Terminals ", and US Patent Application No. 09/457, 776 under joint application on December 9, 1999, and US Patent Application No. 09 / under joint application on December 14, 1999 461,065; U.S. Patent Application Nos. 0 9 / 645,860, 09 / 645,859, 60/227, 689, and 09 / 645,858, co-filed on August 24, 2000; U.S. issued to Li et al. Patent No. 6, 264, 4 76, "Inserts for the Foundation of Metal Wire Segments for High Frequency Electrical Connections", this patent is a US patent application filed on February 9, 1999 09/457, 776-based; issued to Fan et al., US Pat. No. 6, 3 1 2, 266, "Carriers for Arrays of Bearing Grids", which was filed on August 24, 2000 Based on U.S. Patent Application No. 09/645, 86; and U.S. Patent Application No. 09/46 1,0 65 in joint application on December 14, 1999; August 24, 2000 U.S. Patent Application No. 0 9/46 1, 06 5 and 09/645, 8 58 in the Japanese joint application; U.S. Patent Application No. 09/866, 434 in the joint application on May 29, 2001, This patent is a non-tentative application based on US Patent Application No. 09/461, 065 tentatively dated August 24, 2000; the United States of America filed January 31, 2001 The patent application number 09/772, 64 丨 and the above patent applications are designated as the patent documents of the present invention. [Scope of the invention] The present invention relates to a high-density, low-thickness electronic package, especially a high-performance '胄 density memory Body module has impedance control transmission line

Page 5 558807

The Momo group maintains high-density, low-thickness packages that maintain high electrical busbars and optionally built-in driveline terminal performance. [Background of the Invention] < Nowadays, the trend of providing high electrical efficiency, high density production, and no beta sub-package for high-speed, high-performance electronic systems: interconnection, has been opened f: High-reliability interconnection between circuit devices has been formed Attack some important parts of the system. The system may be a brain-communication network device, a head-mounted "personal digital assistant" that includes a plurality of interconnected high-reliability modules, = misconnection (following ctiQns) is the cause of terminal production; failure J causes. Modules, especially the interconnects, are as dense as possible, using the least number of modules to take up space, providing high electrical integrity, and providing minimal collisions on the module wiring and matching the motherboard or system board. In situations such as laptops and head-mounted devices, the lower the height of the connectors and attached circuit components, the better. It is important that the density and performance of the system increase dramatically, so the specifications for the interconnection It is urgent. A method of high electrical execution efficiency is clear = Immediately improve signal integrity (integr 丨 ty). This can be shielded by βHynet interconnect to help them more closely match the impedance required by the system Achieved. Especially when coupled with field-separability 'these demanding requirements have led to significant changes in possible connector solutions. In addition, ensure effectiveness Repair, upgrade, and / or different parts of the system

558807 V. Description of the invention (3), etc.) ^ Replacement (for example, connector, card, chip, board, module 4 requires that the connection in the module is reworkable in the factory. In some cases There is also a high demand. For example, a land grid array (LGA) is needed for the convenience of testing during production. For example, the two connected grids are parallel. Each of the circuit components has a plurality of contact points arranged in a linear or two-dimensional array. An array of interconnecting components, called interposers, is placed between two arrays that are connected, And provide electrical connections between contact points or contact pads. In order to achieve higher density interconnection and save the actual space of the motherboard, additional parallel circuit components may be stacked and electrically connected by the addition of LGA connectors to create three-dimensional In any case, because pin-and-socket type interconnects do not have the ability to hold, the LGA connection requires a clamping mechanism. Structure to create the force needed to ensure that each contact member is compressed by an appropriate amount during use to form the interconnection to the circuit member. Lga inserts can be implemented in many different ways, of which the most interesting The implementation is described in the aforementioned pending US patent applications. Today's' various software execution on high-speed digital computing devices requires more dynamic random storage than ever before with higher bus and clock speeds RAM (RAM). In order to ensure fast memory cycle time (cy c 1 etimes) 'very short' fast rising pulses are used. However, when the speed of the data bus and clock in the system increases, it is used to serve multiple Memory 558807 V. Description of the invention (4) The electrical drive requirements of the device become more urgent than when less memory is used. The maximum operating speed of the memory system is mainly composed of the memory controller and the delta memory device. Or determined by the plurality of electrical interconnections between the busbars. When the data transmission rate increases, the signal transmission through the electrical interconnections Compared with the transient time of the signal, it will no longer be negligible. At high bus speeds, these interconnects will behave like transmi ss 丨 〇η line networks. The response characteristics of this transmission line network are defined The maximum usable speed of the memory bus. In the current low-thickness memory packaging technology, the amount of δ memory that is actually available on the system is determined by the capacity of the memory chip (ch 丨 pS) itself. The number of actual electrical connections that can be made on the memory card or module and the amount of available space are determined by the provision of additional memory cards. The number of line drivers or line receivers is another limitation of the memory card or module The memory card or the memory module can be daisy chained. In a general random access memory system, because only one bit can exist in a bus in a certain time zone, the speed of the bus is mainly determined by the setup time of the bus signal. The highest data transfer rate that a bus can achieve in the current memory systems of personal computers is 266 million bits per second (Mbits per sec). Generally, impedance matching is not required or provided in this general memory system. The first point of view of the U.S. Pat. The two examples are similar. However, reading it more carefully shows some weight

Page 8 558807 V. Description of the Invention (5) The major differences. As shown in Figure 1-3, the De 1 1 embodiment is a stackable 6-memory card design. This embodiment describes a stackable memory card having a connector socket attached to the upper surface of each memory card and the pins of the connector attached to the lower surface of each memory card. The motherboard includes these combo sockets. And this packaging technology is capable of working properly with low memory bus technology. The pins of these unshielded inductive connectors represent an electrical failure, which is sufficient to generate effective reflections and electrical noise. In addition, the unused sockets on the upper surface of the uppermost card act as an antenna to interfere with the pickup of the RF. From a reliability / manufacturability point of view, the possibility of damage to this pin and socket-type method to open the module is even a pin or socket being bent or other damage. In this case, the card must be re-realizable or small. For the purpose of disclosure, a RAM module based on RAM bus was selected. It is obvious that the principles taught by the present invention can not only be applied to high-speed memory modules, such as double data read rate (DDR) SDRAM can also be applied to other electronic packaging structures that require high speed and high performance including, but not limited to, microprocessors, digital signal processors, and communication applications and systems. In order to achieve a higher bus speed and, at the same time, allow a larger memory capacity, it is necessary to use an impedance-controlled bus type. For example, the RAMBUS technology developed by the RAMBUS company in Mountain View, California shows a memory configuration in which the memory devices are placed (packaged) on up to 3 RAMBUS in-line memory modules (RIMM) and on the motherboard Interconnected by a high-speed data bus. One or more terminal components are placed on the motherboard at high speed

Page 9 558807 V. Description of the invention (6) The actual end point of the data bus. In operation, these address / data lines leave the drive lines on the motherboard and enter the first 0 card on the memory chain. The same address / material line must leave the RIMM card via a complete 'second set of connections. This path continues through a second and sometimes a third RIMM module before the drive lines reach their terminals. This memory / bus configuration allows very fast signals to be transmitted to the memory controller and relatively long bus data ^ ΐίΐ :: lineΐsome: The bus allows multiple bits to be transferred to the sink simultaneously Grab the mother in the line. As a result, a transmission rate of 800 million bits per second4 can be reached, and higher data rates may appear in the future. One of the most important characteristics of these buses is that the impedance of the signal transmission path is well controlled. One of the bus's effective characteristic impedance matching terminals (two "points; placement and the integrity of the bus and the signal ') In order to maintain the facsimile of the signal in the system using these buses, it is Limitation of amplitude (dv / dt) which is smaller than the amplitude of ordinary digital signals. 疋 Causes the drive of the device to rely strongly on the reliable operation of the memory bus. Very impedance mismatch will cause errors in transmission along the same time. V. %% v This leads to information on page 10 558807 V. Description of the invention (8) The first half needs to be connected in one mold to be more practically large or even modular and all records are not available. Designed to have group or final execution effect, the socket of the present invention is encapsulated due to the length of the body system, which reduces the possible shape of the memory module, or reduces the cost of the module. The biggest innovation of the terminal module is to achieve the The package is more connected because the physical structure of the package is higher than the previous drive memory to dissipate the pins of the transceiver, and this saving essentially allows for a larger number of chip sets. In order to be placed on a single card, I have recalled: nearly all the driving materials' so all the busbars: for these signals through the external contacts: to more improvements. Similarly, the externality of the conventional technology is also reduced. The part of the bus path between the termination resistors. When the memory modules must be identical (for example, 77 ί creates a separate module for termination only) The situation is shown in the later embodiment. The terminal of the pin dew is in In the case of modules, the design of the present invention ^ complexity and memory modules and motherboards are produced into a memory system with one to three memory modules, using a ^ mo group as the most &- Caimo group can help achieve energy. Low-density, selective self-terminated memory modules combined with land grid array (LGA) have a higher / achievable density. This allows more memory. Restricted applications. More memory can be deployed to the actuator / receiver, so the path length is reduced. When the special module is self-terminal. It can include multiple heat pipes and thus increase reliability. The purpose of Ming is to provide a The thickness of the high density memory

Page 12 558807

5. Description of the invention (9) Another object of the present invention is to provide a novel high-density connector technology using a low-thickness, body package. X 1 high-density memory terminal is another module of the present invention, which is to provide a low-thickness, body module, the memory module selectively has a row f on the line 0. The purpose of the present invention is to provide- A low-thickness, high-density memory package 'This memory package can effectively reduce the data path length, thereby helping to simplify the electrical requirements of drives in high-speed digital computers or similar systems. Another object of the present invention is to provide a low-profile, high-density memory package. The memory package can support both single and two bus channels. [Introduction of Invention] The object of the present invention is to provide a low-thickness, high-density electronic package for high-speed, high-performance semiconductors, such as memory devices. The memory module optionally has a bus terminal on the module. It includes multiple modules with high-speed, impedance-controlled transmission line buses, short interconnections between modules, and optional drive line terminals built into one of these modules to maintain high electrical performance. Suitable applications include, but are not limited to, microprocessor data buses and memory buses such as RAMBUS and DDR. These modules can be directly attached to a general printed circuit card without packaging or packaged chips to form the memory modules. The use of these memory modules with a bus terminal directly attached to them improves the quality and integrity of the signal and therefore enhances the performance of the system. This design can also reduce the connection required for the bus to leave, thus allowing the saved connection capacity to be used for the addressing module

558807 V. Description of the invention (〖〇) _ _____ Extra memory capacity. The module can operate at a reliable operating temperature = f thermal control structure to maintain these high densities. [Simplified description of the diagram] # 园内. In order for your reviewers and their objectives to understand the structure and features of the present invention, the detailed description of the specific embodiment is as shown in the schematic diagram of the arrangement of the host # body in the conventional art; the board has Multi-card memory map lb 疋 cross-section view of the bus terminal, enlarged view. A vertical = gold through-hole (pi a ted-through-hole) attachment connector and memory are cross-sectional views in the conventional art. Memory card; showing the bus terminal of the present invention showing a cross-section body package; showing the bus terminal of the present invention is a cross-sectional view showing the second bus terminal of the present invention in a sectional view, zoomed in Enlarged view shows a schematic diagram of a low-thickness memory motherboard on the first embodiment of the low-thickness embodiment of the conventional art; FIG. 'Enlarges the low-second second embodiment of the preferred embodiment of FIG. 2a A schematic diagram of a low-thickness note on the last memory card; 'Enlarged view shows a low-thickness sound of the present invention in FIG. 3a ^ A schematic diagram of a low-thickness note terminal card in the three embodiments. Shows a low-thickness note of the invention in Figure 4a Memories Figure 1c Connectors and Figure 2a Array with Figure 2b Thickness Memory Figure 3a Body Arrangement Figure 3b Memories Package Figure 4a is a display with a sink Figure 4b is-

Page 14 558807 V. Description of the invention (11) Package; 'Figure 5a shows the different memory devices, contact pads and conventional technology 丨 wiring between dragon cards; and Figure 5b shows a comparison with the conventional technology of Figure 5a The technology disclosed in the disclosed embodiments is used to increase electrical performance. [Detailed description of the preferred embodiment] Generally speaking, the present invention is a low-thickness, high-density electronic package 'for high-speed, high-performance semiconductors, such as those made from bare memory chips or general memory chip packages Into a memory device. The memory module optionally has a bus terminal on the module. It includes multiple modules with high-speed, impedance-controlled transmission line buses, short LGA interconnects between the module and the motherboard, and optional drive line terminals built into one of these modules to maintain high electrical Performance. Thermal control structures may be included to maintain the high-density modules within a reliable operating temperature range. Please refer to FIG. 1a, which illustrates a schematic diagram of a multi-card (2 card) memory system 10 in the conventional art. Generally, the two-slot and three-slot boards need terminals on the motherboard 12, and even when all the slots are not in use, you need to wait for the terminals. The signal quality is proportionally attenuated via electrical noise. Standard card-on-board connectors 22, 36 provide the signal path between the RIMM cards 24, 38 and the circuitry on the motherboard 12. For the purpose of disclosure, a RAMBUS-based memory module was selected. It is obvious that the principles taught by the present invention can not only be applied to high-speed memory subsystems, such as double data read rate (DDR) SDRAM, Can also be applied to other packages that require high speed and high performance

Page 15 558807 V. Description of the invention (13) It becomes the second RIMM card 38. Similarly, the RAMBUS channel segment 46 reaches the terminal 48 via the path of the printed circuit board. Such terminal components, such as resistors, hinder (1) 10 (^ 11 ^) capacitors and / or de-bonding capacitors are also placed on the motherboard 12. All RAMBUS channel signals must pass through two connectors 22, 36 and pass through two RIMM cards 24, 38 before reaching terminal 48. A signal drop occurs along the RAMBUS channel ', especially at connectors 2 2 and 36. In addition, useful real estate is filled on the motherboard 12. RIMM card 24 ' 38 is typically a printed circuit board structure that includes an epoxy-resin-based material (e.g., FR4) and contains one or more conductive (e.g., signal, power, and / or ground) layers therein. Because of the urgency of the RAMBUS specification, these signal paths and the impedance of the system must match within 10 percent. The following figures lb and lc are horizontal and vertical sectional views of the connectors 22 and 36 in FIG. Because the connectors 22 and 36 are substantially the same, only the connector 22 is shown in FIGS. 1b and 1c. Please refer to FIG. 1 b ′, which is a cross-sectional view showing an enlarged view. In the conventional art, a vertical gold-plated-through-hole attachment connector and a memory card are shown. The connectors 22, the spring-load contacts 23, provide electrical connection of the contact pads 29 on the motherboard 12 and the RIMM card 24. This type of connector 2 2 'is suitable for through-hole attachment or surface-mount attachment to, for example, a motherboard 12 (Figure ia) structure. Having a through-hole attachment type is electrically inferior but More commonly used. In another case, the 'special spring-load contact 23' causes a large electrical discontinuity.

558807 V. Description of the invention (14) ------ = L Especially at today's high bus speed. This impedance discontinuity obviously adds electrical noise and causes a time delay that causes reflections. In addition, this vertical connector is not available in low thickness applications. Please refer to FIG. 1c, which is a cross-sectional view showing an enlarged view of a low-thickness connector and a memory card in the conventional art. The connector 22, and the elastic-load contact 23, provide contact and execution on the motherboard 12 and the RIMM card 24? qxi Electrical connection. The connector 22 in this form is mainly a structure suitable for attachment to, for example, the motherboard 12 (Fig. 1a). Again, these spring-load contacts 2 3 ′ cause significant electrical discontinuities, especially at today's high bus speeds. The horizontal form of the n connector 22 '' has a lower thickness so that it can be used in lower thickness applications, but in multi-card applications it requires more real space on the motherboard. A two-layer stack version of this connector is effective, but because the connection to the spring-load contact is longer, the electrical discontinuities and electrical noise are worse. The specific arrangement and position of the memory device 2 8 on the memory module 2 4, 3 8 is very relevant to the specific application and does not affect the conventional technology and the following disclosure of the present invention, but these memories The number is the subject and limit of the RAMBUS specification. Three types of low-thickness memory arrays according to different embodiments of the present invention are disclosed below. The main differences are shown in the example of FIGS. 2 a and 2 b. The bus terminal 48 is shown on the motherboard 12, FIGS. 3 a and 3 b. The example shows that the bus terminal 48 is on the last card 82, and the examples in FIGS. 4a and 4b show that the bus terminal 48 is on a separate terminal card 92.

Page 18 558807 V. Description of the invention (15)-Please refer to FIG. 2a, which illustrates a schematic diagram of a low-thickness memory card system 50 according to the present invention. The part of the motherboard 12 again is shown to have supporting circuits required to implement the RAMBUS memory system. A direct RAMBUS clock generator circuit 14 and a host device 16 include a direct RAMBUS cell 18 and the same method as the memory card of the conventional technology shown in FIG. 1a described above is implemented on the motherboard 12. Violating the RAMBUS The channel segment 20 connects the DRAC18 to an LGA connector 52. Again, the RAMBUS channel segment 20 connection is generally made by printed circuit paths (not shown) on the two panels of the motherboard 12. The LGA connector 5 The 2 series is placed between the main board 12 and the first card 54 and provides electrical interconnection therebetween. The LGA connectors 52, 64 generally have a plurality of short and resilient members 53 (Figure 2b) to accommodate the main board 12 on the contact pad 51, and again from-^ 54 to the first card 66. It is preferable that the housing / carrier 49 of the LGA connector 52, 64 has a coefficient of thermal expansion (CTE) In order to closely match the surrounding cards 54, 66. The contact member 53 is a better structure and its composition please refer to the teaching of the US patent application in the common application and the teaching of the US patent application in the other two common applications. Enhance electrical and mechanical performance. Compared with the LGA connector and the socket, the connectors 52 and 64 of the present invention provide an increase in performance, 'increased density, lower height, and a coefficient of thermal expansion (CTE) to better match the surrounding structure. In addition, because Each contact of the connectors 52, 64 requires less force, allowing a significant increase in the number of contacts for known retention forces. The RAMBUS channel segment 20 enters the first card 54 from the bus entry area 56 and

Page 19 558807 V. Description of the Invention (16) It is then connected to a plurality of separate memory devices 28 via a device connection section 58 for attachment to the RIMM card 54. The RAMBUS channel then leaves the RIMM card 54 via a bus leaving area 60, and the RAMBUS channel 62 passes from the first card 54 to the second card 66 directly through the LGA connector 64 instead of returning to the motherboard 120. The RAMBUS channel enters Section 68, a series of memory devices 28, a series of device connection sections 70, and a RAMBUS channel exit section 72 form a second card 66. Similarly, the RAMBUS channel segment 74 returns to the terminal 48 via the shorter distances of the other contact members 53 of the connectors 52, 64. These termination elements, such as resistors, blocking capacitors and / or decoupling capacitors, are also placed on the motherboard 12 as is the case with conventional techniques. Cards 54 and 66 (Figure 2b) are typically composed of epoxy-glass-based materials (e.g., FR4) for printed circuit boards and include one or more conductive layers (e.g., signals , Power and / or ground). Various materials can be used for other reasons including electrical performance, wiring, and thermal performance, but the epoxy-glass-based material has a price-benefit ratio and has a price-benefit ratio and has a thermal Expansion factor (CTE) to better match motherboard 12 and connectors 52,64. Again, because of the urgency of the RAMBUS electrical specifications, this signal path must match the system impedance within ten percent. Referring now to Figs. 3a and 3b, a schematic diagram of a low-thickness memory card system 80 according to an embodiment of the present invention is shown. The part of the motherboard 12 again shows that it has the supporting circuits required to implement the RAMBUS memory system. A direct RAMBUS clock generator circuit η and a master device 16 include a direct

Page 20 558807 V. Description of the invention (17) The RAMBUS ASIC cell 18 is implemented on the motherboard 12 in the same manner as the memory card of the embodiment shown in FIG. 2a. No. ^ 5 4 is also unchanged. The second card 82 includes a RAMBUS channel entry section 84, a series of memory devices 28, and a series of device connection sections 86. However, unlike the embodiment shown in Figs. 2a and 2b, the terminal 48 is directly adhered to the card 82, thereby reducing the required exit portion of the RAMBUS channel 72 and the RAMBUS channel segment 74 (Fig. 2a). By reducing a complete, extra set of contacts, this extra space allows addressing additional memory capacity and simplifies and reduces the cost of the card 82. In one case, the printed circuit board can be reduced from 8 layers to 6 layers. Another advantage of directly attaching the terminal 48 to the card 82 is that less noise is coupled into the motherboard 12, potentially increasing the performance of the entire system. Now referring to Figs. 4a and 4b, a schematic diagram of a low-thickness memory card system 90 according to an embodiment of the present invention is shown. The part of the motherboard 12 again shows that it has the supporting circuits required to implement the RAMBUS memory system. A direct RAMBUS clock generator circuit 14 and a host device 16 including a direct RAMBUS ASIC cell 18 are implemented on the motherboard 12 in the same manner as the memory card of the embodiment shown in Figs. 2a and 3a as described above. However, in order to obtain a more certain application, this embodiment is extended from the previous two embodiments. When the benefits of installing the terminal directly on the card have been understood and the reasons described above are very satisfactory, from the manufacturing and logical point of view, the same δ-memory card is also required. One way to achieve this is to start with the two cards 54, 66 in Figs. 2a and 2b, but with the terminal 48 adhered to the separate terminal card 92. The terminal card 92 further includes a RAMBUS channel access portion 94 and is connected via a connector 96.

558807 V. Description of the invention (18) In the present invention, because there is not a reserved force in the foot and socket type interconnection, a clamping fflechaniSffl can be used to create the required force to ensure the connection Each of the contact members 53 of the actuators 52, 64, 96 is compressed by an appropriate amount to form the interconnections required to the circuit elements. Preferably, the nipper mechanism does not require any attachment holes on the main board. The array of these contact members 53 provides a controlled and uniform displacement force to avoid the problem of CTE mismatch and is a venue. Isolated for user maintenance and upgrade.

Although a device for aligning the cards 54, 66, 82 to the motherboard 12 is not particularly shown in this embodiment, those skilled in the art can easily understand and implement it. The low-density memory card system 50, 80, 90 has low natural heat dissipation efficiency, because the memory device 28 lacks an efficient heat transfer medium from the chip or package to the air, and lacks a short in the direction of the air flow. Air channel (for example, parallel to the motherboard 12). This is because the relatively large capacity of the memory device 28 and the heat generated by other memory devices 28 in this dense package f make the heat dissipation worse. Thermal management structures (not shown) can be included in the system of the present invention to optimize heat conduction and radiation, thus allowing maximum circuit density without thermal growth

This thermal increase will reduce the performance and reliability of the memory device 28. The role of the thermal management structure is to absorb heat from the memory device 28 and can be implemented in a number of ways. They may be as simple as a layer of thermally conductive material, such as aluminum, attached or held to the memory device by a heat-reinforced composite or a nipper.

Page 22 558807 V. Description of the Invention (19) 2 8. The thermal management junction helps dissipate heat. Other heat pipes, and thermoelectricity Although the technology of the present invention is easy to see in each of the above embodiments, that is, a plurality of materials and memories, these types of changes are described below. And the conventional technology is optimized along a single edge and multiple methods are optimized for power, reliability and electricity optimization. How the present invention is shown in Fig. 5b. Figure 5a shows a typical wiring of pad 29. The length is based on the memory of all signals through phase 3 6. This will lead to delay and noise coupling. The structure may also be more complicated and include, for example, a plurality of fins. Methods may include the use of liquid heat transfer materials, thin devices, etc. Even other solutions to thermal issues will be apparent. In the three disclosed embodiments, two memory card devices are shown for the purpose of disclosure. “In this technology, there will be obvious parameters such as the number, shape specifications, dimensions, and the number and packaging of card devices. . This is within the scope of the present invention. Compared with the RIMM card 24, 38 (all its contacts must be placed), all the cards 54, 66, 82 will allow the contact pads to be placed in order to increase the performance. Contact density, wiring energy and mechanical performance. In this way, an example of a method that can provide the motherboard 12 with an electrical characteristic that can optimize the number of connections compared with conventional technology (Figure 5a) is shown in the memory device 28 to the RIMM card 24, 38 contact The signal connection 25 is connected to the contact pad 27 of the memory device 28. The minimum length "L" of the body device 28 is changed because the same edge 31 enters and leaves the RIMM cards 22. The signal connections of the present invention (Figure 5b) At different times, place the contact pad 55 on the card wisely and carefully

Page 23 V. Description of the invention (20) 54, 66, 82. Minimizing and equalizing the length will optimize all signal connections 57 on the card 54, 66, 82. The best way to optimize the method shown in the figure is the actual space used by another province. In some cases it is 82 (the size and / or complexity of the picture. In other cases, the space can be used to improve the electrical performance of these low-density memory cards 50, 80, 90 (Figures 2b, 3b, 4b). . In key circuits such as clocks can be separated from / isolated in the circuit to improve electrical performance. Signal attenuation is generated along the RAMBUS channel path. The connector can be seen. The result is that with the figure ... all the rr lengths in the second school and all the time extensions are reduced === the reduction of the bus k length can simplify the driver's low cost and increase the reliability of the bus. J ^ Generally speaking, High memory access speed can be obtained by improving the quality of the ramms channel (for example, 'reducing channel length, channel delay, crosstalk, etc.). The reduction of the path length and saving the connection between these memory cards and terminals The electrical integrity of the device is greatly improved. In one example, the electrical unshielded elastic load contact 23, 23 " of the conventional technology connection benefit 22 '^ 2 is 0. 150 center inches. In the present invention, the connector 52 , 64 contact member length It is 0.060 inches long. This electrical discontinuity is minimized when the contact member 53 is packaged in a shielded enclosure (as taught in one of the aforementioned U.S. patent applications). In the present invention, a letter A 558807

V. Description of the invention (21) Card 54 traverses to the second card 66, 82, through two long, unshielded, electrical noise connectors 22, 36 and a RAMBUS channel segment (Figure ia) is eliminated of. This can also simplify wiring and / or reduce the cost of the motherboard. Removing and shortening these connectors improves the susceptibility of electromagnetic interference (EMI) and also reduces the RF emissions of motherboard 12 and cards 54, 66, 82. Compared with the conventional technology circuit RIMM card 24, 38 (Fig. La, ib), it only allows a certain number (for example, 8 or 16) of the memory device 28, and + is invented to maximize the density by allowing memory Other divisions of device 28 allow complete

Use all available space on cards 54, 66, 82, otherwise the helmet will become king. / Extended Although the present invention has been disclosed as above in a preferred embodiment, it does not limit the invention of the scholar. Anyone who is familiar with this skill will not deviate from the fascination fe Θ 'when it can be modified and retouched a little, so this: Protective devices shall be subject to the definition of the scope of patent application attached. Guarantee

Page 25 558807 Brief description of the drawings [Simplified description of the drawings] Fig. 1 a Unintended arrangement of a multi-card memory arrangement having a bus terminal on the motherboard in the conventional art; A vertical gold-plated-through-hole attachment connector and a memory card in the ia technique; FIG. lc is a cross-sectional view showing an enlarged view of a low-thickness connector and a memory card in the la technique; FIG. 2a A schematic diagram showing a low-thickness memory arrangement with a bus terminal on a motherboard in the first embodiment of the present invention; FIG. 2b is a cross-sectional view showing an enlarged low-thickness memory in the preferred embodiment of FIG. 2a Package; Figure 3a is a schematic diagram showing a low-thickness memory arrangement with a bus terminal on the last memory card in the second embodiment of the present invention; Invent a low-thickness memory package; • The first embodiment of the third embodiment of the present invention is a schematic diagram of a low-thickness memory bus terminal on a separate terminal card; package? Sectional view, enlarged view. In Figure 4a, a low-thickness memory of the present invention: 5 cloth I display :: memory device, contact pad and conventional technology 2 RIMM card room 3 5 bt :: Γ Figure 58 Technical Comparison A technique for increasing the electrical performance of the embodiment A disclosed in the present invention. [Illustration of reference numerals of components of the figure] Page 26 558807 The diagram briefly illustrates the memory system 10 motherboard 12 RAMBUS clock generator circuit 14 main device 16 direct RAMBUS ASIC cell 18 RAMBUS channel segment 20 connector 22 connector 22, connection Device 22, 'elastic-load contact 23, elastic-load contact 23,' RIMM card 24 signal connection 25 bus entry area 26 contact pad 27 memory device 28 contact pad 29 device connection segment 30 edge 31 bus departure Area 32 RAMBUS channel segment 34 Connector 36 RIMM card 38 RAMBUS channel entry section 40 Device connection segment 42 RAMBUS channel segment 46 Terminal 48 Housing / plant 49 Memory card system 50 Contact pad 51 LGA connector 52 Elastic member 53 RIMM card 54 contact pad 55 bus entry area 56 signal connection 57 device connection section 58 bus exit area 60 RAMBUS channel 62 LGA connector 64 RIMM card 66 RAMBUS channel entry section 68 device connection section 70 RAMBUS channel exit section 72 RAMBUS Channel segment 74 Memory card system 80 RIMM card 82 RAMBUS channel entry section 84

Page 27 558807 Brief description of the diagram Device connection section 86 Memory card system 90 Terminal card 92 RAMBUS channel entry section 94 Connector 96

Hi Page 28

Claims (1)

558807, patent application range 1 · An electronic package for high-frequency semiconductor devices, a) a plurality of circuit components, which has a first surface and a side, and a plurality of contact pads are arranged on the first surface for at least 7 people -: Used to connect to an external data bus; "contact 塾 中, b) the electrical connection device, including a contact member to connect ^, effectively connected to $ φ I # /, the electrical connection to the solid ,: ί Among the contact pads on the first surface of the road member, the M forms an extension of the external data bus. A placement is placed on at least the extension of the circuit components; the place of choice is connected to the external data bus. Extension d) a plurality of contacts are set on the second surface, and among these contacts, there are Λ fewer components and Λ—a bus; Extending the compression of the external data The device is effectively connected to at least one of the circuit components to extend. The device is effectively connected to the extension of the data bus t :: ^ ::, as described in item 1 for high-frequency semiconductor device installation. Display-impedance is essentially the same as; And the bus terminal device is installed in the same electronic package as the patent application No. 丨. It is re-launched by Yifeng A, which is used to connect high-frequency semiconductor devices effectively: this; line device, this line Straight install the first-electrical connection device in a row so as to connect to 558807 -91inQnoi this day "Yi ^^ repair if VI, apply for a patent" ---- 4 · As described in the first scope of the patent application It is used for high-frequency semiconductor devices, and electronic packaging. It further includes a first; an electrical connection device is provided between two circuit members, and effectively connects one of the contact pads on the first surface of at least one of the circuit members. At least one of the contact pads and the second surface of the circuit member. 5. The electronic package for a high-frequency semiconductor device as described in item 4 of the scope of the patent application, further comprising a linear device that is effectively connected to one of these circuit components, so that The devices connected to the second electrical connection device are aligned in a straight line. & 6 The electronic package for frequency-frequency semiconductor devices as described in item 2 of the scope of patent application, wherein the bus terminal device includes at least one of the following electronic component groups: a plurality of resistors, a plurality of capacitors And a plurality of inductors. 7. The electronic package for high-frequency semiconductor devices as described in item 6 of the scope of patent application, wherein the resistors include distributed & resistors. 8. The electronic package for high-frequency semiconductor devices as described in item 6 of the scope of patent application, wherein the resistors include / excluder. 9. The electronic package for a south frequency semiconductor device as described in item e of the patent application scope, wherein the resistors include a solid state, resistive device. 1 〇 An electronic package for a frequency-frequency semiconductor device as described in item 2 of the scope of patent application, wherein the bus terminal device is placed outside the electronic package. An electronic package for a frequency-consumption semiconductor device as described in item 2 of the scope of patent application, wherein the bus terminal device is placed on such circuit components 558807 ^ 91109001_f car B month / day J Wuzheng VI, one of the scope of patent applications 0 2 Electricity 1 2 · The package for high-frequency semiconductor devices described in item 2 of the scope of patent application ^ The package further includes a terminal module And the bus terminal device is Jin μ # ^ on the terminal module. Electricity · For the high-frequency semiconductor device ^, τ η subpackage as described in the first item of the patent application scope, wherein the first electrical connection device is a socket grid array (LGA) connector. Dry Placed 14. For high-frequency semiconductor coatings as described in item 13 of the scope of the patent application ^ It package ', where the socket grid array connector is provided by a high connection. One of the connectors is based on SuperbuttonTM . Electricity · For high-frequency semiconductor devices as described in item 1 of the scope of the patent application ^ FengShang 'wherein the semiconductor devices are a memory device. Electronics · For surface mounting of high-frequency semiconductor devices as described in item 1 of the scope of patent application, wherein the circuit components include wiring devices connecting at least one of the first contact (contact) to the second surface There is one less of these τ heart masters. Zhilei 1 uses the high-frequency semiconductor device circuit described in item 1 of the patent application scope = sub-package ', where the circuit components further include a multilayer printed circuit. For high-frequency semiconductor device groups, at least one of the special t-conductor devices includes at least a download (CSP, β / thin, small package (TS0P), chip size package (CSP), and on-chip package ( c〇B)。 Person t seal 19. Used in high-frequency semiconductor devices as described in item 1 of patent I color 15 Page 31 558807 Amendment No. 9110 Deletion 1 VI. Electronic packaging within the scope of patent application, where the circuit components are essentially parallel to each other. 20. The sub-package for a high-frequency semiconductor device according to item 19 of the scope of application for a patent, further comprising an external printed circuit board structure, and the circuit components therein are substantially parallel to the external printed circuit board structure. 21-The electronic package for high-frequency semiconductor devices as described in item 1 of the scope of patent application, further comprising a plurality of thermal management structures. 22. The electronic package for a high-frequency semiconductor device as described in item 21 of the scope of patent application, wherein the thermal management structures include a plurality of heat-conducting fins when in thermal contact with the at least one semiconductor device. 2 3 · The electronic package for high-frequency semiconductor devices as described in item 20 of the scope of patent application, wherein the external data bus includes at least two external shells; the extension of the external data bus includes at least two Extensions of two data sink production sites * μ cake; and the semiconductor devices include two groups of at least one lead f ′, each group being individually connected to the extension of the two data buses One of them. 24. The sub-package for a high-frequency semiconductor device as described in item 1 of the scope of the patent application, wherein the at least one semiconductor device includes a first surface connected to a semiconductor device up to φ ^. 2 5 'Shiji · Please apply for the high-frequency semiconductor device electrical package described in the patent scope item 24', where a part of these contacts on one of the circuit components is arranged in line with Substrate contact pads on the first surface of these semiconductor devices have substantially the same shape. 2 0j * n sets the patent application scope of item 25 for high-frequency semiconductor devices and electronic seals, and further includes a plurality of interconnections between these circuit components. Page 558807 ϊίί: · Type and at least one of these semiconductor devices 7 · For high-frequency semiconductor package packaging as described in item 26 of the patent claim, where the interconnections are close to the length Equal, the length is short and the length is adjusted to match the minimized length of the interconnects. j · As described in "Please apply for high-frequency semiconductor device shattering as described in item 27 of the Patent Scope, where the interconnection is close to the transmission delay, and the transmission delay is shortened and the transmission delay is adjusted to match the And other interconnects to minimize transmission delays. 29 a) surface, at least b) connected, and at least c) a surface extension, the state, and its composition. An electronic package for high-frequency semiconductor devices, beans include a plurality of circuit components, which have a The first surface and a plurality of contact pads of the first / second table are disposed on the first surface, one of the contact pads is used to connect to an external data bus; the second electrical connection device includes a contact member to provide electrical interaction To connect to the first surface of the circuit component; to form an extension of the external data bus; at least one semiconductor device is placed in the circuit component at least: 卞 and selectively connected to the The first surface of the external data bus that extends over at least one semiconductor device includes two or more rows that are staggered and equidistant from each other. D) a plurality of contact pads are disposed on at least one of the surfaces of the circuit components, the Wait for at least one data bus in the contact pad; each step further extends the outside world Page 33 558807 Scope of patent application e) The folder device is the contact member attached to the circuit member ™ first electrical connection device; one less, to extend the second) = stream terminal device is effectively connected to the extension of the data bus , I 构件 and other circuit components-the surface of the contact 塾 at least-and the second type, which is composed of two or more rows and mutually staggered m contact pads, #quality on the at least The first forms of the contact pads on the first surface of each of the semiconductors 1 are the same. For the high-frequency semiconductors as described in item 29 of the scope of the patent application, at least one of the road members includes a step-by-step including: a first form of the contact pads to the Wait for electricity. The second type of β-Hai contact pads is extended by a plurality of combination pads and the mutual arrangement of the patent range No. 30 for high-frequency semiconductor devices is the beginning of which the interconnections are close to the same length, The long X-break is shortened and adjusted to match the minimum length of the interconnects. 3 2 · For high-frequency half as described in item g1 of Shenyan's patent scope, where the interconnections are close to the transmission delay. The transmission delay is shortened and the transmission delay is adjusted to match the mutual miniaturization. Transmission delay. 3. For high-frequency semiconductor devices and electronic packages as described in item 29 of the patent application scope, wherein the external data bus includes a characteristic impedance, and an impedance is displayed for the bus terminal device to actually match the characteristic impedance. . 34. For high-frequency semiconductor devices as described in item 29 of the scope of patent application ^ 58807 The line device has a 丄 ΐconnect 2:; K includes a straight line device, which is arranged to be connected to at least one of the first circuit components of the daidai 3 Hai special, with # 疋 主 主 主 亥 first electrical 1U to 35 · Rushen & Emperor Clothing's installations line up. The electronic seal f / 7® described in item 29 is used for mounting a circuit component for high-frequency semiconductors, including the second electrical connection device is provided on the first two surfaces. The stem is effectively connected to at least the circuit component. One-at least one of the contact pads on the surface. The first part of the claim is σ A. Please refer to item 35 of the patent scope for high-frequency semiconductor wiring. Di: it further includes a line of linear devices' the line is directly connected to the circuit At least one of the components for aligning the devices connected to the first electrical connection device. 37. The electronic package for high-frequency semiconductor devices according to item 33 of the scope of the patent application, wherein the bus terminal device includes the following electric types: a plurality of resistors, a plurality of capacitors, and a plurality of 38. The electronic package for high-frequency semiconductor devices as described in the scope of the patent application No. 37, wherein the resistors include distributed resistors. 39. The electronic package for high-frequency semiconductor devices as described in item 37 of the scope of application for a patent, wherein the resistors include a resistor. 40. The electronic package for high-frequency semiconductor devices according to item 37 of the scope of patent application, wherein the resistor includes a solid-state resistance device. 41. The electronic package for high-frequency semiconductor devices as described in item 33 of the scope of patent application, wherein the bus terminal device is placed in the electronic package 558807-tS_91109091 on the 6th of June. -Outside. Device 42. An electronic package for high-frequency semiconductor devices as described in item 33 of the scope of patent application, wherein the bus terminal device is placed on one of these circuit components. 1 43. The electronic package for high-frequency semiconductor devices according to item 33 of the scope of patent application, further comprising a terminal module, and wherein the terminal of the busbar is placed on the terminal module. , 44. The electronic package for high-frequency semiconductor devices as described in item 29 of the scope of patent application, wherein the first electrical connection device is a socket grid array (LGA) connector. 45. The sub-package for high-frequency semiconductor devices according to item 44 of the scope of patent application, wherein the socket grid array connector is a SuperbuttonTM-based connector provided by High Connection Density . 4 6. The electronic package for high-frequency semiconductor devices according to item 29 of the scope of patent application, wherein at least one of the semiconductor devices is a memory device. 4 7 · The electronic package for high-frequency semiconductor devices described in item 29 of the scope of patent application, wherein the circuit components include wiring devices connecting one of the contact pads on the first surface to the second and so on Touch at least one of the tadpoles. Surface ... 48. An electronic package for a high-frequency semiconductor device as described in item 29 of the patent application scope, wherein the circuit components include a multilayer printed circuit card. 4 9 · For high-frequency semiconductor devices 558807 f 丄 6. Scope of patent application > year & month_ amendment. Achieving profitability at least one of these semiconductor devices includes at least one of: a bare chip, a thin, small package (TS0P), a chip size package = SP), and a board-on-chip> 5 package (C0B). • 3 sub-packages for high-frequency semiconductor devices as described in item 29 of the scope of the patent application, wherein the circuit components are substantially parallel to each other. The second son is used for high-frequency semiconductor devices as described in Item 50 of the scope of the application / special application. It further includes an external printed circuit board structure, and the circuit components are substantially connected to the external printed circuit board structure. Parallel. • The three sub-packages for high-frequency semiconductor devices as described in item 29 of the Shenjing patent range, further including a plurality of thermal management structures.艚 奘 Ϊ Ϊ Ϊ 子 封 翔, wherein the thermal management structures, when in contact with the at least one semiconductor device, include a plurality of heat-conducting fins. 甏 之 5 ^ · As described in item 29 of the scope of patent application It is used for high-frequency semiconductor packaging materials, wherein the external data bus includes at least two external m flooding rows; the extension of the external data bus includes at least two data guides and 2 extensions; and The semiconductor devices include two busbars including at least one half: one group is individually connected to one of the two materials ~ bits.