TWI251317B - Apparatus and process for precise encapsulation of flip chip interconnects - Google Patents

Apparatus and process for precise encapsulation of flip chip interconnects Download PDF

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TWI251317B
TWI251317B TW091103587A TW91103587A TWI251317B TW I251317 B TWI251317 B TW I251317B TW 091103587 A TW091103587 A TW 091103587A TW 91103587 A TW91103587 A TW 91103587A TW I251317 B TWI251317 B TW I251317B
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wafer
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Rajendra Pendse
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Chippac Inc
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

1251317 A7 B7
五、發明説明（ 相關申請案之交互參考 本申請案主張於2001年2月27曰立案之臨時申請編號 60/272,280之優先權。 發明背景 本發明關於一半導體裝置之封裝，更特定而言，係關於 覆晶封裝。 覆晶封裝包含一藉由内連線凸塊連接到一封裝基板的一 積體電路晶片’其係黏著在該積體電路晶片上的配置，其 對應於基板上金屬接觸墊之配置。在封裝組裝期間，該晶 片及基板係置於相對應的凸塊附近，並對準於該墊，然後 該晶片及基板被放置在一起，其條件為促進該金屬墊上該 凸塊之接合。 覆晶裝置習用上係被封膠來改善該晶片與該基板之間的 内連線之可靠性。通常該封膠係使用兩種方法之一來進行。 在第一種方法中，其稱之為“底部填膠，，，封膠係在形成 該晶片與基板之間的内連線之後來進行，其藉由散佈該封 膠樹脂到靠近該晶片之外緣的基板上之晶片之間的間隙中 ’然後允許該樹脂藉由毛細作用而移入到該晶片與該基板 之間的間隙中。此方法具有較高的製程成本，因為該底部 填膠處理較為耗時，而不能夠達到高產量。再者，在相鄰 裝置之間必須提供一明顯的間隔來在每個晶片的邊緣處容 納該散佈的樹脂球，此對於相鄰裝置之間的額外間隔之需 求限制了該基板的使用率在高密度應用中。 在第二種方法中，一定量的封膠樹脂在組裝該封裝之前 -4 - ^i>(CNS) x 297^?)-----~_ 1251317 A7 B7 五、發明説明（2 被％加到該基板的表面上°然後’當在該組裝處理中該晶 片及基板放置在一起時，任何覆蓋該墊的封膠樹脂在該附 著處理期間，藉由壓力而相對於該墊來取代該凸塊。此技 術可用來由該晶片邊緣橫向地排出該樹脂，以及沿著該晶 片的側壁垂直地排出。由該晶片邊緣之排出需要在相鄰裝 置之間有額外的空間，其會限制了基板的使用率；而垂直 地排除可造成樹脂達到該晶片的背面，並在一些例子中， ^污h】用來操縱該晶粒的接合工具。由於排出會破壞了 製程，因此是不想要的。再者，附著一裝置所需要的熱性 偏移’會造成在相鄰位置上所施加樹脂的部份硬化，因此 對於相鄰裝置上之内部連接之品質有不良的影響。另外， 该樹脂材料藉由散佈或藉由篩網印刷所施加到一表面上的 薄度，實際上會有下限，而該限制一般會大於（在一些例子 中為大兩倍或三倍··對於散佈約為1〇〇微米；對於篩網印刷 約為50微米）該凸塊凸出高度（基本上例如在接合之前約為 50-75微米；而在接合之後最小例如可到約25_3〇微米），其 在一些小型覆晶封裝中為較佳。 、 這兩種方法皆需要一專用的單元製程來施加該樹脂材料 ，該單元製程通常需要專用的設備，因此同時增加了整體 製程之人工成本及資本折舊成本。 _ 本發明提供一種用於封膠覆晶内連線之改進的方法。裙 據該方法，一有限的封膠樹脂量被施加到該晶片的内連線 側，然後該晶片及基板係對準地置於該相對應的凸塊及墊 1251317
I付近’接考該晶片及基板被放置在_起，而其條件可促進 在該金屬墊上該凸塊的接合。該樹脂可用不同的方法來施 力…亥晶片的内連線側。但是，我已發現到由一定義的樹 脂量可以方便及可靠地選擇性施加到該晶片，其係藉由二 浸該晶片的内連線側在該樹脂池中一預定的深度，然後由 ㈣脂池中退出該晶 …樹脂量可精碟地由該晶片被沉 浸在該樹脂μ的預定深度較義，纟係在當該晶片由該 樹脂池退出並帶入該基板來組裝時，所仍保留在該晶片的 被沉浸部份。最為方便及可靠的I，該樹脂池容器中提供 一淺的深度，而該晶片被沉浸到該容器中的樹脂池内，藉 此σ玄凸塊接觸到該容器的底部。因此該樹脂池的預定之淺 涞度決定了當該晶片由該池退出時，仍保留在該晶片的沉 浸部份上的樹脂量。 因此，在本發明一通用方面之特徵為一種用於封膠覆晶 内連線之方法，其藉由施加一限量的封膠樹脂到一積體電 路晶片的内連線側，然後將該晶片與一基板放置在一起， 其條件為利用該基板上的接合墊來促進該晶片的内連線側 上δ玄凸塊的接合。 在一些具體實施例中’該施加樹脂到該晶片的步驟包含 沉浸該晶片的内連線側到一樹脂池中一預定的深度’然後 由該樹脂池退出該晶片。在一些具體實施例中，該晶片被 沉浸到該.池中的預定深度接近於該凸塊表面及該晶片表面 之間的凸出高度，所以該樹脂池的表面會接觸於該晶片表 面’其結果是當該晶片由該樹脂池退出時，一些量的樹月旨
裝 耵
-6- 1251317 A7 B7 五、發明説明（4 ) 會保留在該晶片表面上，以及在與該晶片表面凸出的特徵 上。或是，該晶片被沉浸在該池中的預定深度係略為小於 該凸出高度，所以該晶片表面並不接觸該樹脂池，其結果 是當該晶片由該樹脂池退出時，一些量的樹脂僅會保留在 凸出於該晶片表面之特徵上，例如該凸塊或該凸塊的一部 份。 在一些具體實施例中，該施加樹脂到該晶片的步驟包含 提供具有一底部之容器，其在該容器中提供一樹脂池到該 合為底部之上的一淺深度，沉浸該晶片到該樹脂池中，所 以。亥凸塊會接觸到该谷為底部，然後由該樹脂池退出該晶 片。在一些這種具體實施例中，在該容器底部之上該池的 淺沬度接近於該凸塊表面與該晶片表面之間的凸出高度， 或略為小於該凸出高度。 在另一通用方面’本發明之特徵為用以施加一精確量的 封膠樹脂到-晶片的裝置，其包含一具有底部之容器，及 用於在该容器底部之上散佈一池的封膠樹脂到一預定的深 f的構件。在—些具體實施例中，該容ϋ至少足夠深而能 容納具有-職深度的池，其接近於該晶片上的—凸塊凸 出高度。在一些具體實施例中’用於散佈該樹脂池的構件 包含用以散佈一量測量（measure v〇lume)的樹脂到該容器内 的構仵。在一些具體實施例中，該用以散佈該樹脂池的構 件包含用以散佈一過量樹脂到該容器内的構件，及像是醫 2用於移除過量的構件；在這種具體實施例中，該池的預 定深度係由該容器本身的深度所建立。 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公爱:） 1251317 AT B7
五、發明説明（5 本發明方法之好處為該樹脂圖案係自我對準到該晶片， 所以根據本發明其不需要對準該散佈圖案與該基板上的覆 晶足跡圖案。再者，根據本發明，該樹脂較诖地是施加= 最為特別需要施加樹脂之晶片内連線側之部份，也就是蕙 ，在該凸塊的附近。 根據本發明，該樹脂容器可立即整合到既有的晶片附著 設備，所有其不需要特別或專用的設備或製程步驟來施加 樹脂。 圖式簡單說明 圖1-5所不為本發明方法之具體實施例之階段的部份橫戴 面圖。 發明詳細說明 現在將參考圖面來進一步詳細說明本發明，其代表了本 發明一具體實施例。該圖面為圖形化，以顯示本發明的特 徵及其與其它特徵及結構之關係，其並未依比例繪製。為 了改善表達的明確性，在圖面中所示的本發明方法之階段 中 些元件對應於其它圖面中所示的元件並未全部特別 地重新編號，縱使其可在所有圖面中皆可立即辨識出來。 現在請參考圖1，一般而言在2〇所示為在一支撐22中形成 的容器，及在1 〇所示為由一習用工具丨2所夾持的一積體電 路晶片。該容器28係由一容器底部24及侧邊26所定義。該 容器深度由27所代表，而該容器在此處顯示為將封膠樹脂 填入將近於全深度來形成一樹脂池3 〇 ,3該積體電路晶片i 〇 包含一半導體晶粒18，其具有附著於一晶片表面17中内連 -8 - 本紙張尺度適用中國时標準(CNS) A4規格(210 X 297公董） "' '' 1251317 A7 _— B7 五、發明説明（6 ) 、線f立置（未示於圖中）的内連線凸塊1 6。該凸塊凸出高度係由 1〕代表。該晶片表面1 7及該内連線凸塊1 6及其它未示於圖 中的特徵共同構成該晶片的一内連線側邊14。在圖1中，該 工具12係保持平衡來向該容器20移動（如圖2之箭頭1 1所示） ’以沉浸該晶片的該内連線側14到該樹脂池3 0中。 圖2所示為該晶片正沉浸到該樹脂池30中。該凸塊16已 經帶入而接觸於該容器底部28，所以該池深定義了該晶片 的内連線側被沉浸到該池中的深度。在圖1及2中，該池深 係”、’員示為略小於該容态珠度2 7，而池深亦顯示為略小於該 凸塊凸出高度丨5。因此，在此處所示的範例中，該樹脂池 的表® j 2並未與該晶片表面丨7接觸，所以可預期在當該晶 片由該池退出時，樹脂僅會停留在該凸塊上。 圖j所示為一晶片丨〇已由一樹脂池退出。明顯地，圖3所 不之晶片的内連線側被沉浸到樹脂池中一較大的深度，其 如圖2所示，既然在圖3中該樹脂質量34係顯示成僅在該凸 塊16上承載，但也會在該半導體晶粒的表面丨7上承載。如 所瞭解的，在該晶片由該樹脂池退出之後，由該晶片所承 載的一樹脂質量中的樹脂量將不會僅根據該晶片與該池中 的樹脂接觸於該晶片的含量，但也根據該晶片上不同特徵 之表面特性（例如由該樹脂之濕化度），並根據該樹脂本身的 特性（例如黏度）。一特殊晶片必須沉浸在一特殊樹脂組成的 所想要的預定深度，及造成一特殊需求的封膠形式之預定 深度，其可被立即決定，而不需要過多的實驗。圖3亦顯示 出具另金屬内連線塾42的封裝基板4〇，其配置係亙補於該 -9 - 本紙張足度通用中國國家標準(CNS) A4規格(210 X 297公釐） 1251317 A7 B7 五、發明説明（7 ) 晶片上該凸塊的配置，而該工具I 2係夾持該晶片置於該基 板的附近’並對準相對應的凸塊及墊。該工具在圖3中為保 持平衡來將該晶片及基板置於一起，如例如圖4所示。 在圖4中’該樹脂質量36係顯示已經壓縮在該基板中的晶 片之間’並由該晶片及該基板之内連線侧上不同的特徵所 取代，以形成所想要的“平角”37，其位在該晶粒與基板之 間的間隙之邊緣，其不會有過量的排出。然後該工具1?由 该晶粒釋放，而封膠樹脂即硬化來形成該封裝5 〇之完成的 封膠38，如圖5所示。在該附著作業期間可預期該&塊有一 些變形，而造成該凸出高度的降低。此可進一步壓縮今神子 脂，並強迫其進入由該基板表面上電路圖案，以及由兮曰 片的内連線側上之特徵所形成的凹凸不平處，而造成改進 的封膠積集度。 其它具體實施例皆位在以下的申請專利範圍中。
本纸張尺度適用中國國家標準(CNS) Α4規格(210 X 297公肩

Claims (1)

  1. 號申請案 中iS申請專利範圍替換本(94年11月）
    8 8 8 8 A B c D Ί: 一種用以封膠覆晶内連線的方法，其包含施加一限量的 封膠樹脂到一積體電路晶片的該内連線側，然後將該晶 片與基板放在一起，其條件為藉由該基板上的接合墊 f促進該晶片的内連線側上之凸塊的接合，其中該施加 树月曰到5亥晶片的步驟包含沉浸該晶片的内連線側到一樹 2. 月曰池中預疋的深度，然後由該樹脂池退出該晶片。 如申請專利範圍第！項之方法，其中該晶片被沉浸在該池 中的預定深度接近於_凸塊凸出高度，所以該樹脂池的 表面接觸於該晶片的一表面，因此當該晶片由該樹脂池 退出時，一些量的樹脂會保留在該晶片表面，以及凸出 該晶片表面的特徵上。 3. 4. 如申請專利範圍第1項之方法，其中該晶片被沉浸在該池 中的預定深度係小於該凸塊凸出高度，所以該晶片表面 ?未接觸該樹脂池，其結果在當該晶片由該樹月旨池退出 枯，一些量的樹脂可僅保留在凸出該晶片表面的特徵上。 如申請專利範圍第1項之方法，其中施加樹脂到該晶片包 含提，-具有底部的容器’其在該容器中提供—樹脂池 為該容器底部之上一淺的深度’沉浸該晶片到該樹脂池 中;’所以該凸塊會接觸該容器底部，然後由該樹脂池退 出该晶片。 5.如申請專利範圍第4項之方法，其中在該容器底部之上該 池的淺深度接近於該凸塊凸出高度。 6·如申請專利範圍第4項之方法，其中在該容器底部之上該 池的淺珠度係小於該凸出高度。 76393-941107.doc 本紙張尺度適用中國國家標準(CNS) A视格 1251317
    A B c D 7. -種用以施加一精確量的封膠樹脂到一積體電路晶片的 裝置’其包含具有—底部的容器，及用以在該容器底部 之上散佈一封膠樹脂池到一預定的深度的構件。 如申請專利範圍第7項之裝置，其中該容器係至少足夠地 冰以谷納具有接近於該晶片上^一凸塊凸出高度之預定 深度的池。 如申請專利範圍第7項之裝置，其中用以散佈該樹脂池的 構件包含用以散佈一量測的樹脂量到該容器内的構件。 10 ·如申請專利範圍第7項之裝置，其中用以散佈該樹脂池的 構件包含用以散佈一過量樹脂到該容器内之構件，及用 以移除該過量的構件。 8. 9. 76393-941107.doc 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐）
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US6780682B2 (en) 2004-08-24
US20020123173A1 (en) 2002-09-05
KR20030092001A (ko) 2003-12-03
EP1461823A1 (en) 2004-09-29
JP4243487B2 (ja) 2009-03-25
WO2002069377A1 (en) 2002-09-06
JP2004525512A (ja) 2004-08-19
EP1461823A4 (en) 2009-09-23
US20030205197A1 (en) 2003-11-06

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