TWI248141B - Semiconductor device and manufacturing method therefor - Google Patents
Semiconductor device and manufacturing method therefor Download PDFInfo
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- TWI248141B TWI248141B TW092108527A TW92108527A TWI248141B TW I248141 B TWI248141 B TW I248141B TW 092108527 A TW092108527 A TW 092108527A TW 92108527 A TW92108527 A TW 92108527A TW I248141 B TWI248141 B TW I248141B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 97
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 112
- 239000002184 metal Substances 0.000 claims abstract description 112
- 150000002739 metals Chemical class 0.000 claims abstract description 7
- 238000010030 laminating Methods 0.000 claims abstract description 6
- 238000001039 wet etching Methods 0.000 claims abstract description 5
- 238000007747 plating Methods 0.000 claims description 25
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 22
- 238000000576 coating method Methods 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 229910052759 nickel Inorganic materials 0.000 claims description 11
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims 1
- 238000007789 sealing Methods 0.000 abstract description 32
- 239000010410 layer Substances 0.000 description 135
- 238000005530 etching Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 9
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 238000005260 corrosion Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910000975 Carbon steel Inorganic materials 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000005587 bubbling Effects 0.000 description 2
- 239000010962 carbon steel Substances 0.000 description 2
- 239000011247 coating layer Substances 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 229920000768 polyamine Polymers 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 230000008093 supporting effect Effects 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052770 Uranium Inorganic materials 0.000 description 1
- 230000002609 anti-worm Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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Description
1248141 拾、發明說明 L發明所屬技術領域;| 發明之背景資料 1. 發明之技術區域 本發明係有關於一種具有等同於半導體構件尺寸之半 5 導體元件及其製造方法。 C先前技術3 2. 相關技術之説明 圖5為習知如晶片尺寸之半導體元件1〇的範例的組 態0 在半導體構件12上形成電極端14,再於其表面之上形 成保護膜16,並裸露出該電極端14。 在保護膜16上塗佈一由有機樹脂所組成的絕緣塗層 18,並使半導體構件12的電極端14裸露在外。 在、、’巴緣塗層18上形成(一或多個)配線圖案,其一 且(一或多個)
端與半導體構件12的電極端14電氣相接 配線圖案20的另一端形成-區域20a。圖
封該配線圖案2〇。 ,依序塗佈鍍鎳和鍍金的鍍 柱狀電極26的頂端表面上, 1248141 拾、發明說明 層22。 另外’在柱狀電極26的頂端表面上(也就是在鍍層22 的表面之上)形成外連接端24,並使其頂端表面裸露於該 密封層28外。 5 當該半導體元件10被設在框架(未示出)上時,由於 半V體構件12和框架(例如樹脂電路板)的熱膨脹係數相 異’使配線圖案20受到壓力。 因此,將延長狀的柱狀電極26介入外連接端24和(一 或夕個)配線圖f 20之間,而柱狀電極26本身會吸收及減 10 輕該壓力。 如上所述之半導體構件12上所形成的半導體元件10 中的配線圖案20,其製造方式的概要說明,以圖6至1〇 說明。 首先,如圖6所示,在半導體構件12上的保護膜16 15上於電極端14以外的地方,形成聚胺型樹脂所製的絕緣 塗層18。 接著如圖7所示,以濺鑛方式建造由鈦或鉻所製的 黏性金屬層25a和銅層25b所構成的金屬膜25,,使25a 和25b層的厚度各自大約為〇 〇5至〇·2 #爪和大約〇 5 # m。 2〇 接著,如圖8所示,將防蝕圖案27形成凹槽狀,並使 銅層25b的σ卩份保留裸露以形成配線圖案(重配線圖案), 並將此防蝕圖案27當為鍍罩,和金屬膜25為導電層,在 金屬膜25上以電解鍍銅形成鍍膜,以製造配線圖案20。 1248141 拾、發明說明 該電解鍍銅所形成的金屬層構成配線圖案20的基礎部份。 在形成配線圖案2 0之後’將防钱圖案2 7移除。 接著’如圖9所示’在半導體構件12上形成防敍層29, 其中’在半導體構件12上面形成配線圖案2〇,在執行曝 5光和形成後,防蝕層29中形成開口 31,並裸露配線圖案 20之區域20a。 接著,如圖10所示,在開口 3 1之内的區域2〇a上, 以電鍍(銅、鎳或其相似)形成鍍膜,並且填補開口 31形 成柱狀電極26 (大約至高度1〇〇 " m)。 10 另外,在此柱狀電極26的頂端表面的上面,形成由鎳 鍍膜和金鍍膜所組成的鍍膜22。鍍膜22也可呈雙層鍍膜, 其是由鎳鍍膜和鈀鍍膜連續形成的。 接著,將防蝕層29移除。然後,將配線圖案2〇當作 蝕刻遮罩圖案,執行蝕刻以移除裸露的金屬膜25(銅膜Mb 15和黏性金屬膜25a),使(一或多個)配線圖案20獨立。 以此方式在半導體構件12上面(圖1〇)形成絕緣塗層 18 ( —或多個)配線圖案2q和柱狀電極26。 接著,如第11圖所示,在半導體構件上形成電極端14, 而在半導體構件表面上,利用有絕緣性質的樹脂,形成密 2〇封層28以密封該半導體構件的表面。 詳細說明之,以密封層28形成柱狀電極26的頂端表 面裸露在外。外連接端24,例如焊錫球,被接合於裸露在 密封層外的柱狀電極26的頂端表面。 1248141 拾、發明說明 至此的程序通常是被執行於半導體晶圓上,並在其上 形成多數半導體構件。 接者,最後依各半導體構件,將該晶圓切割成獨立的 複數單位,以便製造如圖5所示的半導體元件1〇。 5 圖13為用此方法製造的半導體元件範例的透視圖。 圖Μ為用此方法製造的半導體元件範例的截面圖。此 例中沒有安裝柱狀電極。 圖15為由頂部所觀察以此方法製造的半導體元件範 例。 1〇 此圖透過密封層顯示配線圖案等。 在以上所敘述的半導體元件10之中,密封層28覆蓋 及饴封半導體構件12頂端表面,以及在半導體構件上 面形成電極端。由於半導體構件12和密封層28的熱膨脹 係數相異甚大,密封層28被認為必須不能因溫度起伏而輕 15 易地脫離黏著表面。 在習知的半導體元件10中,密封層28是由兩種黏著 力緊黏在半導體構件12上所形成之電極端的表面的頂 邛’此兩種黏著力就是密封層28和形成於半導體構件j2 上之電極端的表面上的絕緣塗層18間的黏著力,以及配線 20圖案20和密封層28間的黏著力。 此外’因為這兩種黏著力中,樹脂層之間的黏著力較 大’由聚胺型樹脂或其類似所形成的絕緣塗層18和密封層 2 8之間的黏者力’被認為是全體黏者力的較大部份。 1248141 拾、發明說明 然而,隨著半導體構件12上的電極端14的數量持續 i曰加’以及因近年的小型化及高密度化的實現’形成在電 極端形成表面上的(-個或多個)配線圖案20的面積持續 枚加’絶緣塗層18裸露部份的比例減少,因而造成密封層 5 Μ於電極端形成表面上的整體黏著性減少 的問題。 【發明内容】 因此,本發明是用來解決以上所描述的問題,並提供 "種半導體70件和其製造方法為目標,其中當密封層密封 半導體構件之電極端形成表面時,其將顯示出極佳的黏著 10 性。 曼ϋ之概要說明 具體地說,在此應用的本發明如下: 1· 一種半導體元件,其包含有 配線圖案,其—端電連接至形成在半導體構件之電 15極端形成表面上的電極端,其另_端形成區域連接至外連 接端’ 該配線圖案被形成在半導體構件之電極端形成表面上,且 該配線圖案有一側表面有内切部份。 2. 如上述1之半導體元件,其中該配線圖案是以層屋 20多數金屬的金屬層所形成的層狀結構,且在該配線圖案中 至少-金屬層Α的侧表面,相較於形成在金屬層Α上面或 更高的的金屬層B的側表面,是形成凹入。 3. 如上2之半導體元件,其中該金屬層a是由錢铜所 1248141 拾、發明說明 形成,和該金屬層B是由鍍鎳或鍍鎳合金所形成的。 4· 一種製造半導體元件的方法,其中配線圖案之一端 電連接至形成在半導體構件之電極端形成表面上的電極 端,且其另一端形成連接至外連接端的區域,其步驟包含 5 有: 該配線圖案以層壓包含多數金屬的金屬層形成層 狀結構;和 蝕刻該配線圖案的側表面。 5. 如上4之製造半導體元件的方法,其中該配線圖案 10是以層壓金屬層,以鑛鎳或錄錄合金層於鑛銅形成的層次 之上,形成層狀組織。 6. 如上5之製造半導體元件的方法,其更包含以下步 驟: 於該電極端形成表面上形成絕緣塗層,並裸露該電極 15 端; 於該絕緣塗層和該電極端上形成金屬膜; 於該金屬膜上形成防姓圖案,並裸露配線圖案的形成 點; 以層壓形成該配線圖案後,移除該防敍圖案; 20 細己線圖案當作遮罩圖案,刻和移除該裸露的金 屬膜。 7. 如上述6之製造半導體元件的方法,其中該金屬膜 是以鉻金屬膜層壓於銅金屬膜上而形成的層狀組織。 1248141 拾、發明說明 當上述的配線圖案的側表面部份有内切部份時,可發 現密封層28的黏著性可被顯著改進。「内切」在此意味著 將配線圖案20的側表面形成得使其較低部份比其較高部 伤凹入’如圖12A、12B及12C所示。如圖12A、12B及 5 12C中所示,當上拉密封層28的力量產生時,由於填充於 凹入處的树月日產生所明的支撐效應(anch〇r e£Yect )會抗拒 該「上拉力量」,本發明被認為達得效果。 如此的内切結構可由任何已知的方法製造。例如,如 圖12A所示,可實行電鍍而使最上面的鍍層突出。 10 另外,例如若該配線圖案是包含,由濕蝕刻(wet etching)輕易侵蝕的金屬所組成的金屬層X (如圖12B中 示範)和形成於其上由尚度抗濕餘刻侵|虫所組成的金屬層 Y (如圖12B中示範),相較於γ層側表面,執行濕蝕刻以 敍刻較多的X側表面,而形成如圖12 a (譯註:原文為2 a ) 15 所示的内切是可能的。此方法技術上簡單且較佳。 不必多說,層壓金屬層不是形成内切的必要條件。 再者,在由多數金屬層所組成的配線圖案的例子中, 將錢鋼作為金屬層基礎部份,以及在其之上形成由鍍鎳或 艘鎳合金所形成的金屬層,是較佳於達成較易形成内切的 20 目的。 若當如此,被蚀刻較多的金屬層之上或更上端的金屬 層並不一定需要緊連著該被餘刻較多的金屬層頂部,但金 屬層緊連被餘刻較多的金屬層頂部的結構會有較明顯的内 1248141 拾、發明說明 切成效(凹入成效)。因此這是較佳的。 如前文所說明,注意當製造半導體元件時,通常會被 加入藉著以蝕刻移除裸露的電導金屬膜的處理步驟,而且 匕有時發生於金屬膜橫截面比作為蝕刻遮罩圖案的配線圖 5案的橫截面更為凹入,因而產生内切結構的過程。但是, 這類的内切對於改進密封層28的黏著力沒有太大的貢 獻’因此在配線圖案本身上有内切是重要的。 造成這個的原因不是很清楚,但據猜測該原因是,由 於金屬膜的厚度大約〇·5至〇.7#m ,密封物本身很難進入 〇凹處,而且即使它進入凹處,該充分的剛性不能牢固地反 抗向上的拉力。 本發明也包括上述所說明的方法4至7。 依照刖文,更明確地說,蝕刻配線圖案的分層金屬側 表面部份是較佳的方法。乾蝕刻或濕蝕刻都可被應用。濕 15蝕刻是較佳的,因為可輕易地影響金屬間蝕刻速度的差異。 上述所說明的金屬膜最好是由層壓銅金屬層成層狀組 織於鉻金屬膜上。 因為依據本發明的配線圖案在提高密封層的黏著性方 面提供顯著的效用,明確測量安裝於功能上無須重配線的 2〇位置以及於原配線太少(密度太小)的位置的假配線圖案, 以獲得本發明目的相等的支撐效應,且將會是有效的。若 是如此,則顯示出不需要將配線圖案連接至半導體電極端 或外連接端。 1248141 拾、發明說明 圖式之簡要說明 圖1A為描述依據本發明的半導體元件的一種實施例中 配線圖案結構之橫截面圖; 圖1B為顯示圖1A中配線圖案在形成内切結構前的狀 5 態之橫截面圖。 圖2 A為描述依據本發明的半導體元件的另一種實施例 中配線圖案結構之橫截面圖; 圖2B為顯示圖2A中配線圖案在形成内切結構前的狀 態之橫截面圖; 圖3為半導體元件之橫截面圖,其中外連接端被設定 為L狀的彎曲金電線; 圖4為半導體元件組態之橫截面圖,其中鼓起狀的外 連接端直接形成於配線圖案的區域上; 圖5為半導體元件组態之橫截面圖,其中鼓起狀的外 15連接端形成於柱狀電極上,而柱狀電極形成在配線圖案區 域上; 圖6為說明圖5中半導體元件的製造方法之解釋圖, 並顯示當絕緣塗層和保護膜形成於晶圓上的狀態; 圖7為當導電層(包含黏著性金屬層和塗層的金屬膜) 2〇形成於圖6中絕緣護層上的狀態之解釋圖; 圖8為當配線圖案形成於圖7中導電層(包含黏著性 金屬層和塗層的金屬膜)的狀態之解釋圖; 圖9為當柱狀電極將要形成於圖8中配線圖案的區域 1248141 拾、發明說明 上的狀態之解釋圖; 圖10為當圖9中的護層已被移除、導電層(包含黏著 性金屬層和塗層的金屬膜)已被蝕刻所移除以及每個配線 圖案已被獨立的狀態之解釋圖; 5 圖11為描述被密封層28密封的半導體元件之解釋圖; 圖12A、12B和12C為描述内切的模型圖; 圖13為半導體元件範例之透視圖; 圖14為半導體元件範例之截面圖;和 圖15為半導體元件之上視圖。 10 【實施方式】 較佳實施例之説明 現在,詳細說明依據本發明的半導體元件和其製造方 法的較佳實施例。應用在組態中相同的符號與習知(一個 或多個)範例中的相同,因此不此作額外的說明。 15 '主忍以下僅為半導體元件和其製造方法的實施例,且 並不侷限本發明之區域。 參考圖1A和圖2A,先說明本發明之基本概念。 、’I圖案20形成於半導體構件12之電極端形成表 面寺》亥配線圖案2〇是由各種金屬層麼而成層狀組織(例 2〇 在圖1八中,1;和¥兩片金屬層為層狀組織),以構成 多數金屬層疊層的組態。U金屬層為較低層,且是配線圖 案2〇的基礎部份,幼對於直卿成在U金屬層之上的v 孟屬層的侧表面,其側表面被設定成將會被内凹。換言之, /4 拾、發明說明 該内凹部份因此成為内切。 因此,在已形成電極端之表面上塗上呈現電絕緣性質 的樹脂以形成密封層28,且已形成電極端之表面被密封 4 ’该樹脂由配線圖案20的周邊進入側表面的凹入部分, 與配線圖案20結合,並且呈現支撐效應。因而提高該密封 層28的黏著性。 另外’配線圖案20可被形成為如圖2A所示的三個或 以上的多層結構(例如,四層U、v、W和X ),U和W金 屬層構成配線圖案20的基礎部份,相對於直接形成在個別 之上的V和X金屬層的側表面,其側表面被形成為會内 凹與雄、封層2 8結合地點的數量增加,會更提高支樓效應。 接著δ兒明半導體元件的組態和該半導體元件的製造方 法。由於泫半導體元件的組態和製造方法和習知範例有許 多相同點,圖5至10與圖1至4 一併使用。 首先指向依據本發明的半導體元件的組態,如圖5所 示的基本組態。該組態不同於習知技術,如先前說明以及 如圖1Α和圖2Α所示的配線圖案2〇是由各種金屬層壓而 形成層狀組織(圖1Α中的二層,即❻v金屬層,和圖 2Α中的四層,即υ、ν、w和χ金屬層),以成為一種組 匕其中u金屬層(亦同圖2Α中^金屬層)構成配線圖 案20的基礎部份,且相對於直接形成在U金屬層上的V 金屬層(亦同圖2Α中χ金屬層),其側表面被内凹。 例如,將如圖1Β和圖2Β中側表面無内凹的配線圖案 1248141 拾、發明說明 触刻或其相似,可形成此内凹結構(將在以下說明)。 接著說明一種依據本發明的半導體元件製造方法。 由圖6中在半導體構件12之電極端形成表面上,形成 絶緣塗層18並裸露電極端的程序步驟,至圖7中於絕緣塗 層18上形成金屬膜25的程序步驟,更至圖8中形成防蝕 圖案27且於形成配線圖案2()的地方裸露金屬膜υ之程序 步驟’這些步驟和習知技射的步驟完全相同。 10 接著,如圖8中所示,在將防餘圖案27為鍍罩,於裸 露的金屬膜25上形成配線圖案2〇的程序步驟中,以層壓 形成不同金屬的金屬層,例如依據本發明的實施例,層壓 於構成配線圖案20基礎部份的銅電鍍形成的金屬層上,然 而,在習知範例中,配線圖案是由鋼電鍍形成且厚度為5 至20#m不等的一片金屬層。 具體地說,以由鎳電鍍或鎳合金電鍍所形成的金屬 15層,層壓於構成配線圖案20之基礎部份的金屬層是較佳 的0 參照先前說明的圖1B,由銅電鍍形成的金屬層是u 層,以及由鎳電鍍形成的金屬層是V層。 而且,重複執行此金屬層壓可形成有3或更多層的配 20 線圖案20。 接著,如習知範例,將防蝕圖案27移除。 在此之後,如習知範例,實施如圖9中所示的程序步 驟’形成防韻層29,其中開口 31裸露區域20a,以及形成 16 1248141 拾、發明說明 柱狀電極26。 在形成柱狀電極26之後,將防_29移除。 接著,在如圖1G所㈣程序步”,也就是在使配線 %、20獨立的程序圖案中,將配線圖案20當作遮軍圖荦, 以钱刻將裸露在半導體構件之上的金屬膜h (銅層⑽和 點者性金屬層…)料。同時,相對於V金屬層(圖2B 中的V和X層)的側表面,構成配線圖案20基礎部份的u 金屬層(圖2B中的層)的側表面独刻且内凹。 10 在此程序步驟中所使用的蚀刻液會姓刻金屬膜Μ和構 成配線圖案20基礎部份的金屬層(u^w層),但卻不會 侵#緊接在上的金屬層(▽和\層)。 接著,如習知範例以及如圖n所示,於半導體構件η 之建造電極端的表面之上形成密封層28,在柱狀電極^ 的頂端表面上形成外連接端24(焊錫凸塊),並裸露在密 15封層28之外,最後,該晶圓依半導體構件12切割成獨立 單位以完成依據本發明的半導體元件。 在刚文所說明的實施例中,雖然組態是將外連接端24 形成政起狀’且形成於柱狀電極26頂端表面之上,但該半 導體元件能夠設定成一種組態,其中將彎曲成L狀的金線 2〇直接結合在區域20a上,如圖3所示範。 另外,半導體元件能夠設定一種組態,其中將同樣為 鼓起狀的外連接端24直接形成在區域20a上,並不需形成 柱狀電極2 6,如圖4所示範。 η 1248141 拾、發明說明 如上說明,在一個將外連接端24直接形成在(一或多 )-己線圖案20上的程序圖案範例中,如圖8令所示的程 乂驟*電解錄鎳形成的金屬層直接形成於由電解錢鋼 成的至屬層上面,然後最上層形成為⑽金形成的錢金 5 層, ;4後’在移除防1虫圖案27後,省略如圖9中形成柱狀 電極26的程序步驟,並且若外連接端24為圖3中所示的 、爿則形成防蝕層29使成為能使區域2〇a為裸露的狀 〜、如圖9所不。然後將金線彎曲成l狀,直接接和至區 或20a ’而形成外連接端24,並將該金線以鍍鎳合金覆蓋 表面於以增強。在此之後’將防則29移除,並且將配線 圖案20當作遮罩圖案,以蝕刻移除金屬膜25。於此時, 配線圖案2G的U金屬層(由電解賴所形成的金屬層)的 側表面也會被蝕刻和内凹。 15 在此之後,將防焊油墨覆蓋於半導體構件12之形成的 電極端表面上,以形成密封層28但裸露外連接端24。 另外,若外連接端24為如圖4所示之形狀,則在移除 防蝕圖案27之後,將配線圖案2〇當作遮罩圖案,以蝕刻 移除金屬膜25。於此時,配線圖案2〇的u金屬層(由電 2〇解鍍銅所形成的金屬層)的側表面也會被蝕刻和内凹。 在此之後,將防焊油墨覆蓋於半導體構件12之形成的 電極端表面上,以形成密封層28但只裸露區域2〇a,並將 焊錫球或其他的外連接24接合至區域2〇a。 1248141 拾、發明說明 在上述說明的實施例中的半導體元件製造方法之中, 成果包含半導體晶圓,但成果為單一的半導體構件是被許 可的。在此情況時,切割成獨立單位的工作就變得不是必 要的。 5 録本發明中所說明的半導體元件和半導體元件製造 方法,配線圖案的部份側表面被内凹,並使側表面形成不 均勻狀。於是,當在電極端形成表面上形成密封層時,密 封層的樹脂與配線圖案的不均勻處結合,產生支撐效應。 因此提高密封層的黏著性,並且獲得益處因為密封層變得 10 很難剝落。 【圖式簡單說明】 圖1A為描述依據本發明的半導體元件的一種實 施例中配線圖案結構之橫戴面圖; 15 圖1B為顯示圖1A中配線圖案在形成内切結構前 的狀態之橫戴面圖。 圖2A為描述依據本發明的半導體元件的另一種 實施例中配線圖案結構之橫截面圖; 圖2B為顯示圖2A中配線圖案在形成内切結構前 20 的狀態之橫截面圖; 圖3為半導體元件之橫截面圖,其中外連接端被 設定為L狀的彎曲金電線; 圖4為半導體元件組態之橫截面圖,其中鼓起狀 1248141 拾、發明說明 的外連接端直接形成於配線圖案的區域上; 圖5為半導體元件組態之橫截面圖,其中鼓起狀 的外連接^开> 成於柱狀電極上,而柱狀電極形成在配 線圖案區域上; 圖6為說明圖5中半導體元件的製造方法之解釋 圖,並顯不當絕緣塗層和保護膜形成於晶圓上的狀態; 圖7為當導電層(包含黏著性金屬層和塗層的金 屬膜)形成於圖6中絕緣護層上的狀態之解釋圖; 圖8為當配線圖案形成於圖7中導電層(包含黏 1〇 著性金屬層和塗層的金屬膜)的狀態之解釋圖; 圖9為當柱狀電極將要形成於圖8中配線圖案的 區域上的狀態之解釋圖; 圖10為當圖9中的護層已被移除、導電層(包含 黏著性金屬層和塗層的金屬膜)已被蝕刻所移除以及 15 母個配線圖案已被獨立的狀態之解釋圖; 圖11為描述被密封層28密封的半導體元件之解 釋圖; 圖12A、12B和12C為描述内切的模型圖,· 圖13為半導體元件範例之透視圖; 20 圖14為半導體元件範例之截面圖;和 圖15為半導體元件之上視圖。 1248141 拾、發明說明 【圖式之主要元件代表符號表】 10.· .半導體元件 12·· .半導體構件 14·. .電極端 16.· .保護膜 5 18·· .絕緣塗層 20.. .配線圖案 20a. ..區域 20b. ..導電點 22·· .鍍層 24...外連接端 25a. ..黏性金屬層 25b. ..銅層 25·· .金屬膜 26··, .柱狀電極 10 27.. .防蝕圖案 28...密封層 29·· .防蝕層29 31… .開口 3 1
Claims (1)
12481411 玖、申請專利範圍 1 . 一種用以製造半導體元件的方法,其中一配線圖案 被形成在該半導體元件上,該配線圖案之一端電連 接至形成在一半導體構件之電極端形成表面上的電 極端,且其另一端形成連接至外連接端的區域,其 步驟包含有: 於該電極端形成表面上形成一絕緣塗層,並暴露 該電極端; 於該絕緣塗層和該電極端之上形成一金屬膜; 於該金屬膜上形成一抗蝕圖案,以此方式,暴露 用以形成配線圖案的位置; 藉由將電鍍形成之包含多數不同金屬的金屬 層,層壓成為一層狀形狀,以形成該配線圖案;及 形成該配線圖案後移除抗蝕圖案;及 將配線圖案用作為遮罩,藉由施行濕蝕刻以蝕刻 金屬膜和該配線圖案的側表面部分,同時移除該已 經暴露的金屬膜。 2 .如申請專利範圍第1項之用以製造半導體元件的方 法,其中該形成配線圖案的步驟包含藉由將金屬層 層壓成為一層狀形式,該層狀形式在一藉由鍵銅所 形成之層上具有一鎳或鎳合金鍍佈層。 3.如申請專利範圍第 2項之用以製造半導體元件的方 法,其中該金屬膜是藉由將一銅金屬膜層壓成為一 22 1248141 玖、申請專利範圍 層狀形式,而被形成於一鉻金屬膜上。
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JP35522999A JP3502800B2 (ja) | 1999-12-15 | 1999-12-15 | 半導体装置の製造方法 |
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US (1) | US6667235B2 (zh) |
EP (1) | EP1109219A3 (zh) |
JP (1) | JP3502800B2 (zh) |
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EP1868423A1 (en) * | 1998-09-17 | 2007-12-19 | Ibiden Co., Ltd. | Multilayer build-up wiring board |
JP3409759B2 (ja) * | 1999-12-09 | 2003-05-26 | カシオ計算機株式会社 | 半導体装置の製造方法 |
JP2003152014A (ja) * | 2001-11-09 | 2003-05-23 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法及び半導体装置 |
JP3829325B2 (ja) * | 2002-02-07 | 2006-10-04 | 日本電気株式会社 | 半導体素子およびその製造方法並びに半導体装置の製造方法 |
JP2004104103A (ja) * | 2002-08-21 | 2004-04-02 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2005203695A (ja) * | 2004-01-19 | 2005-07-28 | Casio Micronics Co Ltd | 半導体装置およびその製造方法 |
US7830011B2 (en) * | 2004-03-15 | 2010-11-09 | Yamaha Corporation | Semiconductor element and wafer level chip size package therefor |
JP4449824B2 (ja) * | 2005-06-01 | 2010-04-14 | カシオ計算機株式会社 | 半導体装置およびその実装構造 |
DE102006036798B4 (de) * | 2006-08-07 | 2013-08-29 | Infineon Technologies Ag | Elektronisches Bauteil und Verfahren zum Herstellen |
JP2009135417A (ja) * | 2007-11-07 | 2009-06-18 | Sumitomo Metal Mining Co Ltd | 半導体素子搭載用基板の製造方法 |
JP5164160B2 (ja) * | 2008-09-25 | 2013-03-13 | 日立マクセル株式会社 | 半導体装置とその製造方法 |
KR101111930B1 (ko) * | 2008-09-30 | 2012-02-14 | 이비덴 가부시키가이샤 | 다층 프린트 배선판, 및 다층 프린트 배선판의 제조 방법 |
JP2012054359A (ja) | 2010-08-31 | 2012-03-15 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP6030370B2 (ja) * | 2012-07-27 | 2016-11-24 | 京セラ株式会社 | 配線基板および電子装置 |
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JP6210818B2 (ja) | 2013-09-30 | 2017-10-11 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
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US6667235B2 (en) | 2003-12-23 |
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JP3502800B2 (ja) | 2004-03-02 |
EP1109219A2 (en) | 2001-06-20 |
KR20010062416A (ko) | 2001-07-07 |
US20010004133A1 (en) | 2001-06-21 |
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