JPS61296800A - 設計変更用電極 - Google Patents

設計変更用電極

Info

Publication number
JPS61296800A
JPS61296800A JP60138722A JP13872285A JPS61296800A JP S61296800 A JPS61296800 A JP S61296800A JP 60138722 A JP60138722 A JP 60138722A JP 13872285 A JP13872285 A JP 13872285A JP S61296800 A JPS61296800 A JP S61296800A
Authority
JP
Japan
Prior art keywords
electrode
design change
insulating layer
connection pad
cut
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60138722A
Other languages
English (en)
Other versions
JPH0440878B2 (ja
Inventor
金原　広治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60138722A priority Critical patent/JPS61296800A/ja
Priority to US06/875,670 priority patent/US4710592A/en
Priority to EP86108689A priority patent/EP0206337B1/en
Priority to DE8686108689T priority patent/DE3677417D1/de
Publication of JPS61296800A publication Critical patent/JPS61296800A/ja
Publication of JPH0440878B2 publication Critical patent/JPH0440878B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5382—Adaptable interconnections, e.g. for engineering changes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0292—Programmable, customizable or modifiable circuits having a modifiable lay-out, i.e. adapted for engineering changes or repair
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4076—Through-connections; Vertical interconnect access [VIA] connections by thin-film techniques
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は配線基板上に形成される設計変更用電極に関す
る。
〔従来の技術〕
従来の多層配線基板における設計変更用！極の一例が、
ＩＢＭ　Ｊ、ＲＥ８．ＤＥＶＥＬＯＰ、ＶＯＬ、２６゜
先１．ＪＡＮ、１９８２の第３０頁〜第３６頁に所載の
Ａ、Ｊ、Ｂｌｏｄｇｅｔｔ等の“Ｔｅｒｍａｌ　Ｃｏｎ
ｄｕｃｔｉｏｎＭｏｄｕｌｅ　：　Ａ　Ｈｉｇｈ−Ｐｅ
ｒｆｏｒｍａｎｃｅ　Ｍａｌ　ｔ　ｉ　ｌａｙｅｒＣｅ
ｒａｍｉｃ　Ｐａｃｋａｇｅ”と題す石論文に、開示さ
れている。第３図はこのような電極を示す。この電極は
、集積回路チップまたはワイヤー（導電線）を接続する
接続部分３１と、設計変更時にパッド間を切シ離す切断
部分３２とから構成され、各部分３１および３２は層構
成も導体材料も同じであ）、構造上の差異はない。基板
上にこのような電極が形成されたあと、この電極および
他の必要部分を残して、絶縁膜によシ基板上が覆われる
。
〔発明か解決しようとする問題点〕
上述した従来の電極構造では、チップやワイヤーを半田
づけするときには、基板上の配線パターンに半田か流れ
ないよう設計変更電極上にソルダーダムを設ける必要が
ある。すなわち、電極形成後、ちらにソルダーダム形成
工程が必璧となる。
ソルダーダム形成工程では、パターン化、硬化および焼
成等の処理が必要であるため、設計震災電極の表面を酸
化物等を生じない金属で形成しなけれはならす、この結
果、半田ぬれ性や切断性を十分に満足する材料だけで電
極を形成することができないという欠点かある。
〔問題点を解決するだめの手段〕
本発明の電極は、基板上に形成した電極部と、該電極部
を少なくとも２つの部分に切断できるように該電極部の
一部を紐出させて該電極部を扱う絶縁層と、それぞれ前
記２つの部分に対向する前記絶縁層上の対応位置に形成
した少なくとも２つの接続用パッドと、前記接続用パッ
ドと前記電極部とを接続するよう前記絶縁〜を貫通する
ピアホールとから構成もれる。
〔実施例〕
次に本発明について図面を参照して詳細に説明する０ 第１図を参照すると、本発明の一実施例は、内部に各種
の配線パターン（図示せず）を有する配線層部（基板）
１１と、配線層部１１上に形成され配線部分１２および
切断部分１３からなる電極部１９と、電極部１９を２つ
の部分に切断できるように電極部１９の切断部分１３を
紐出させて電極部１９を覆う絶縁層１４と、配線部分１
２に対向する絶縁層１４上の対応位置に形成した２つの
接続用パッド１８と、燐続用パッド１８と配線部分１２
とを電気的に接続するよう絶に層１４を貫通するピアホ
ール１６と、前記各種の配線パターンの一部と配線部分
１２とを電気的に接続するピアホール１７とから構成さ
れる。設計変更時には、電極部１９は、露出部１５を介
して超音波カッタやレーザー光線等により切断部分１３
で切断できる。電極部１９は、電気抵抗の低減および切
断の容易性を考慮して、スパッタリングによシ形成され
たクロムおよびパラジウム膜上に金をめっきすることに
よりｍ成される。パッド１８は、半田ぬれ性を考慮し１
、スパッタリングにより形成されたクロム、パラジウム
および銅膜上に半田ぬれ性のよい銅をめっきすることに
より構成される。この方法では、銅層の形成か多層化の
最終工程となるため、銅の酸化等は全く発生しない。本
実施例では、絶縁層１４かソルダーダムとして＠き、半
田か他の配線パターンに流れるのを阻止している。
第２図を参照すると、本発明の第２の実施例の断面図を
第２図に示す。２１から２７は、接続用パッド２８の構
成以外は第１の実施例と全同じ構成である。パッド２８
は、クロム・パラジウム・銅スパッタ膜の上に銅・ニッ
ケル・金の多層めっきを行なうことによシ形成され、接
続用パッドを酸化等から保護している。本実施例でも、
電極の形成か多層化の最終工程となるため、金の熱拡散
。
熱Ｉ＃Ｉ＆率の遠いによる多層めっき間での剥れ等は全
く生じない。
〔発明の効果〕
以上、＆明した↓うに、本発明は設計変更！極のチップ
およびワイヤー接続部を最上場に形成し、配線部分やパ
ターン切断部分をパッドの下に絶縁層を介し１形成する
ことによシ、接続性や切断性に対し１それぞれすぐれた
性質をもった金属を使っ１設計変Ｊｌ！電極を形成でき
るという効果がある。
【図面の簡単な説明】
第１図は本発明σノ第１の実施例の断面図、第２図は本
発明の第２の実施例の断面図および第３図１従来例を示
す斜視図である。 図において、１１・・・・・・基板、１２・・・・・・
配縁部分、１３・・・・・・切断部分、１４・・・・・
・絶縁層、１５・・・・・・露出部、１６・・・・・・
ピアホール、１７・・・・・・ピアホール、１８・・・
・・・パッド、２８・・・・・・パッド、３１・・・・
・・接続部％３２・・・・・・切断部。　　　　　　　
　　　ｙ−＝１、代理人　弁理士　　内　原　　　晋／
”　　　’。 茅　ｌ　閃 ＄　２　図

Claims (4)

    【特許請求の範囲】
  1. （１）配線基板上に形成される設計変更用電極において
    、前記基板上に形成した電極部と、該電極部を少なくと
    も２つの部分に切断できるように該電極部の一部を露出
    させて該電極部を覆う絶縁層と、それぞれ前記２つの部
    分に対向する前記絶縁層上の対応位置に形成した少なく
    とも２つの接続用パッドと、前記接続用パッドと前記電
    極部とを接続するよう前記絶縁層を貫通するビアホール
    とから構成したことを特徴とする設計変更用電極。
  2. （２）前記接続用パッドと、前記切断部分とを異なる導
    電材料より形成したことを特徴とする特許請求の範囲第
    （１）項記載の設計変更用電極。
  3. （３）前記接続用パッドが銅を含むことを特徴とする特
    許請求の範囲第（１）項記載の設計変更用電極。
  4. （４）前記接続用パッドの表面の材料が貴金属であるこ
    とを特徴とする特許請求の範囲第（３）項記載の設計変
    更用電極。
JP60138722A 1985-06-25 1985-06-25 設計変更用電極 Granted JPS61296800A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP60138722A JPS61296800A (ja) 1985-06-25 1985-06-25 設計変更用電極
US06/875,670 US4710592A (en) 1985-06-25 1986-06-18 Multilayer wiring substrate with engineering change pads
EP86108689A EP0206337B1 (en) 1985-06-25 1986-06-25 Multilayer wiring substrate with engineering change pads
DE8686108689T DE3677417D1 (de) 1985-06-25 1986-06-25 Mehrschichtleitersubstrat mit kontaktflecken zum aendern von verbindungen.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60138722A JPS61296800A (ja) 1985-06-25 1985-06-25 設計変更用電極

Publications (2)

Publication Number Publication Date
JPS61296800A true JPS61296800A (ja) 1986-12-27
JPH0440878B2 JPH0440878B2 (ja) 1992-07-06

Family

ID=15228614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60138722A Granted JPS61296800A (ja) 1985-06-25 1985-06-25 設計変更用電極

Country Status (4)

Country Link
US (1) US4710592A (ja)
EP (1) EP0206337B1 (ja)
JP (1) JPS61296800A (ja)
DE (1) DE3677417D1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0271590A (ja) * 1988-09-06 1990-03-12 Mitsubishi Electric Corp ハイブリッドｉｃ用基板
JPH04132292A (ja) * 1990-09-21 1992-05-06 Nec Corp ポリイミド樹脂多層配線基板

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FR2650471B1 (fr) * 1989-07-27 1991-10-11 Bull Sa Procede de formation de piliers du reseau multicouche d'une carte de connexion d'au moins un circuit integre de haute densite
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US5060116A (en) * 1990-04-20 1991-10-22 Grobman Warren D Electronics system with direct write engineering change capability
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US5162792A (en) * 1990-08-03 1992-11-10 American Telephone And Telegraph Company On-the-fly arrangement for interconnecting leads and connectors
US5220490A (en) * 1990-10-25 1993-06-15 Microelectronics And Computer Technology Corporation Substrate interconnect allowing personalization using spot surface links
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US5155302A (en) * 1991-06-24 1992-10-13 At&T Bell Laboratories Electronic device interconnection techniques
US5917229A (en) * 1994-02-08 1999-06-29 Prolinx Labs Corporation Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect
US5813881A (en) * 1994-02-08 1998-09-29 Prolinx Labs Corporation Programmable cable and cable adapter using fuses and antifuses
US5537108A (en) * 1994-02-08 1996-07-16 Prolinx Labs Corporation Method and structure for programming fuses
US5572409A (en) * 1994-02-08 1996-11-05 Prolinx Labs Corporation Apparatus including a programmable socket adapter for coupling an electronic component to a component socket on a printed circuit board
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US5808351A (en) * 1994-02-08 1998-09-15 Prolinx Labs Corporation Programmable/reprogramable structure using fuses and antifuses
US5834824A (en) * 1994-02-08 1998-11-10 Prolinx Labs Corporation Use of conductive particles in a nonconductive body as an integrated circuit antifuse
US5962815A (en) * 1995-01-18 1999-10-05 Prolinx Labs Corporation Antifuse interconnect between two conducting layers of a printed circuit board
US5906042A (en) * 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
US5767575A (en) * 1995-10-17 1998-06-16 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
JP2776365B2 (ja) * 1996-04-04 1998-07-16 日本電気株式会社 多段接続型半導体用キャリヤーとそれを用いた半導体装置、及びその製造方法
US5872338A (en) * 1996-04-10 1999-02-16 Prolinx Labs Corporation Multilayer board having insulating isolation rings
US6307162B1 (en) 1996-12-09 2001-10-23 International Business Machines Corporation Integrated circuit wiring
US6034427A (en) * 1998-01-28 2000-03-07 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
US6013952A (en) * 1998-03-20 2000-01-11 Lsi Logic Corporation Structure and method for measuring interface resistance in multiple interface contacts and via structures in semiconductor devices
JP3502800B2 (ja) * 1999-12-15 2004-03-02 新光電気工業株式会社 半導体装置の製造方法
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JPH04132292A (ja) * 1990-09-21 1992-05-06 Nec Corp ポリイミド樹脂多層配線基板

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Publication number Publication date
EP0206337B1 (en) 1991-02-06
US4710592A (en) 1987-12-01
EP0206337A3 (en) 1987-03-04
DE3677417D1 (de) 1991-03-14
JPH0440878B2 (ja) 1992-07-06
EP0206337A2 (en) 1986-12-30

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