JP2767978B2 - はんだパッドの製造方法とはんだパッド - Google Patents

はんだパッドの製造方法とはんだパッド

Info

Publication number
JP2767978B2
JP2767978B2 JP2140403A JP14040390A JP2767978B2 JP 2767978 B2 JP2767978 B2 JP 2767978B2 JP 2140403 A JP2140403 A JP 2140403A JP 14040390 A JP14040390 A JP 14040390A JP 2767978 B2 JP2767978 B2 JP 2767978B2
Authority
JP
Japan
Prior art keywords
solder
layer
solder pad
wettability
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2140403A
Other languages
English (en)
Other versions
JPH0433347A (ja
Inventor
東夫 反町
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2140403A priority Critical patent/JP2767978B2/ja
Publication of JPH0433347A publication Critical patent/JPH0433347A/ja
Application granted granted Critical
Publication of JP2767978B2 publication Critical patent/JP2767978B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/03828—Applying flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05019—Shape in side view being a non conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔概要〕 はんだパッドの製造方法とはんだパッドに関し、 はんだパッドの強度を上げ、電気的，機械的接続の信
頼性を向上することを目的とし、 基板上に導体層を形成する工程と、前記導体層上には
んだ拡散防止層とはんだ濡れ性のよい金属層とを形成す
る工程と、前記はんだ濡れ性のよい金属層上にはんだ融
着窓をあけたはんだ濡れ性の悪い絶縁層を形成する工程
と、前記はんだ融着窓に露出した前記はんだ濡れ性のよ
い金属層にはんだを融着して合金層を形成する工程とを
少なくとも含むようにはんだパッドの製造方法を構成
し、さらに、その製造方法によりはんだパッドを形成す
る。
〔産業上の利用分野〕
本発明ははんだパッド、とくに、セラミック多層配線
基板などにおいて、フリップチップICの実装，基板上の
ワイヤ接続，他回路とのワイヤ接続等に用いられる高信
頼度のはんだパッドの改良にに関する。
〔従来の技術〕
第３図は従来のはんだパッドの例を示す図で、薄膜２
層配線回路基板の場合について示したものである。
同図（イ）の断面図でその構造の概要を説明すると、
１は基板，たとえば、アルミナセラミック板またはガラ
スセラミック板で、その上に導体配線層2,たとえば、Cr
/Cu/Crの３層薄膜を所要の回路配線パターンにホエッチ
ングして形成されている。３は絶縁層で，たとえば、ポ
リイミド樹脂層である。４は導体層で，たとえば、Cu/C
rの２層薄膜からなり、必要に応じて絶縁層３にスルー
ホールをあけて導体配線層２との導通を取るように形成
する。５ははんだ拡散防止層で，たとえば、Ni層で下層
のCuと上層のはんだとの反応バリヤとてして機能する。
60は合金層で，予め、はんだ拡散防止層５の上に形成し
ておいたはんだ濡れ性のよい金属層（たとえば、Auな
ど）とはんだとの合金層で、図には破線で境界を示して
あるが実際には必ずしも明確な境界を形成しているとは
限らない。80ははんだ層である。このようにして形成さ
れたはんだ層80からワイヤボンディングその他適当な方
法により，たとえば、他回路などへの電気的および機械
的接続を行っている。
〔発明が解決しようとする課題〕
しかし、上記従来のはんだパッドでははんだ層80に力
Ｐが加わると、はんだバッドの周辺部〔第３図（ロ）の
矢印Ｃ部〕に集中的に力がかゝり局部的に剥離が始ま
る。一度このような剥離が始まると、急速にはんだパッ
ドは不安定となり全体が基板からはずれてしまうという
重大な問題がありその解決が必要であった。
〔課題を解決するための手段〕
上記の課題は、基板１上に導体層４を形成する工程
と、前記導体層４上にはんだ拡散防止層５とはんだ濡れ
性のよい金属層６とを形成する工程と、前記はんだ濡れ
性のよい金属層６上にはんだ融着窓70をあけたはんだ濡
れ性の悪い絶縁層７を形成する工程と、前記はんだ融着
窓70に露出した前記はんだ濡れ性のよい金属層６にはん
だを融着して合金層60を形成する工程とを少なくとも含
むはんだパッドの製造方法と、それによって形成された
はんだパッドにより解決することができる。
〔作用〕
本発明によれば、はんだ濡れ性のよい金属層６の上
に、はんだ融着窓70をあけたはんだ濡れ性の悪い絶縁層
７を設けているので、はんだ層80を形成する際にはんだ
濡れ性の悪い絶縁層７の下部に隠れている部分のはんだ
濡れ性のよい金属層６でも合金層60が導体層４のエッジ
部を覆うように形成される。したがって、はんだ層80に
力が加わっても、従来例のごとくはんだバッドの周辺部
（矢印Ｃ部）に集中的に力がかゝることがなく，しか
も、はんだパッドの周辺部全体が絶縁層７で覆われてい
るので、耐剥離力は極めて大きくはんだパッドの剥離は
生じないのである。
〔実施例〕
第１図は本発明の実施例を示す断面図である。
図中、７ははんだ濡れ性の悪い絶縁層で，たとえば、
ポリイミド樹脂層である。はんだ濡れ性の悪い絶縁層７
にははんだパッドとなる部分にはんだが融着して合金化
できるようにはんだ融着窓70を，たとえば、ホトリソグ
ラフィ技術により孔明けする。
なお、前記の図面で説明したものと同等の部分につい
ては同一符号を付し、かつ、同等部分についての説明は
省略する。図では合金層60の境界として破線で示してあ
るが、実際には必ずしも明確な境界を形成しているとは
限らない。
図からわかるように、本実施例でははんだパッドの周
辺部を絶縁層７が覆っており、矢印Ｃで示したコーナ部
分だけに力が集中的にかゝることがなく，しかも、はん
だパッドの周辺部全体が絶縁層７で覆われているので、
そこに押え力が働きはんだパッドの耐剥離力は極めて大
きくなる。
たとえば、はんだ層80に水平に力Ｐを加える，いわゆ
る、横押し試験を実施したところ、従来例では300gの力
で約10％程度のはんだパッドが剥離したのに対して、本
実施例の場合400〜500gの力を加えても剥離するものが
なくその効果は極めて顕著であった。
第２図は本発明実施例の製造工程の例を示す図で、具
体的に本発明のはんだパッドを作成するための主な工程
を以下に順次説明する。
工程（１）：基板1,たとえば、厚さ1mm,大きさ120×100
mmのアルミナセラミック板やガラスセラミック板の上に
連続スパッタ法によりCr/Cu/Crの３層の導体配線層２を
形成する。導体配線層２の厚さは基板１に接している下
の方から順に、Cr:100nm,Cu:5μm,Cr:100nm程度とす
る。導体配線層２のパターニングは公知のホトエッチン
グ技術を用いて所要のパターンに形成する。
次に、絶縁層３として10μｍの厚さに感光性のポリイ
ミド樹脂層をスピンコートし、導体配線層２の所要箇所
に，同じく公知のホトリソグラフィ技術によりスルーホ
ールを形成する。次いで、Cu:5μm/Cr:100nmの２層膜か
らなる導体層４を連続スパッタにより形成して、前記絶
縁層３のスルーホールを介して導体配線層２と接続して
はんだパッドとなる部分を形成する。
工程（２）：前記処理基板のはんだパッドとなる部分の
導体層４の領域に、はんだ拡散防止層5,たとえば、厚さ
３μｍのNi層と、はんだ濡れ性のよい金属層6,たとえ
ば、厚さ１μｍのAu層とを，たとえば、連続めっき法で
形成する。
工程（３）：上記処理基板の上に絶縁層7,たとえば、感
光性のポリイミド樹脂を約５〜10μｍの厚さにスピンコ
ートし、はんだパッドとなる部分のはんだ濡れ性のよい
金属層６の上に，たとえば、直径約300μｍφの大きさ
のはんだ融着窓70をホトエッチングにより形成する。こ
のとき、導体層４の周辺部の縁から絶縁層７の内縁が20
μｍ程度内側にはみ出すように、相互の大きさを適宜設
定して形成する。
工程（４）：上記処理基板のはんだ融着窓70にフラック
ス９と、直径約300μｍの，たとえば、60％Sn−40％Pb
からなるはんだボール８を公知の方法で塗布および散布
する。
工程（５）：上記処理基板を，たとえば、ベーパフェー
ズ・リフロー炉に入れ220℃に加熱する。
はんだボール８が融解するとはんだ濡れ性のよい金属
層６と反応し合金層60を形成する。合金層60は絶縁膜７
の下の部分の金属層６とも容易に反応して一体の合金層
となり、本発明のはんだパッドを形成される。
上記実施例では導体回路パターンは２層の場合につい
て説明したが、３層以上の多層導体回路パターンを形成
する場合のはんだパッドにも適用できることは勿論であ
る。
また、基板１は通常のプリント配線基板の場合にも本
発明が適用できることは言うまでもない。
なお、上記実施例は一例を示したものであり、本発明
の趣旨に添うものであれば、使用する素材やそれらの組
み合わせ，あるいは、各部分の構成や製造プロセスなど
は適宜最適なものを選択使用してよいことは言うまでも
ない。
〔発明の効果〕 以上述べたように、本発明によれば、はんだ濡れ性の
よい金属層６の上に、はんだ融着窓70をあけたはんだ濡
れ性の悪い絶縁層７を設けているので、はんだ層80を形
成する際にはんだ濡れ性の悪い絶縁層７の下部に隠れて
いる部分のはんだ濡れ性のよい金属層６部分でも、合金
層60が導体配線層４のエッジ部を覆うように形成され
る。したがって、はんだ層80に力が加わっても、従来例
のごとくはんだバッドの周辺部（矢印Ｃ部）に集中的に
力がかゝることがなく，しかも、はんだパッドの周辺部
全体が絶縁層７で覆われているので、耐剥離力は極めて
大きくはんだパッドの剥離が生じることはなく、はんだ
パッドの品質および信頼性の向上に寄与するところが極
めて大きい。
【図面の簡単な説明】
第１図は本発明の実施例を示す断面図、 第２図は本発明実施例の製造工程の例を示す断面図、 第３図は従来のはんだパッドの例を示す断面図である。 図において、 １は基板、 ２は導体配線層、 3,7は絶縁層、 ４は導体層、 ５ははんだ拡散防止層、 ６ははんだ濡れ性のよい金属層、 ８ははんだボール、 60は合金層、 70ははんだ融着窓、 80ははんだ層である。

Claims (2)

    (57)【特許請求の範囲】
  1. 【請求項１】基板（１）上に導体層（４）を形成する工
    程と、 前記導体層（４）上にはんだ拡散防止層（５）とはんだ
    濡れ性のよい金属層（６）とを形成する工程と、 前記はんだ濡れ性のよい金属層（６）上にはんだ融着窓
    （70）をあけたはんだ濡れ性の悪い絶縁層（７）を形成
    する工程と、 前記はんだ融着窓（70）に露出した前記はんだ濡れ性の
    よい金属層（６）にはんだを融着して合金層（60）を形
    成する工程とを少なくとも含むことをことを特徴とした
    はんだパッドの製造方法。
  2. 【請求項２】請求項（１）記載のはんだパッドの製造方
    法により形成されたことを特徴とするはんだパッド。
JP2140403A 1990-05-30 1990-05-30 はんだパッドの製造方法とはんだパッド Expired - Lifetime JP2767978B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2140403A JP2767978B2 (ja) 1990-05-30 1990-05-30 はんだパッドの製造方法とはんだパッド

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2140403A JP2767978B2 (ja) 1990-05-30 1990-05-30 はんだパッドの製造方法とはんだパッド

Publications (2)

Publication Number Publication Date
JPH0433347A JPH0433347A (ja) 1992-02-04
JP2767978B2 true JP2767978B2 (ja) 1998-06-25

Family

ID=15267959

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2140403A Expired - Lifetime JP2767978B2 (ja) 1990-05-30 1990-05-30 はんだパッドの製造方法とはんだパッド

Country Status (1)

Country Link
JP (1) JP2767978B2 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0739034B2 (ja) * 1990-11-14 1995-05-01 株式会社日立製作所 半導体素子のフラックス塗布方法
US20130341785A1 (en) * 2012-06-22 2013-12-26 Lei Fu Semiconductor chip with expansive underbump metallization structures

Also Published As

Publication number Publication date
JPH0433347A (ja) 1992-02-04

Similar Documents

Publication Publication Date Title
US4463059A (en) Layered metal film structures for LSI chip carriers adapted for solder bonding and wire bonding
US6395993B1 (en) Multilayer flexible wiring boards
JP3262497B2 (ja) チップ実装回路カード構造
JP3300839B2 (ja) 半導体素子ならびにその製造および使用方法
JP3320979B2 (ja) デバイスをデバイス・キャリヤ上に直接実装する方法
JP4685834B2 (ja) 集積回路デバイス
JPH02272737A (ja) 半導体の突起電極構造及び突起電極形成方法
JP2000299337A (ja) 半導体装置及びその製造方法
US6485843B1 (en) Apparatus and method for mounting BGA devices
US7057294B2 (en) Semiconductor device
JP2833642B2 (ja) 多層配線基板及びその製造方法
JP2767978B2 (ja) はんだパッドの製造方法とはんだパッド
EP0262580A2 (en) Method of electrically bonding two objects
JP4002117B2 (ja) 多層基板及びその製造方法
JPH03218644A (ja) 回路基板の接続構造
JPH0529363A (ja) 配線基板
JPH0684916A (ja) 多層バンプ
JPH07240434A (ja) バンプ電極、およびその製造方法
JPH05144821A (ja) 半導体装置
JP2000294675A (ja) チップキャリア及び半導体装置並びにチップキャリアの製造方法
JP7382167B2 (ja) 電子装置、および電子装置の製造方法
JP5482170B2 (ja) 半導体装置、半導体装置の製造方法、回路基板及び回路基板の製造方法
JPH11307688A (ja) 配線基板及びその製造方法
JP3615628B2 (ja) 半導体チップの製造方法及びその実装方法
JPH03268385A (ja) はんだバンプとその製造方法