JPH0433347A - はんだパッドの製造方法とはんだパッド - Google Patents

はんだパッドの製造方法とはんだパッド

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Publication number
JPH0433347A
JPH0433347A JP2140403A JP14040390A JPH0433347A JP H0433347 A JPH0433347 A JP H0433347A JP 2140403 A JP2140403 A JP 2140403A JP 14040390 A JP14040390 A JP 14040390A JP H0433347 A JPH0433347 A JP H0433347A
Authority
JP
Japan
Prior art keywords
solder
layer
wettability
insulating layer
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2140403A
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English (en)
Other versions
JP2767978B2 (ja
Inventor
Haruo Tanmachi
東夫 反町
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
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Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2140403A priority Critical patent/JP2767978B2/ja
Publication of JPH0433347A publication Critical patent/JPH0433347A/ja
Application granted granted Critical
Publication of JP2767978B2 publication Critical patent/JP2767978B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［概要］ はんだバンドの製造方法とはんだパットに関し、はんだ
パッドの強度を上げ、電気的２機械的接続の信転性を向
上することを目的とし、基板上に導体層を形成する工程
と、前記導体層上にはんだ拡散防止層とはんだ濡れ性の
よい金属層とを形成する工程と、前記はんだ濡れ性のよ
い金属層上にはんだ融着窓をあけたはんだ濡れ性の悪い
絶縁層を形成する工程と、前記はんだ融着窓に露出した
前記はんだ濡れ性のよい金属層にはんだを融着して合金
層を形成する工程とを少なくとも含むようにはんだパッ
ドの製造方法を構成し、さらに、その製造方法によりは
んだバンドを形成する。
〔産業上の利用分野〕
本発明ははんだバンド、とくに、セラミンク多層配線基
板などにおいて、フリップチンプＩＣの実装、基板上の
ワイヤ接続、他回路とのワイヤ接続等に用いられる高信
鎖度のはんだバンドの改良にに関する。
〔従来の技術〕
第３図は従来のはんだパッドの例を示す図で、薄膜２層
配線回路基板の場合について示し７たものである。
同図（イ）の断面図でその構造の概要を説明すると、１
は基板、たとえば、アルミナセラミンク板またはガラス
セラミック板で、その上に導体配線層２．たとえば、Ｃ
ｒ／Ｃｕ／Ｃｒの３層薄膜を所要の回路配線パターンに
ホエッチングして形成されている。３は絶縁層で、たと
えば、ポリイミド樹脂層である。４は導体層で、たとえ
ば、Ｃｕ／Ｃｒの２層薄膜からなり、必要に応して絶縁
層３にスルーホールをあけて導体配線層２との導通を取
るように形成する。５ははんだ拡散防止層で、たとえば
、Ｎｉ層で下層のＣｕと上層のはんだとの反応バリヤと
てして機能する。６０は合金層で、予め、はんだ拡散防
止層５の上に形成しておいたはんだ濡れ性のよい金属層
（たとえば、Ａｕなど）とはんだとの合金層で、図には
破線で境界を示しであるが実際には必ずしも明確な境界
を形成しているとは限らない。８０ははんだ層である。
このようにして形成されたはんだ層８０からワイヤボン
ディングその他適当な方法により、たとえば、他回路な
どへの電気的および機械的接続を行っている。
〔発明が解決しようとする課題］ しかし、上記従来のはんだパッドでははんだ層８０に力
Ｐが加わると、はんだハントの周辺部〔第３図（ロ）の
矢印Ｃ部〕に集中的に力がか＼り局部的に剥離が始まる
。−度このような剥離が始まると、急速にはんだパッド
は不安定となり全体が基板からはずれてしまうという重
大な問題がありその解決が必要であった。
〔課題を解決するための手段〕
上記の課題は、基板１上に導体層４を形成する工程と、
前記導体層４上にはんだ拡散防止層５とはんだ濡れ性の
よい金属層６とを形成する工程と、前記はんだ濡れ性の
よい金属層６上にはんだ融着窓７０をあけたはんだ濡れ
性の悪い絶縁層７を形成する工程と、前記はんだ融着窓
７０に露出した前記はんだ濡れ性のよい金属層６にはん
だを融着して合金層６０を形成する工程とを少なくとも
含むはんだバットの製造方法と、それによって形成され
たはんだパッドにより解決することができる。
［作用］ 本発明によれば、はんだ濡れ性のよい金属層６の上に、
はんだ融着窓７０をあけたはんだ濡れ性の悪い絶縁層７
を設けているので、はんだ層８０を形成する際にはんだ
濡れ性の悪い絶縁層７の下部に隠れている部分のはんだ
濡れ性のよい金属層６でも合金層６０が導体層４のエツ
ジ部を覆うように形成される。したがって、はんだ層８
０に力が加わっても、従来例のごとくはんだパッドの周
辺部（矢印Ｃ部）に集中的に力がか＼ることかなく、シ
かも、はんだパッドの周辺部全体が絶縁層７で覆われて
いるので、耐剥離力は極めて大きくはんだバラ１”の剥
離は生じないのである。
〔実施例〕
第１図は本発明の実施例を示す断面図である。
図中、７ははんだ濡れ性の悪い絶縁層で、たとえば、ポ
リイミド樹脂層である。はんだ濡れ性の悪い絶縁層７に
ははんだバットとなる部分にはんだが融着して合金化で
きるようにはんだ融着窓７０を、たとえば、ホトリソグ
ラフィ技術により孔明けする。
なお、前記の図面で説明したものと同等の部分について
は同一符号を付し、かつ、同等部分についての説明は省
略する。図では合金層６０の境界として破線で示しであ
るが、実際には必ずしも明確な境界を形成しているとは
限らない。
図かられかるように、本実施例でははんだバンドの周辺
部を絶縁層７が覆っており、矢印Ｃで示したコーナ部分
だけに力が集中的にが−ることかな（、シかも、はんだ
バンドの周辺部全体が絶縁層７で覆われているので、そ
こに押え力が働きはんだパッドの耐剥離力は極めて大き
くなる。
たとえば、はんだ層８０に水平に力Ｐを加える。
いわゆる、横押し試験を実施したところ、従来例では３
００ｇの力で約１０χ程度のはんだバ・ンドが剥離した
のに対して、本実施例の場合４００〜５００ｇの力を加
えても剥離するものがなくその効果は極めて顕著であっ
た。
第２図は本発明実施例の製造工程の例を示す図で、具体
的に本発明のはんだバンドを作成するための主な工程を
以下に順次説明する。
工程（１）二基板１．たとえば、厚さ１ｍｍ、大きさ１
２０　Ｘ１００　ｍｍのアルミナセラミック板やガラス
セラミック板の上に連続スパンタ法によりＣｒ／Ｃｕ／
Ｃｒの３層の導体配線層２を形成する。導体配線層２の
厚さは基板１に接している下の方から順に、Ｃｒ：１０
０ｎ　ｒｎ、　Ｃｕ：５μｍ、　Ｃｒ：１００ｎ　ｍ程
度とする。
導体配線層２のバターニングは公知のホトエンチング技
術を用いて所要のパターンに形成する。
次に、絶縁層３として１０μｍの厚さに感光性のポリイ
ミド樹脂層をスピンコードし、導体配線層２の所要箇所
に、同じく公知のホトリソグラフィ技術によりスルーホ
ールを形成する。次いで、Ｃｕ：５μｍ／　Ｃｒ：１０
０ｎ　ｍの２層膜からなる導体層４を連続スパッタによ
り形成して、前記絶縁層３のスルーホールを介して導体
配線層２と接続してはんだパッドとなる部分を形成する
。
工程（２）：前記処理基板のはんだパッドとなる部分の
導体層４の領域に、はんだ拡散防止層５．たとえば、厚
さ３μｍのＮｉ層と、はんだ濡れ性のよい金属層６．た
とえば、厚さ１μｍのＡｕ層とを、たとえば、連続めっ
き法で形成する。
工程（３）：上記処理基板の上に絶縁層７．たとえば、
感光性のポリイミド樹脂を約５〜１０μｍの厚さにスピ
ンコードし、はんだパッドとなる部分のはんだ濡れ性の
よい金属層６の上に、たとえば、直径約３００μｍφの
大きさのはんだ融着窓７０をホトエツチングにより形成
する。このとき、導体層４の周辺部の縁から絶縁層７の
内縁が２０μｍ程度内側にはみ出すように、相互の大き
さを適宜設定して形成する。
工程（４）：上記処理基板のはんだ融着窓７０にフラッ
クス９と、直径約３００μｍの、たとえば、６０？４Ｓ
ｎ−４０χｐｂからなるはんだボール８を公知の方法で
塗布および散布する。
工程（５）二上記処理基板を、たとえば、ヘーパフ工−
ズ・リフロー炉に入れ２２０°Ｃに加熱する。
はんだボール８が融解するとはんだ濡れ性のよい金属層
６と反応し合金層６０を形成する。合金層６０は絶縁膜
７の下の部分の金属層６とも容易に反応して一体の合金
層となり、本発明のはんだパッドを形成される。
上記実施例では導体回路パターンは２層の場合について
説明したが、３層以上の多層導体回路パターンを形成す
る場合のはんだパッドにも適用できることは勿論である
。
また、基板１は通常のプリント配線基板の場合にも本発
明が適用できることはごうまでもない。
なお、上記実施例は一例を示したものであり、本発明の
趣旨に添うものであれば、使用する素材やそれらの組み
合わせ、あるいは、各部分の構成や製造プロセスなどは
適宜最適なものを選択１吏用してよいことは言うまでも
ない。
〔発明の効果〕
以上述べたように、本発明によれば、はんだ濡れ性のよ
い金属層６の上に、はんだ融着窓７０をあけたはんだ濡
れ性の悪い絶縁層７を設けているので、はんだ層８０を
形成する際にはんだ濡れ性の悪い絶縁層７の下部に隠れ
ている部分のはんだ濡れ性のよい金属層６部分でも、合
金層６０が導体配線層４のエツジ部を覆うように形成さ
れる。したがって、はんだ層８０に力が加わっても、従
来例のごとくはんだパッドの周辺部（矢印Ｃ部）に集中
的に力がか＼ることかなく、シかも、はんだバンドの周
辺部全体が絶縁層７で覆われているので、耐剥離力は掻
めて大きくはんだパッドの剥離が生じることはなく、は
んだパッドの品質および信転性の向上に寄与するところ
が極めて大きい。
【図面の簡単な説明】
第１図は本発明の実施例を示す断面図、第２図は本発明
実施例の製造工程の例を示す面図、 第３図は従来のはんだパッドの例を示す断面である。 図において、 １は基板、 ２は導体配線層、 ３．７は絶縁層、 ４は導体層、 ５ははんだ拡散防止層、 ６ははんだ濡れ性のよい金属層、 ８ははんだボール、 ６０は合金層、 ７０ははんだ融着窓、 ８０ははんだ層である。

Claims (2)

    【特許請求の範囲】
  1. （１）基板（１）上に導体層（４）を形成する工程と、
    前記導体層（４）上にはんだ拡散防止層（５）とはんだ
    濡れ性のよい金属層（６）とを形成する工程と、前記は
    んだ濡れ性のよい金属層（６）上にはんだ融着窓（７０
    ）をあけたはんだ濡れ性の悪い絶縁層（７）を形成する
    工程と、 前記はんだ融着窓（７０）に露出した前記はんだ濡れ性
    のよい金属層（６）にはんだを融着して合金層（６０）
    を形成する工程とを少なくとも含むことをことを特徴と
    したはんだパッドの製造方法。
  2. （２）請求項（１）記載のはんだパッドの製造方法によ
    り形成されたことを特徴とするはんだパッド。
JP2140403A 1990-05-30 1990-05-30 はんだパッドの製造方法とはんだパッド Expired - Lifetime JP2767978B2 (ja)

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JPH0433347A true JPH0433347A (ja) 1992-02-04
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04182067A (ja) * 1990-11-14 1992-06-29 Hitachi Ltd 半導体素子のフラックス塗布方法
WO2013192054A1 (en) * 2012-06-22 2013-12-27 Advanced Micro Devices, Inc. Semiconductor chip with expansive underbump metallization structures

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04182067A (ja) * 1990-11-14 1992-06-29 Hitachi Ltd 半導体素子のフラックス塗布方法
JPH0739034B2 (ja) * 1990-11-14 1995-05-01 株式会社日立製作所 半導体素子のフラックス塗布方法
WO2013192054A1 (en) * 2012-06-22 2013-12-27 Advanced Micro Devices, Inc. Semiconductor chip with expansive underbump metallization structures

Also Published As

Publication number Publication date
JP2767978B2 (ja) 1998-06-25

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