TWI226662B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI226662B
TWI226662B TW092121261A TW92121261A TWI226662B TW I226662 B TWI226662 B TW I226662B TW 092121261 A TW092121261 A TW 092121261A TW 92121261 A TW92121261 A TW 92121261A TW I226662 B TWI226662 B TW I226662B
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TW
Taiwan
Prior art keywords
semiconductor
insulating sheet
sheet member
semiconductor device
semiconductor wafer
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TW092121261A
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English (en)
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TW200416850A (en
Inventor
Shigeo Tokumitsu
Satoshi Shimizu
Original Assignee
Renesas Tech Corp
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Publication of TW200416850A publication Critical patent/TW200416850A/zh
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Publication of TWI226662B publication Critical patent/TWI226662B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3164—Partial encapsulation or coating the coating being a foil
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    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/05599—Material
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
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    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/013—Alloys
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Wire Bonding (AREA)

Description

1226662 玖、發明說明 [發明所屬之技術領域] 本發明係關於半導體裝置，尤係關於防止切割時 發生之毛邊與導體配線之電氣短路者。 [先前技術] 於半導體裝置製造中，首先，係以半導體基板（晶 圓）狀態，在晶圓表面施以預定處理，以形成元件及 配線等。而於晶圓狀態完成應施的所有處理後，須沿 切割線（d i c i n g 1 i n e )將晶圓予以切割成各個半導體 晶片。 切割為各個的半導體晶片’將施以包含晶片接 合（die bonding)製程或引線接合（wire bonding)製 程等預定的封裝（package)處理，以完成半導體裝 置。 唯於沿切割線切割時，有使位於切割線區域的 導電性膜上翹狀者。為此，在進行引線接合時，引線 與該上翹導電性膜的部分接觸，有導致電氣短路的問 題。 為解決該問題，例如在日本專利“特開平1 Ο-ΐ 5 4 6 7 0 號”公 報及“ 特開平 1 1 - 2 0 4 5 2 5 號” 公報等 係提議，於進行切割前，先去除位於切割線區域的導 電性膜的製造方法。 若將位於切割線區域的導電性膜、在切割iii能 事先予以去除，則可使導電性膜無上翹現象，因而， 5 314871 1226662 得能防止因引線盘上翱道 士 ^ >、上遇導電性膜部分接觸而導致的
電氣短路。 J 但於上述半導體奘 篮式置之製造方法中，於曰 狀態附加去除切割線區$ ' J線£域導電性膜製程的問題。 [發明内容] 本發明係為解決上述 上入 门7^而作，係在於提供一種不雲 去除位於切割線區域導電 而 的半導體裝置為目的。 止包孔性短路 有關本發明的半導體裝置，係且備 體線，及絕緣片構件。半導 月丑Β日片，導 而抿Λ箱—-A V體日曰片係於半導體基板的主表 面幵y成預疋7〇件，及雷托立 Μ # A 和邛，且係於切割線區域留存導φ 性膜的狀態進行切刻 ^ ^ 去。 作業。因此’導體部係連接於電極部
者。而以絕緣片構件，、、儿 ^ 〇P 性膜部分者。 體曰曰片的周緣覆蓋殘存導電 因此，右依有關於本發明的半導 割線區域之導電性腺“ i ’置係、將位於切 割成半導體晶片後Γ，係以留存之狀態進行切
再將半導體晶片周緣之殘存導電性膜 部分，以絕緣片構件 r M .^ 牛予以後盍，因而，得使連接於電極邻 的導體線不與殘在道+ 电拉4 體裝置中之電氣短路膜直接接觸，故得以防止在半導 本發明的上试M甘a
Bl ^ 这及其他目的、特徵、局面以及其優點 則可由添付圖式夕 、彳炎點， 口八之下記關連說明得以了解。 f實施方式J J】實施形[ 31487] 6 1226662 炫將有關本發明第1貫施形態的半導體裝置製造方 法，及由該製造方法製造半導體裝置之狀況說明於後： 首先，在晶圓上完成為預定元件及配線等的形成晶圓 狀態之處理。此時，於晶圓上之切割線區域留存有形成配 線專的未去除狀態之導電性膜。 主丁碌葫圓；亍 如第2圖所示，係以保護層（passivati〇… 體晶片1。亦因 -------·，·、口又 /百、passivation) 膜8將半導體晶片i表面la予以覆蓋，且將連接於配線部 分之所謂“銲墊（b〇ndingpad)”電極部5露出。 又，在半導體晶片1的周緣部分，存在有因切割而殘 留在切割線區域之導電性膜上翹部分（毛邊）7。而該導電性 膜亦係為形成電極部5或配線（未圖示）等者。 A然後，如第1圖所示，為覆蓋半導體晶片1中之所定 一分，準備黏貼於半導體晶M i的絕緣片構件3。唁 :構件““才f，得適用樹脂系片材構件或橡膠崎 此时，係於絕緣片構件 S 1 κ如\ 人抑〜…卞守髖晶片1 4 σ刀的第1黏貼部分3a，黏貼於半導 部分的楚〇 & , 守體日日片1側面 刀的第2黏貼部分补，及黏貼於沿半 置表面la邱八1 τ守粒日日片1周緣你 r囬u邛分的第3黏貼部分氕。 其所謂的半導體晶片！側面，係 的晶圓剖面。 U切割日日®而露出 及第 其次，如第1及第2圖所示，留下第 3黏貼部》3c，將絕緣片構件3之第 2黏貼部分3b 】點貼部分3a 3J4871 7 1226662 黏貼於半導體晶片1背面lb。 再次’如第3及第4圖所示，將絕緣片構件3之第2 黏貼部分313黏貼於半導體晶片i側面。再如第5及第6 圖所示，將絕緣片構件3之第3黏貼部分3e黏貼於沿半導 體晶片1周緣位置表面1 a部分。 由此’可使殘留於半導體晶片i周緣部分的上翹毛邊 7’得由絕緣片構件3的第2黏貼部分讣及第3黏貼部分 其次’如第7圖所示，對設於半導體晶片i表面的電 進行導體配線9銲接，以將電極部5及所定的引線 框（未圖示）予以電氣連接。之後’將該半導體晶片】封裝 於所疋組件（package ·未圖示）完成為一 在上述半導體裝置之製造方法中，d置… F试 百先在日日®切割線 ::…不去除用以形成配線等的導電性膜 打切割作業，將半導體晶片i切出。 然後，對所切出的半導體晶片丨由半導體晶片丨的背 面1 b側黏貼預定的纟邑缕η错生 半導，曰η二象片構件3,而以絕緣片構件3覆蓋 表面二分；…側面及位於沿半導體晶"周緣的 膜之1二：使在半導體晶片1周、缘，因切割而有導電性 以絕缝產生殘留於㈣線區域，亦可將該毛邊7 、、’"彖片構件3加以覆蓋。由此纟 極部5後β u _此將導體配線9銲接於電 後’仔不使導體配線9與毛邊7直接接觸。 其結果’在半導體裝置中’可防止藉由毛邊7，將一 314871 8 1226662 方配線與另方配線形成電氣連接的短路狀態。目而，得以 提升半導體裝置之可靠性（信賴度）。 實施形態 么么將有關本發明第2實施形態之半導體裝置的製造方 法，及由該製造方法製造的半導體裝置說明如下： *如第8圖所示，首先與上述製造方法一樣，在晶圓切 割線區域，為形成配線等以殘留狀態施行不去除導電性膜 的切割作業，料導體晶片1切出。 言雕…、後，如第8圖所示，準備絕緣片構件3以覆蓋於半 ^ 曰日片1的預定部份之方法黏貼於半導體晶片，而該絕 彖片構件3的材質，得適用樹脂系片材構件或橡膠系片材 構件，且^ %、+、 ^ 逃’月b於線桿（wire bonding)中之銲接孰進行 溶解為宜。 … 此時’係於絕緣片構件3配設黏貼於半導體晶片1表 面1 a部分Μ | 、第黏貼部分3 a，及黏貼於半導體晶片1側 面部分的第2黏貼部分扑。 ^ 、 °弟8圖及第9圖所示，留下第2黏貼部分3b， 網1、絕緣片構# 主I 1干3之第1黏貼部分3a黏貼於半導體晶片i 衣面1 a。再» ^ 榮， 如弟10圖及第11圖所示，將絕緣片構件3之 弟2點貼叫八 、。丨刀3b黏貼於半導體晶片1的側面。 由此， 7 ,, ’可將殘留於半導體晶片1周緣部分的上翹毛邊 ;命、月構件3之第1黏貼部分3a及第2黏貼部分3b 卞以覆蓋。 再如第 ； __ 2圖所示，為將導體配線9接合於電極部5， 9 314871 1226662 將導體配線9的前端部分配置於電 第回^ 口F 5正上方。苴二分丄 3圖所示，以銲接導體配線9及命 ，、人如 位於泰枚立R c τ 电°部5時的熱量，脸 於电極部5正上方的絕緣片構件3 里將 以溶解而形成開口部12。 。为，予以破壞或加 a其次，如第U圖所示’通過形成於絕 口。"2,將導體配線9接合於電極部 丨的開 電連接於引線框(未圖示)。之後可將電極部5 於所定組㈣圖示)而完成為—半Si體晶片1封袭 上述半導體裝置的製造方法，係與第丨每> 〃 & 造方法-樣，在晶圓切割線區域I “形悲的製 成配線等的導電性膜之狀能去除而殘留用以形 i切出。 膜之狀‘％進仃切割作業，將半導體晶片 表面？：對於被切出的半導體晶片1從半導體晶片1的 表面la側黏貼所定絕緣 導體晶片1表面及側卜 ^緣片構件3覆蓋半 戏的Ξ二I :半導體晶片1周緣’即使有殘留於切割線區 因切割而產生上趣毛邊7的情況，亦可將該 毛邊7以矣巴緣片；q舜$ 豕乃構件3復盍。由此，將導體配線9合於電 極部5後，得不使導體配線9與毛邊7直接接觸。 其結果，在半導體裝置中，可防止藉由毛邊7，將一 方配線與另方配線形成電性連接的短路狀態。因而，得以 提升半導體裝置之可靠性（信賴度）。 隹 L成年來，隨著移動（mobile)式機器之發展， 對半V 兀件（半導體晶片）的封裝也要求小型化、薄型 314871 10 1226662 、。為響應該需求，有 半導體晶片厚度變薄， 之提案。 對半導體晶片施行研磨處理，以使 且累積複數個該半導體晶片的構成 t此’特以變形例說明累積第1實施形態中之黏貼絕 片構件的半導體晶片之半導體裝置於後： 如第 1 5 R自a - 、， _ m不’在有關該變形例的半導體裝置 "先係將由半導體晶片1背面1 b側黏貼有絕緣片 的-個半導體晶片1固定於晶片墊〃表面上。 …、後，將由其他半導體晶片2背面2b側黏貼有絕 緣片構件4的另_袖主道威 为個+導體晶片2固定於半導體晶片1 表面 la上。 人，以另一變形例，說明累積第2實施形態中之 黏貼有絕緣片構株屯 —豕乃稱仵的+導體晶片之半導體裝置如下： 圖所示，在有關該另一變形例的半導體裝 置中’百先係精由絕緣片構件6將由半導體晶片！前面 1“則黏貼有絕緣片構件3的一個半導體晶片i固定於 晶片墊1 1表面上。 然後’將由其他半導體晶片2表面2a側黏貼有絕 緣片構件4的另-個半導體晶片2固定於覆蓋半導體晶 片1表面1 a之絕緣片構件3上。 如上述，有關各變形例半導體裝置中，係分別將經 由薄型研磨且黏貼絕緣片構件3、4的半導體晶片卜2 予以累積，可達成半導體裝置的小型化、薄型化。 尤於第16圖所示之另一變形例的半導體裝置，係 314871 1226662 1 ¥ ’需要多餘的絕 15圖所示之變形例半 〇 於在晶片墊1 1上固定半導體晶片 緣片構件6，相對於此在有關第 導體裝置，即無需該絕緣片構件 即較另一變形例 數來作半導體裝 其結果，一變形例的半導體裝置， 的半導體裝置，得減少絕緣片構件的片 置。 =係就本發明的狀態予㈣述者。唯其僅係—種 -例之說明’並不為限定本發明之内容 =内容，係僅以附記於中請專利範圍各項之界定曰為及 [圖式簡單說明] 第1圖係表示有關本發明第丨實施形態之半導體裝 置製造方法一製程的斜視圖。 第2圖係表示該同一實施形態中，第1圖所示製程 的部分剖面圖。 1圖所示製程 3圖所示製程 3圖所示製程 5圖所示製程 第3圖係表示該同一實施形態中，第 後應進行製程的斜視圖。 第4圖係表示該同一實施形態中，第 的部分剖面圖。 第5圖係表示該同一實施形態中，第 後應進行製程的斜視圖。 第6圖係表示該同一實施形態中，第 的部分剖面圖。 第7圖係表示該同一實施形態中，第5圖所示製程 314871 Ϊ226662 後應進行製程的部分剖面圖。 第8圖係有關本發明第2實施形態之半導體裝置製 造方法一製程的斜視圖。 第9圖係表示該同一實施形態中，第8圖所示製程 的部分剖面圖。 第1 0圖係表示該同一實施形態中，第8圖所示製 程後應進行製程的斜視圖。 第11圖係表示該同一實施形態中，第i 〇圖所示製 程的部分剖面圖。 第12圖係表示該同一實施形態中，第11圖所示製 程後應進行製程的部分剖面圖。 第13圖係表示該同一實施形態中，第12圖所示製 程後應進行製程的部分剖面圖。 第14圖係表示該同—實施形態中，第13圖所示製 程後應進行製程的部分剖面圖。 第15圖係表示有關本發明各實施形態半導體裝置 之一變形例剖面圖。 弟1 6圖係表示有關 ^ ’關本發明各實施形態半導體裝置 之另種變形例剖面圖。 2a表面 第1黏貼部分 第3黏貼部分 1 ' 2 半導體晶片 3、4、6絕緣片構件 lb 、 2b背面 3 b 第2黏貼部分 314871 13 1226662 5 電極部 7 毛邊 8 保護層 9 導體配線 11 晶片塾 12 開口部 14 314871

Claims (1)

  1. I226662 拾、申請專利範圍： h —種半導體裝置，係具備： 於半導體基板主表面形成預定元件及電極部，且係 片切割線區域留存導電性膜狀態，予以切割的半導體晶 連接於上述電極部的導體配線，及 沿上述半導體晶片周緣，而覆蓋上述殘存導命 部分之絕緣片構件者。 ^ 如申請專利範圍第！項記載之半導體裝置，其中， 性膜 2. 、…上述絕緣片構件，係於上述半導體晶片背面、上 半導體晶片側面，及沿上述半導體晶片周緣位置的表面 部分位置配設成覆蓋狀態者。 3·如申請專利範圍第2項記載之半導體裝置，係具備：由 上边絕緣片構件覆蓋的多個上述半導體晶片，且將上述 多個半導體晶片予以堆積者。 4·如申μ專利範圍帛】項記載之半導體裝置，其中，上述 絕緣片構件係配設為覆蓋上述半導體晶片表面及上述 半導體晶片側面者。 1226662 多個半導體晶片予以堆積者。 7. 如申請專利範圍第4項記載之半導體裝置，係具備： 由上述絕緣片構件覆蓋的上述多個半導體晶片，且 將上述多個半導體晶片予以堆積者。 8. 如申請專利範圍第1項記載之半導體裝置，係具備： 由上述絕緣片構件覆蓋的上述多個半導體晶片，且 將上述多個半導體晶片予以堆積者。 16 314871
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