1274373 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種晶圓構裝結構，更特別地是一種利用晶圓對晶圓 的堆疊構裝結構。 【先前技術】 、 對於目前消費性電子產品高效能、多功及輕薄短小之趨勢，如何達成 • 高積集度、高密度及高可靠度之電子構裝型式，將主導未來產品之實際效 • 能與發展里程。因應電子構裝的發展趨勢，電子構裝之形式已由早期的插 腳式構裝方式(pin through hole)，演進至表面黏著型(surfaee m〇unting technology，SMT)，而為了符合電子元件晶片ι〇數增加之趨勢，晶片與基 板的接合也由打線接合(wire bonding)進展至目前陣列式(area ajTay)的覆晶 接^(flip-chip)形式。雖然以此方式可大幅增加單一構裝之效能，但是在尺 寸縮裝之能力上，卻面臨了發展之極限與瓶頸，因此堆疊構裝技術的發展 曰益重要，可視為未來的主流之一。 於發展堆疊構裝之前，system Gn ehip (SqC)被視為晶#組整合之解決 方案。目前，亦有甚多研究機構著手s〇c之發展。但經比較，屬於平面整 馨合之S〇C系統將導致整體晶片尺寸擴大甚多，且其光罩及為複雜，無論於 製程成本或產品趨勢上，其實仍有許多缺點。她之下，社體方向堆疊 之構裝技術，可有效地達成縮小尺寸及減短線路長度等優點。 /以堆且的方式可以分為晶片對晶片、晶圓對晶圓以及構裝對構裝三種 形式。在晶片對晶牌麵祕式係將完成線路之晶片切狀後，再進行 堆疊，裝。在此形式之構料，可以達到最高_之縮裝、最短之訊號路 徑、、最錄熱等優點。最高比例之縮裝，可在固定產品尺寸中，整合多種 •形式之晶片，以因應電子元件多功能及微小化之需求。此外，因本身晶片 裸路在外，有助於散熱，對於高功率之元件將可以改善其熱當機之缺點。 '1274373 但是此構裝方式之缺點在於測試不易，known good die之晶片不易取得， 因此構裝成本相對的會大幅的提升。 【發明内容】 鑒於上述之發明背景中，以堆疊晶片構裝結構所產生的種種問題，本 發，揭露一種以堆疊晶圓結構取代堆疊晶片結構，藉以增改善習知技術中 堆疊晶片構裝結構的成本問題，因此可財效地降低單位成本以及構裝元 件之應用。 本發明的目的在於’在每—晶圓上形成相同線路分佈的重分配層扣 distnbutKmlayer ; rdl)，並且以相同方向進行堆疊。 本發_目的’藉由電鍍的方式將導線填充於堆叠晶_貫孔内，藉 以導通上下每一個晶圓的電路。 ，據以上所述之目的’本發明揭露—種堆疊晶關裝結構及其形成方 法、、堆豐晶圓構裝結構包含：具有重分配層之第—晶圓；具有斑第一曰 圓相同線路分佈方向之重分配層之第二晶圓層置放 了: ，、中《亥堆疊晶圓的主動面向上或是向下置放。 據;t述種種之目的，本發明還揭露—種形成堆疊晶_方法，复方 膠接合形成-堆叠晶圓結構;接著，於上述堆 接者 電路’根據堆疊晶圓結構上的切騎將堆叠晶圓結構分開 ^ 相同線路分佈的堆疊Μ結構；接著，將其中之 面朝上’其背面置放在具有導電膠之基板上；接著執行—回 '1274373 ，在本發明的另—個實施例係將切割後的另—個堆疊晶圓結構， 將，、主動2朝下，並且置放在具有«膠之基板上，_地進行-回銲步 驟·Γ使仔導電膠可以黏附在主動面朝基板置放的堆疊晶圓結構的導體 上’农後’細底膠填充(underfn⑽方式，完成堆疊晶圓封裝。 【實施方式】 些實_會詳細描述釘。然而，除了詳細観外，本發 二^〜乏地在其他的實闕綺，並不受独下魏賴定，本發明 之保護範圍以之後的專利範圍為準。 a堆係表示本發明所揭露之堆叠晶圓結構之結構示意圖。 , 具有導電膠12之-紐1G、具有第-重分配層 在圖中表’^L)(未在圖巾表示)以及複數個第_職連接元件(未 接亓杜㈤圓具有第二重分配層42以及複數個第二訊號達 其中，在摊之属第曰二晶圓40位於第一晶圓20上方，以構成一堆叠晶圓結構。 結構上的第—重分配層以及第二重分配層42的一端可 而藉馳ΪΒ日圓結構外緣’而另—端則位於堆疊晶圓結構上的切割道旁； ΐ 至每—個晶圓上的重分配 = m /刀配層與其他堆疊層的晶®結構連接，織將訊號傳送至其 可二二在此’位於第二晶圓4G上的第二重分配層42的佈線分式， 分配一，2〇的第一重分配層的佈線方式，亦或不同於第-重 i傳i、另冰方^因此’訊號可以在第一晶圓20與第二晶圓40之間相 内mi/#於第—晶w 2G上具有複數個第—貫孔，以及在第二晶圓4〇 t 1貫孔，複數個第—貫孔與複數個第二貫孔具有相同的 生貫孔與複數個第二貫孔内具有複數條導線％，用以電 性連接第一晶圓20與第二晶圓40。 Ϊ274373 另外要說明的是’在第-A圖中的堆叠晶圓結構是以主動面朝上、背 『設置在基板10上。在本發明的另一較佳堆疊晶圓結構，則是以主動面 朝下設置在基板H)上，如第-B圖所示。在第—b圖中，第—晶圓2〇 二及上方的第二晶圓4〇都與第—A圖中的結構與功能相同，其差 ^於’整個堆疊晶_構的主動面是朝向基板1Q的正面置放。因此，在 苐-B圖中的堆疊晶圓結構可以稱為覆晶堆疊晶圓結構。 另外’根據第- A圖及第- B圖所揭露之堆疊晶圓結構，本發明還 揭露-種形成堆疊晶圓結構的方法。參照第二A圖，係麵具有複數個第 ~重分配層ϋ圓之俯視圖。第二A圖中，形成複數個第—重分配層 ㈣咖—福嘴，狐)22的方法，係以沉積複數層金屬層於第一晶圓2〇 上，然後再以圖案化的方式，於第—晶圓2〇上形成第一重分配層22，且 f鄰Ϊ於第一晶圓2〇外側之第一重分配層22，延伸至第-晶圓2〇的最外 緣，第-重分配層22的另-端鄰近於第—切割道(啊_^)28。 將第一重分配層22形成的位置，設計在延伸至第一晶圓20的 貝、這疋為了在後續進行晶圓切割時，晶圓内的線路可以避免被破壞。 ^外這线數個第-重分配層22可以做為堆叠晶圓結構之間的訊號連 f ’而訊號是由第-晶圓20上的訊號連接元件24所傳送，而訊號連接元 件24可以是接觸墊(contact _、或是導體凸塊(c〇nductive加㈣。在本 發明的較健體實施财’卿接纏做為第—訊號連接元件％。另外， 在第日a® 20的上方還包含第一保護層⑦as—咖柳，肖以保護第 '一晶圓20。 …接著’參照第二B ® ’係表示具有第二重分配相及複數個第二訊 號連接70件之第二晶圓之俯視圖。在此，第二晶圓4〇可以是由兩片或是 兩片以上的晶圓所堆疊構成4第二B圖中，係將已經完成堆疊的第二晶 圓40以主動面朝上，以背面置放在第一晶圓2〇的主動面上。其中，第一 晶圓20與第二晶圓40之間，係以低模數的接著膠接合，⑽成一堆疊晶 圓、··。構。在此’位於第二晶圓40上之第二重分配層的佈線方式可相同或 8 I274373 义不同於位於第一晶圓上之該第一重分配層42的佈線方式。另外，在第 二晶圓40的上方更包含第二保護層50，用以保護第二晶圓4〇。 復參考第二B圖，於完成晶圓堆疊的堆疊晶圓結構上，以雷射鑽孔 的方式’在堆疊晶圓結構内’形成複數個貫孔，在此，第 ~切割道48的位置對應於第一切割道28的位置。因此，可以將堆疊晶圓 ，構側邊、每一層的重分配層（第一重分配層22以及第二重分配層42)裸 路出來。此外’在堆疊晶圓結構上所形成的複數個貫孔6〇，完全或是不完 乂 全貫穿整個堆疊晶圓結構。當複數個貫孔00為不完全貫穿之貫孔時，其 • 貫穿於堆疊晶圓的深度，必須可以導通第一晶圓20與第二晶圓40之間的 電路。另外，具有不完全貫穿之複數個貫孔的堆疊晶圓結構，在後續的步 驟中，可以將堆疊晶圓結構的主動面朝下置放於基板10上，以覆晶的方 式進行構裝。 復參考®，以完全貫雜個堆疊晶齡構之貫孔6G而言，以 電鍍的方式，於貫孔60内填入導體，此導體用以導通堆疊晶圓結構中， 第一晶圓20與第二晶圓40之間的電路。 接著’參考第一C目’係表示將第三B圖中的堆疊晶圓結構單體化 之〜構示思圖。在此，係根據堆疊晶圓結構上的第一切割道％與第二切 』道48 ’將整個堆疊晶圓結構單體化，此時，裸露出位於堆疊晶圓結構中， 複數個貫孔6G内之魏條導線7〇。另外，餅—提的是，若當複數個貫 孔60的位置並非鄰近於第—切割道28與第二糊道，在單體化時，則 複數個貫孔60不會裸露出來。 接著’參考第二D圖，係表示在堆叠晶圓結構於切割完成之後，以 主動面朝上設置於基板上之結構示_。第二E圖係表示，堆疊晶圓結構 於切割完成之後’以主動面朝下置放於基板上之結構示意圖。於本發明所 揭露之具體實施例中，在堆#晶_構切割分開之後，可以根據製程之須 9 1274373 求，將堆疊晶圓結構以主動面朝上(faee up)置放(如第二D圖所示），或是 將堆疊晶圓結構的主動面朝下(face d〇wn)置放(如第二£圖所示)與基板1〇 上。 參照第三A圖，係根據第二D圖以主動面朝上之堆疊晶圓結構為實 施例。將堆疊晶圓結構的主動面朝上、而背面設置於基板1〇的上方。接 著，利用印刷的方式，在堆疊晶圓結構與基板1〇之間，形成導電膠12， 在本發明的實施例中，其導電膠12印刷的位置，可設置於堆疊晶圓結構 所裸露出複數條導線70的位置。 接著’ 4參照第二b ®，係表示在堆疊晶圓結構社動面朝上置放 在基板10之後，執行一回銲步驟(refl〇w)步驟，使得位於堆叠晶圓結構側 ，的導電膠12與堆疊晶15結結構之側邊裸露出來，的複數條導線結合。 ，後’於堆疊晶®結構上，執行—賴步驟（圖树示），以完成整個堆 豐晶圓結構的封裝步驟。 另外，參照第二B圖，係根據第二E圖中 付食$日日l構可以藉由導電膠12固定於基板1〇上 膝填入___ (_)，藉叫成難_。 緣灯一底 專利2====1 ㈣，、_順姻之申請 飾，均應包含訂叙”專所完紅等效改變或修 ；1274373 【圖式簡單說明】 第一A圖係根據本發明所揭露之技術，表示堆疊晶圓結構之結構示竜 具有主動面朝下之堆疊晶圓結 第一 B圖係根據本發明所揭露之技術， 構之結構示意圖； 第二A圖係根據本發明所揭露之技術，表示具有複數個第一重分配声 以及複數個第一接觸墊之第一晶圓之俯視圖； 曰 第二3圖係根據本發明所揭露之技術，係表示具有複數個第二重分配 層以及複數個第二接觸墊之第二晶圓層之結構示意圖； 第二C圖係根據本發明所揭露之技術，係表示堆疊晶圓結 之結構示意圖； 丹-I刀開 …第，D圖係根據本發明所揭露之技術，係表示在堆疊晶圓結構於切割 完成之後，以主動面朝上置放於基板上之結構示意圖； 第1圖係根據本發明所揭露之技術，表示堆疊晶圓結構於切割完成 之後，以主動面朝下置放於基板上之結構示意圖； 第三A圖係根據本發明所揭露之技術，表示堆叠晶圓結構的主動面朝 上置^:在具有導電膠的基板的上方之結構示意圖；以及 第三B圖係根據本發明所揭露之技術，係表示將堆疊晶圓結構的主動 面朝下置放於基板上之結構示意圖。 11 1274373 【主要元件符號說明】 ίο基板 12導電膠 20第一晶圓 22第一重分配層 24複數個第一接觸墊 26第一保護層 28第一切割道 40第二晶圓 42第二重分配層 44複數個第二接觸墊 48第二切割道 50第二保護層 60貫孔 70導線 121274373 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer structure, and more particularly to a wafer-to-wafer stack structure. [Prior Art] How to achieve the trend of high-performance, multi-functional and light-weight and short-term consumer electronics products. • High-integration, high-density and high-reliability electronic components will dominate the future products. Can develop milestones. In response to the development trend of electronic assembly, the form of electronic assembly has evolved from the early pin through hole to the surfering m〇unting technology (SMT), and in order to comply with the electronic component wafer ι The trend of increasing the number of turns, the bonding of the wafer to the substrate has also progressed from wire bonding to the current flip-chip form of area ajTay. Although the efficiency of a single package can be greatly increased in this way, the development limit and bottleneck are faced in the ability to shrink the size. Therefore, the development of the stacking technology is important and can be regarded as one of the mainstream in the future. Before the development of the stack, system Gn ehip (SqC) was considered a solution for the integration of the crystal group. At present, there are also many research institutions to start the development of s〇c. However, by comparison, the S〇C system, which is a flat and sleek combination, will result in a large increase in the overall wafer size, and its reticle is complicated, and there are still many shortcomings in terms of process cost or product trend. Under her, the stacking technology of the community direction can effectively achieve the advantages of downsizing and shortening the length of the line. / Stacked in three ways: wafer-to-wafer, wafer-to-wafer, and package-to-package. After the wafer-to-wafer surface is cut, the wafers of the completed lines are stacked and assembled. In this form of material, the highest shrinkage, the shortest signal path, and the most heat recording can be achieved. The highest proportion of shrink-fits can be integrated into a variety of formats in a fixed product size to accommodate the versatility and miniaturization of electronic components. In addition, because the chip itself is bare, it helps to dissipate heat, and the high-power components will improve the shortcomings of its thermal engine. '1274373 However, the disadvantage of this construction method is that the test is not easy, and the wafer of the known good die is not easy to obtain, so the construction cost is relatively increased. SUMMARY OF THE INVENTION In view of the above problems in the background of the invention, in order to solve the problems caused by the stacked wafer structure, the present invention discloses a stacked wafer structure instead of a stacked wafer structure, thereby improving the stacked wafer structure in the prior art. The cost problem, so it can effectively reduce the unit cost and the application of the components. It is an object of the present invention to form a redistribution layer distnbutKmlayer; rdl) of the same line distribution on each wafer and to stack in the same direction. In the present invention, the wires are filled in the stacked via holes by electroplating to turn on the circuits of each of the upper and lower wafers. According to the above-mentioned purposes, the present invention discloses a stacked crystal-off structure and a method for forming the same, and the stacked-wafer structure comprises: a first wafer having a redistribution layer; The second wafer layer of the redistribution layer of the line distribution direction is placed: , , , , , , , , , , , , , , , , , , , , , , , , According to the purpose of the various embodiments, the present invention also discloses a method of forming a stacked crystal, in which a compound bonding is formed to form a stacked wafer structure; and then, in the above-mentioned stacker circuit, a stacking according to a stacked wafer structure is performed. The wafer structure is separated from the stacked germanium structure of the same line distribution; then, the back side thereof is placed on the substrate with the conductive paste; then - back '1274373, in another embodiment of the present invention After cutting the other stacked wafer structure, the active 2 is placed down, and placed on the substrate with the glue, the _ ground-reflow step, and the conductive paste can be adhered to the active surface. On the conductor of the stacked wafer structure placed on the substrate, the 'after-slurry' fine-filled glue is filled (underfn (10) way to complete the stacked wafer package. [Embodiment] Some of the _ will describe the nail in detail. However, in addition to the detailed ,, this The scope of protection of the present invention is based on the scope of the following patents. The stack represents the structural schematic of the stacked wafer structure disclosed in the present invention. With Conductive adhesive 12 - New 1G, with a first redistribution layer in the figure '^L) (not shown in the drawing) and a plurality of first-level connecting elements (not connected to the Du (5) circle has a second redistribution layer 42 and a plurality of second signals are obtained, wherein the second wafer 40 is located above the first wafer 20 to form a stacked wafer structure. The structural first redistribution layer and the second redistribution layer One end of 42 can be used to ride the outer edge of the Japanese yen structure while the other end is located next to the scribe line on the stacked wafer structure; 重 Redistribution to each wafer = m / knife layer and other stacked layers The crystal® structure is connected, and the woven signal is transmitted to the wiring division of the second redistribution layer 42 on the second wafer 4G, and the wiring of the first redistribution layer of one, two 分配 is distributed. The method may also be different from the first-weight i-i, the other ice, so the signal may have a plurality of mi/# on the first-crystal w 2G in the phase between the first wafer 20 and the second wafer 40. a through hole, and a through hole in the second wafer 4 〇t 1 , the plurality of first through holes and the plurality of second through holes have the same through hole and a plurality of The two through holes have a plurality of wires % for electrically connecting the first wafer 20 and the second wafer 40. Ϊ274373 It is also noted that the stacked wafer structure in the first-A diagram is actively facing The upper and lower sides are disposed on the substrate 10. Another preferred stacked wafer structure of the present invention is disposed on the substrate H with the active surface facing downward, as shown in FIG. In the figure -b, the first wafer 2 and the second wafer 4 are the same as the structure and function in the Figure A, and the difference is that the active surface of the entire stacked crystal structure is The front surface of the substrate 1Q is placed. Therefore, the stacked wafer structure in the 苐-B diagram can be referred to as a flip chip stacked wafer structure. Further, the present invention also discloses a method of forming a stacked wafer structure in accordance with the stacked wafer structure disclosed in Figures AA and B. Referring to Figure 2A, the system has a top view of a plurality of first redistribution layers. In the second A diagram, a method of forming a plurality of first-redistribution layers (four) coffee-fussing foxes 22 is performed by depositing a plurality of metal layers on the first wafer 2, and then patterning, Forming a first redistribution layer 22 on the first wafer 2, and f adjacent to the first redistribution layer 22 outside the first wafer 2, extending to the outermost edge of the first wafer 2, The other end of the redistribution layer 22 is adjacent to the first cutting channel (ah_^) 28. The position at which the first redistribution layer 22 is formed is designed to extend to the first wafer 20, so that in the subsequent wafer dicing, the wiring within the wafer can be prevented from being destroyed. The number of the first redistribution layer 22 can be used as the signal connection between the stacked wafer structures and the signal is transmitted by the signal connection component 24 on the first wafer 20, and the signal connection component 24 can It is a contact pad (contact _, or a conductor bump (c〇nductive plus (4). In the health of the present invention, the implementation of the squadron is the first-signal connection component%. In addition, on the first day of the a® 20 The upper layer also includes a first protective layer 7as--willow to protect the first wafer 20. [Following the second B ® ' indicates that the second redistribution phase and the plurality of second signal connections are 70 A top view of the two wafers. Here, the second wafer 4 can be stacked by two or more wafers. 4 In the second B diagram, the second wafer 40 that has been stacked is The active surface is facing up, and the back surface is placed on the active surface of the first wafer 2〇, wherein the first wafer 20 and the second wafer 40 are bonded by a low modulus adhesive, and (10) are stacked. The wafer, the structure of the second redistribution layer on the second wafer 40 may be the same or 8 I274373 The difference is different from the wiring manner of the first redistribution layer 42 on the first wafer. Further, a second protective layer 50 is further disposed on the second wafer 40 for protecting the second wafer 4 . Referring to FIG. 2B, on the stacked wafer structure of the completed wafer stack, a plurality of through holes are formed in the stacked wafer structure by laser drilling, where the position of the first to scribe line 48 corresponds to At the position of the first dicing street 28. Therefore, the stacked wafers, the side edges, the redistribution layers of each layer (the first redistribution layer 22 and the second redistribution layer 42) can be bared out. The plurality of through holes 6 形成 formed on the wafer structure are completely or incompletely traversed throughout the stacked wafer structure. When a plurality of through holes 00 are through holes that are not completely penetrated, they are penetrated through the stacked wafer The depth must be such that the circuit between the first wafer 20 and the second wafer 40 can be turned on. In addition, the stacked wafer structure having a plurality of through holes not completely penetrated, the stacked wafer can be stacked in a subsequent step. The active side of the structure is placed face down on the substrate 10 to cover the crystal In the case of a through-hole 6G of a stacked crystal age, a conductor is filled in the through hole 60 by electroplating, and the conductor is used to turn on the stacked wafer structure. The circuit between the first wafer 20 and the second wafer 40. Next, the 'reference first C-head' indicates that the stacked wafer structure in the third B-picture is singularized. Here, The entire stacked wafer structure is singulated according to the first dicing channel % and the second dicing channel 48' on the stacked wafer structure. At this time, the bare exposed substrate is located in the stacked wafer structure, and the plurality of through holes 6G are The strip wire is 7〇. In addition, the cake is provided that if the positions of the plurality of through holes 60 are not adjacent to the first cutting channel 28 and the second paste channel, in the case of singulation, the plurality of through holes 60 are not Will be bare. Next, referring to the second D diagram, the structure of the stacked wafer structure is disposed on the substrate with the active surface facing up after the cutting is completed. The second E diagram shows the structure of the stacked wafer structure placed on the substrate with the active surface facing down after the cutting is completed. In a specific embodiment of the present disclosure, after the stacking of the stacks, the stacked wafer structures may be placed with the active face up (eg, second) according to the process requirements 9 1274373. As shown in Figure D, the active wafer face of the stacked wafer structure is placed face down (as shown in the second figure) with the substrate 1 . Referring to the third A diagram, the stacked wafer structure with the active face up is taken as an embodiment according to the second D diagram. The active surface of the stacked wafer structure is facing upward, and the back surface is disposed above the substrate 1〇. Then, a conductive paste 12 is formed between the stacked wafer structure and the substrate 1 by printing. In the embodiment of the present invention, the position where the conductive paste 12 is printed can be disposed on the stacked wafer structure. The position of the plurality of wires 70. Then, '4 refers to the second b ® , which means that after the stacked wafer structure is placed on the substrate 10 facing up, a reflow step is performed to make the conductive layer on the side of the stacked wafer structure. The glue 12 is exposed to the side of the stacked crystal 15 junction structure, and the plurality of wires are combined. Then, on the stacked crystal® structure, a step-by-step (illustration) is performed to complete the packaging step of the entire stacked wafer structure. In addition, referring to the second B diagram, according to the second E diagram, the food can be fixed on the substrate 1 by the conductive adhesive 12 to fill the ___ (_), and the borrowing is difficult. The edge of the edge of the patent 2 ====1 (four), _ shun marriage application decoration, should contain the narrative "specialized red equivalent change or repair; 1274337 [Simple diagram] The first A diagram is based on The technology disclosed in the present invention indicates that the structure of the stacked wafer structure has an active face-down stacked wafer junction. The first B-picture is a schematic structural view of the structure according to the disclosed technology. The second A-picture is based on The technology disclosed in the present invention represents a top view of a first wafer having a plurality of first redistribution sounds and a plurality of first contact pads; 曰 second 3 is a plurality of techniques according to the disclosed technology Schematic diagram of the second redistribution layer and the second wafer layer of the plurality of second contact pads; the second C diagram is a schematic diagram showing the structure of the stacked wafer junctions according to the technology disclosed in the present invention; Dan-I knife opening ...the D, according to the technology disclosed in the present invention, is a schematic view showing the structure of the stacked wafer structure placed on the substrate with the active surface facing up after the completion of the cutting. FIG. 1 is a schematic view of the present invention. Technology, indicating stacking After the cutting is completed, the active structure is placed face down on the substrate; the third A is based on the technology disclosed in the present invention, indicating that the active surface of the stacked wafer structure is facing upwards: A schematic diagram of the structure above the substrate of the glue; and a third B diagram showing the structure of the stacked wafer structure with the active surface facing down on the substrate according to the technology disclosed in the present invention. 11 1274373 [Main component symbol Примение задрание информация информация информация Two contact pads 48 second cutting track 50 second protective layer 60 through hole 70 wire 12