TWI224336B - Semiconductor memory device having a sub-amplifier configuration - Google Patents

Semiconductor memory device having a sub-amplifier configuration Download PDF

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Publication number
TWI224336B
TWI224336B TW092117532A TW92117532A TWI224336B TW I224336 B TWI224336 B TW I224336B TW 092117532 A TW092117532 A TW 092117532A TW 92117532 A TW92117532 A TW 92117532A TW I224336 B TWI224336 B TW I224336B
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TW
Taiwan
Prior art keywords
aforementioned
sub
semiconductor memory
memory device
sense amplifier
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Application number
TW092117532A
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English (en)
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TW200414193A (en
Inventor
Takashi Kono
Takeshi Hamamoto
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Renesas Tech Corp
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Publication of TW200414193A publication Critical patent/TW200414193A/zh
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Publication of TWI224336B publication Critical patent/TWI224336B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/065—Sense amplifier drivers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)

Description

1224336 $年^月1 9着(更)i£本丨 —…__. —…| “第921 17532號專利申請案 申請專利範圍更正本 (93年12月29曰） 1 · 一種具有次放大架構之半導體記憶裝置，具備： 行列狀配置之複數的記憶體單元； 對應於前述複數之記憶體單元之複數之行而配置 之複數的字元線； 對應於前述複數之記憶體單元之複數之列而配置 之複數的位元線對； 用以檢測放大由前述複數之記憶體單元讀出之數 據之複數的感測放大器帶；以及 與前述各複數之感測放大器帶交叉配置之複數的 次字元線驅動帶， 前述複數之感測放大器帶各含有： 對應於前述複數之位元線對所設之用以檢測放大 ，對應之位元線對之電位差之複數的感測放大器； 與前述複數之感測放大器共通而設之感測放大器 驅動線；以及 對應於前述複數之位元線對所設之各各與對應之 位元線為選擇性的連接之複數的第_數據線對， 並具有對應於各各前述複數之第一數據線對所設 之複數的次放大器， 前述複數之次放大器各含有： 第一、第二及第三電晶體， (更正本）314827 1224336 前述第一電晶體之控制端子為連接於前述第— 據線對之-方線’其第i導通端子為連接於前述第？ 據線對之m其第2導通料料接於前逑第三 電晶體之第1導通端子， 一 前述第二電晶體之控制端子為連接於前述第— 據線對之另—方線，其第丨導通料為連接於前述第— 數據線對之—方線’其第2導通端子則連接於前述第三 電晶體之第1導通端子，以及 鈾述第二電晶體由控制端子輸入前述次放大器之 活性化時序控制訊號，其第2導通端子為連接於前述感 測放大器驅動線。 2· —種具有次放大架構之半導體記憶裝置，具備： 行列狀配置之複數的記憶體單元； 對應於前述複數之記憶體單元之複數的行配置之 複數的字元線； 對應於前述複數之記憶體單元之複數的列配置之 複數的位元線對； 用以檢測放大由前述複數之記憶體單元讀出之數 據之複數的感測放大器帶；以及 與岫述各複數之感測放大器帶交叉而設之複數的次 字元線驅動帶， 前述複數之感測放大器帶之各各為含有： 對應於前述複數之位元線叙所設之用以檢測放大對 應之位元線對之電位差之複數的感測放大器； 2 (更正本）314827 1224336 與前述複數之感測放大器共通而μ 、阳叹之感測放大界 動線；以及 八的· 對應於前述複數之位元線對所設 各為與對庶之 位元線選擇性的連接之複數的第一數據線對 前述複數之次字元線驅動帶之各各含有 對應於前述複數之第一數據線對 0又 < 於讀出動 作時’接收經由對應之前述第一數據線、 J <►月1j述次放女 裔放大之數據之複數的第二數據線對； 並具有對應於各各前述複數之第一數 佩深對而言旁 之複數的次放大器， ^ 前述複數之次放大器各各含有： 第一、第二及第三電晶體， 前述第一電晶體之控制端子為連接於前述第一 據線對之一方線，其第1導通端子為連接於前述第二 據線對之一方線，其第2導通端子則連接於前述第2 + 晶體之第1導通端子， ^ 月ίι述第二電晶體之控制端子為連接於前述第—數 據線對之另一方線，其第丨導通端子為連接於前述第二 數據線對之另一方線，其第2導通端子則連接於前述： 三電晶體之第1導通端子，以及 前述第三電晶體由控制端子輸入前述次放大器 活性化時序控制訊號，其第2導通端子為連接於前、,、/ 測放大器驅動線。 則述感 3.如申請專利範圍第1項之半導體記憶裝 八甲具有： 幻 4827 (更正本) 3 1224336 產生應於位址訊號而選擇與前述複數之第一數據 口各連接之則述位π、線對之行選擇訊號 碼器； 接又使刖述仃解碼器活性化之行選擇賦能訊號而 2出前述次放大器之活性化時序控制訊號的控制訊號 產生電路； 前述控制訊號產生電路含有使前述次放大器之活 I·生化時序控制訊號之活性化以延遲至前述行選擇訊號 活性化之後的延遲電路。 4.如申請專利範圍第2項之半導體記憶裝置，其令具有： 產生應於位址訊號而選擇與前述複數之第一數據 線對各各連接之前述位元線對之行選捧訊號的行解媽 3S · an 9 接受使前述行解碼器活性化之行選擇賦能訊號而 輸出則述次放大器之活性化時序控制訊號的控制訊號 產生電路； 前述控制訊號產生電路含有使前述次放大器之活 性化時序控制訊號之活性化以延遲至前述行選擇訊號 活性化之後的延遲電路。 5.如申請專利範圍第2項之半導體記憶|置，其巾前述次 放大器含有：用以控制前述第一數據線對與前述第二數 據線對之分離/連接之輪入出開關電路； 前述輸入出開關電路具有： 輸入前述次放大器之活性化時序控制訊號之反轉 (更正本）314827 4 1224336 訊號及輸入出開關訊泸* x ' • 〜之NAND電路· ，將前述NAND電敗—+ ’ 之輸出予以反轅 σ 及 人得之換流為；以 應於前述換流器之於 輸入出而將前述第一 及前述第二數據線對分離康線對 收 弟及第二轉移閘電 路0 6·如申請專利範圍帛1項之半導體記憶襄置，其中前述客 複數之次放大器為設在前述複數之感測放大器帶與前 述複數之次字元線驅動帶之交叉領域。 7· ”請專利範圍第2項之半導體記憶裝置，其中前述各 複數之次放大器為設在前述複數之感測放大器帶與前 述複數之次字元線驅動帶之交又領域。 (更正本）314827 5
TW092117532A 2003-01-28 2003-06-27 Semiconductor memory device having a sub-amplifier configuration TWI224336B (en)

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Application Number Priority Date Filing Date Title
JP2003018366A JP4397166B2 (ja) 2003-01-28 2003-01-28 半導体記憶装置

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TW200414193A TW200414193A (en) 2004-08-01
TWI224336B true TWI224336B (en) 2004-11-21

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US (1) US6894940B2 (zh)
JP (1) JP4397166B2 (zh)
KR (1) KR100560134B1 (zh)
CN (1) CN100367409C (zh)
TW (1) TWI224336B (zh)

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Publication number Priority date Publication date Assignee Title
KR100555568B1 (ko) * 2004-08-03 2006-03-03 삼성전자주식회사 온/오프 제어가 가능한 로컬 센스 증폭 회로를 구비하는반도체 메모리 장치
KR100699875B1 (ko) * 2005-11-08 2007-03-28 삼성전자주식회사 센스앰프 구조를 개선한 반도체 메모리 장치
KR100656452B1 (ko) 2005-11-29 2006-12-11 주식회사 하이닉스반도체 프리차지 장치
JP5743045B2 (ja) * 2008-07-16 2015-07-01 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置及び半導体記憶装置におけるメモリアクセス方法
JP5624715B2 (ja) * 2008-10-30 2014-11-12 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置
JP2010140579A (ja) * 2008-12-15 2010-06-24 Elpida Memory Inc 半導体記憶装置
JP2010257552A (ja) * 2009-04-28 2010-11-11 Elpida Memory Inc 半導体記憶装置
JP2011090750A (ja) 2009-10-23 2011-05-06 Elpida Memory Inc 半導体装置及びその制御方法
JP2011113620A (ja) 2009-11-27 2011-06-09 Elpida Memory Inc 半導体装置及びこれを備えるデータ処理システム
JP2011175719A (ja) * 2010-02-25 2011-09-08 Elpida Memory Inc 半導体装置
KR102319827B1 (ko) * 2017-06-28 2021-11-01 에스케이하이닉스 주식회사 증폭기 회로
JP7222568B2 (ja) * 2017-09-11 2023-02-15 ウルトラメモリ株式会社 サブアンプ、スイッチング装置、及び、半導体装置

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JPS6187782A (ja) * 1984-03-19 1986-05-06 Kawasaki Heavy Ind Ltd 予備圧縮された単位成形炭ブロックの本成形機装入方法およびそれを可能にした成形装置
JP3067060B2 (ja) 1992-10-20 2000-07-17 三洋電機株式会社 半導体記憶装置
US5596521A (en) * 1994-01-06 1997-01-21 Oki Electric Industry Co., Ltd. Semiconductor memory with built-in cache
JP3666671B2 (ja) * 1994-12-20 2005-06-29 株式会社日立製作所 半導体装置
JP2000200489A (ja) * 1999-01-07 2000-07-18 Mitsubishi Electric Corp 半導体記憶装置

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Publication number Publication date
US20040145956A1 (en) 2004-07-29
KR100560134B1 (ko) 2006-03-13
US6894940B2 (en) 2005-05-17
JP4397166B2 (ja) 2010-01-13
KR20040069251A (ko) 2004-08-05
JP2004234704A (ja) 2004-08-19
CN1518001A (zh) 2004-08-04
CN100367409C (zh) 2008-02-06
TW200414193A (en) 2004-08-01

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