TWI223862B - Procedure for the fixation of chip carriers - Google Patents
Procedure for the fixation of chip carriers Download PDFInfo
- Publication number
- TWI223862B TWI223862B TW091134483A TW91134483A TWI223862B TW I223862 B TWI223862 B TW I223862B TW 091134483 A TW091134483 A TW 091134483A TW 91134483 A TW91134483 A TW 91134483A TW I223862 B TWI223862 B TW I223862B
- Authority
- TW
- Taiwan
- Prior art keywords
- metal foil
- wafer
- procedure
- wafer carrier
- scope
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 12
- 239000000969 carrier Substances 0.000 title claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000011888 foil Substances 0.000 claims abstract description 28
- 239000000565 sealant Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 238000004512 die casting Methods 0.000 claims description 2
- 239000011344 liquid material Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 238000010292 electrical insulation Methods 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 abstract 1
- 238000007789 sealing Methods 0.000 abstract 1
- 238000004080 punching Methods 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004873 anchoring Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004049 embossing Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Measuring Leads Or Probes (AREA)
Description
^862 ⑴ ,、發明說明 (發明說明應敘明:發明所屬之技術領域 本發明係關於金屬羯上的曰前技術、内容、實施方式及圖式簡單,: ,其中從一金屬fl將軌跡衝斷二載體之非接觸固定裎序 夕缸 衡崎,接著將該晶片應用於所俨 軌跡系統’並將晶片焊接於烊線且進行密封。 于 在非接觸晶片卡的製造中,總是從一金細斷軌跡 。所用之金屬箱係-拉長的落條,其上有相同的軌跡圖案 重複排列,可使用積體電路並藉由一機器對其進行焊接。
一般情況下,在用一密封劑塗佈該晶片前,通過使用焊線 來形成接觸。隨後,從一金屬箔條將積體電路及其周圍的 軌跡圖案(晶片載體)衝壓成一片,並插入相應的晶片卡的 部分(比較 D E 1 9 8 1 6 0 6 6)。 試該 由於處理技術的原因,當晶片還在該金屬箔上時需測 該晶片的電氣性能。藉由金屬箔形成的兩橋接(接地橋)
,可用固定於適當位置的晶片成功地執行一些測試。雖然 對於某些測試而言,切斷所有與該金屬箔的導電連結係絕 對必要的。然而,一旦切斷包含兩橋接的所有連結時,該 晶片即不再固定於適當的位置。 因此,本發明的目的係提供晶片載體的某種支撐方法 ,以用於切斷所有導電連結時電氣系統測試的輸送。 該項工作係藉由申請專利範圍第1項之特徵予以解決 。在衝斷步驟後,為了將該晶片載體固定於適當位置’本 發明擬在該晶片上使用一絕緣支撐層,該支撐層延伸超出 該晶片之外,並連接至周圍的箔條。為此*好使用上述之 密封劑,且為液體劑,特別係以黏性可固化材料的形式。 -6 - 1223862 (2) 發明說明續頁 此外,最好在該晶片載體鄰近的金屬箔邊緣配置錨定孔或 凹穴,使該材料可注入上述錨定孔及凹穴以增強穩定性' 或者,該絕緣層的黏著作用可作為唯一的固定方式。 隨後,最好係藉由衝斷(完全衝斷、衝離)將包含接地橋 的導電連結切斷,而晶片載體則可藉由其與該絕緣層的連 結固定於適當位置。這些步驟完成後,可執行所需的電氣 系統測試。 因此,本發明係關於晶片載體的固定程序,其中從一 金屬箔衝斷執跡,接著將該晶片應用於所得之執跡系統, 並將晶片焊接於焊線且進行密封,其中承載晶片的該晶片 載體塗佈有一電氣絕緣層,該絕緣層最好為密封劑,使切 斷金屬箔與晶片載體之間的所有金屬接觸時,延伸出晶片 載體的該絕緣層仍能使該晶片載體透過該絕緣層固定於 金屬箔的適當位置。 該絕緣層最好係一液體可固化材料,其係藉由壓鑄及 固化形成。在金屬箔中可配置錨定孔以利液體材料的穿 透。 熟悉技術人士應知道適合的金屬箔及密封劑。 圖1說明具有衝斷前執跡(1)的一金屬箔,在斜線所示的 位置處將其衝斷。虛線(2)顯示所用的絕緣層之輪廓。晶 片的輪廓係藉由方形(4)顯示。圖中未顯示焊線。虛線(3) 指示凹六的位置(若有的話)。下側邊緣的方形代表金屬箔 條的輸送孔。 圖2說明沿線A-A的一截面,顯示晶片(4)(其用黑色標注 1223862
發_說明續I :圖中未顯示焊線)及密封劑塗層(交叉斜線),其係塗佈 在圖1中衝斷前的虛線(2)内。凹穴用單斜線顯示為金屬 左側部分中的一步驟。藉由壓花法可在金屬箔上提供凹穴 。或者,可提供錨定孔,也可在其較低邊緣提供凹穴。在 圖1或圖2中未顯示此類型的錨定孔。 圖3顯示圖1重複排列的佈線模式中整個箔條或箔帶的 一截面。該箔帶的方形輸送孔係在邊緣顯示。
圖式簡單說明 以上已根據圖示對本發明之一項可能的具體實施例加 以說明。圖式中: 圖1係承載一晶片載體的金屬箔的一部分, 圖2係沿圖1中線A - A的^一截面’以及 圖3係承載多個晶片載體的金屬箔條的一部分。 圖式代表符號說明 1 衝斷前軌跡
2 虛線 3 虛線 4 方形
Claims (1)
1223862 拾、申請專利範圍 1. 一種晶片載體的固定程序,在該等晶片載體中從一金 屬箔中將軌跡衝斷,接著將該晶片應用於所得到的執 跡系統,並將其焊接於焊線且進行密封;其特徵為承 載該晶片的該晶片載體塗佈有一電氣絕緣層,該絕緣 層最好為密封劑;且該絕緣層延伸超出該晶片載體之 範圍,使得當切斷金屬箔與晶片載體之間的所有金屬 接觸時,該晶片載體仍能透過該絕緣層固定於該金屬 箔的適當位置。 2. 如申請專利範圍第1項之程序,其特徵為所塗佈的該絕 緣層最好係一液體固化材料,其係藉由壓鑄及固化所 塗佈。 3. 如申請專利範圍第1或2項之程序,其特徵為該金屬箔 具有錫定孔,其用於該液體材料的穿透。 4. 如申請專利範圍第1或2項之程序,其特徵為與該晶片 載體鄰接的該金屬箔的該等邊緣具有一或數個凹穴。 5. 如申請專利範圍第4項之程序,其特徵為該等凹穴係藉 由浮ί匕壓化制法在該金屬上形成。 6. 如申請專利範圍第3項之程序,其特徵為該錨定孔具有 凹穴。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10202257A DE10202257B4 (de) | 2002-01-21 | 2002-01-21 | Verfahren zum Fixieren von Chipträgern |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200305243A TW200305243A (en) | 2003-10-16 |
TWI223862B true TWI223862B (en) | 2004-11-11 |
Family
ID=7712737
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW091134483A TWI223862B (en) | 2002-01-21 | 2002-11-27 | Procedure for the fixation of chip carriers |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP1329952A3 (zh) |
JP (1) | JP2003218172A (zh) |
KR (1) | KR20030063103A (zh) |
CN (1) | CN1434497A (zh) |
DE (1) | DE10202257B4 (zh) |
SG (1) | SG111095A1 (zh) |
TW (1) | TWI223862B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI474457B (zh) * | 2010-01-25 | 2015-02-21 | Heraeus Materials Tech Gmbh | 在凸起位置藉由自由裁切以改善平整性 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100971037B1 (ko) * | 2008-09-26 | 2010-07-20 | 주식회사 더존뉴턴스 | 탁상용 달력 |
DE102012103583B4 (de) * | 2012-02-29 | 2017-06-22 | Heraeus Deutschland GmbH & Co. KG | Substrat mit vergrößerter Chipinsel und Verfahren zu dessen Herstellung |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5265670A (en) * | 1975-11-27 | 1977-05-31 | Mitsubishi Electric Corp | Production of semiconductor device |
JPS5381076A (en) * | 1976-12-27 | 1978-07-18 | Hitachi Ltd | Lroduction of resin seal semiconductor device |
JPS5478087A (en) * | 1977-12-05 | 1979-06-21 | Toshiba Corp | Manufacture of semiconductor |
JPS6362366A (ja) * | 1986-09-03 | 1988-03-18 | Matsushita Electronics Corp | リ−ドフレ−ム |
JP2617218B2 (ja) * | 1989-02-06 | 1997-06-04 | ローム株式会社 | 半導体部品の製造方法及びその製造方法に使用するリードフレーム |
JP2672924B2 (ja) * | 1992-07-30 | 1997-11-05 | 三菱電機株式会社 | 非接触icカードとその製造方法及びテスト方法 |
JP3157947B2 (ja) * | 1993-03-26 | 2001-04-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
DE19703057A1 (de) * | 1996-12-20 | 1998-07-02 | Siemens Ag | Trägerelement zum Einbau in Kombi-Chipkarten und Kombi-Chipkarte |
DE19800646C2 (de) * | 1998-01-09 | 2000-05-04 | Siemens Ag | Trägerelement für einen Halbleiterchip |
DE19816066A1 (de) | 1998-04-09 | 1999-10-14 | Philips Patentverwaltung | Folie als Träger von integrierten Schaltungen |
DE19922473A1 (de) * | 1999-05-19 | 2000-11-30 | Giesecke & Devrient Gmbh | Chipträgermodul |
DE10038120A1 (de) * | 2000-08-04 | 2001-10-18 | Infineon Technologies Ag | Systemträger zum Verpacken von Halbleiterchips zu elektronischen Bauteilen und Verfahren zur Herstellung von Systemträgern und elektronischen Bauteilen |
-
2002
- 2002-01-21 DE DE10202257A patent/DE10202257B4/de not_active Expired - Fee Related
- 2002-11-27 TW TW091134483A patent/TWI223862B/zh not_active IP Right Cessation
- 2002-11-27 EP EP02026290A patent/EP1329952A3/de not_active Withdrawn
- 2002-12-05 SG SG200207449A patent/SG111095A1/en unknown
- 2002-12-27 KR KR1020020085269A patent/KR20030063103A/ko not_active Application Discontinuation
-
2003
- 2003-01-13 CN CN03101662A patent/CN1434497A/zh active Pending
- 2003-01-20 JP JP2003010927A patent/JP2003218172A/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI474457B (zh) * | 2010-01-25 | 2015-02-21 | Heraeus Materials Tech Gmbh | 在凸起位置藉由自由裁切以改善平整性 |
Also Published As
Publication number | Publication date |
---|---|
EP1329952A2 (de) | 2003-07-23 |
EP1329952A3 (de) | 2009-03-04 |
TW200305243A (en) | 2003-10-16 |
KR20030063103A (ko) | 2003-07-28 |
CN1434497A (zh) | 2003-08-06 |
DE10202257A1 (de) | 2003-08-07 |
JP2003218172A (ja) | 2003-07-31 |
DE10202257B4 (de) | 2005-12-01 |
SG111095A1 (en) | 2005-05-30 |
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MM4A | Annulment or lapse of patent due to non-payment of fees |