KR20070049964A - 전력용 반도체 모듈 - Google Patents

전력용 반도체 모듈 Download PDF

Info

Publication number
KR20070049964A
KR20070049964A KR1020060107601A KR20060107601A KR20070049964A KR 20070049964 A KR20070049964 A KR 20070049964A KR 1020060107601 A KR1020060107601 A KR 1020060107601A KR 20060107601 A KR20060107601 A KR 20060107601A KR 20070049964 A KR20070049964 A KR 20070049964A
Authority
KR
South Korea
Prior art keywords
metal layer
power semiconductor
semiconductor module
power
logic
Prior art date
Application number
KR1020060107601A
Other languages
English (en)
Other versions
KR101271283B1 (ko
Inventor
고블 크리스티안
칼르하인즈 어거스틴
Original Assignee
세미크론 엘렉트로니크 지엠비에치 앤드 코. 케이지
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 세미크론 엘렉트로니크 지엠비에치 앤드 코. 케이지 filed Critical 세미크론 엘렉트로니크 지엠비에치 앤드 코. 케이지
Publication of KR20070049964A publication Critical patent/KR20070049964A/ko
Application granted granted Critical
Publication of KR101271283B1 publication Critical patent/KR101271283B1/ko

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0263High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H05K1/0265High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251Disposition
    • H01L2224/2518Disposition being disposed on at least two different sides of the body, e.g. dual array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48699Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48717Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48724Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48699Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48747Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385Assembly of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20Parameters
    • H01L2924/207Diameter ranges
    • H01L2924/20757Diameter ranges larger or equal to 70 microns less than 80 microns
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0352Differences between the conductors of different layers of a multilayer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0367Metallic bump or raised conductor not used as solder bump
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/10166Transistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/049Wire bonding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

기판(12), 결합 시트(14) 및 기판(12)과 결합 시트(14) 사이에 적어도 하나의 전력용 반도체 구성 요소(16)를 포함하는 전력용 반도체 모듈(10)이 제공된다. 결합 시트(14)는 회로 구조의 얇은 논리 금속층(26)과, 상기 논리 금속층에 비해 두꺼운 회로 구조의 전력용 금속층(28), 및 그 사이의 얇은 전기 절연성 합성 수지 시트(24)를 포함한다. 결합 시트(14)에는 적어도 하나의 반도체 구성 요소(16)와 접촉을 위한 접촉 돌기(30)가 형성되어 있다. 논리 금속층(26) 및 전력용 금속층(28) 사이에는 접촉 통공(32)이 제공되어 있다. 합성 수지 시트(24)에는 각 접촉 통공(32)의 영역에 논리 금속층(26)의 자유 영역(36)에 대한 공간(34)이 형성되어 있다. 얇은 배선(40)의 유연성 부분(38)이 논리 금속층(26)의 자유 영역(36) 및 공간(34)을 통해 합성 수지 시트(24)로 연장되어 있고, 논리 금속층(26) 및 전력용 반도체층(28)과 접합 부위(44, 48)를 통해 접촉된다.
전력용 반도체 모듈, 논리 금속층, 전력용 금속층, 결합 시트, 접촉 통공

Description

전력용 반도체 모듈 {Power Semiconductor Module}
도 1은 전력용 반도체 모듈의 형태를 나타낸 단면도.
도 2는 도 1의 II 부분에 대한 확대도.
<도면의 주요 부분에 대한 부호의 설명>
10: 전력용 반도체 모듈
12: (10에서) 기판
14: (10에서 16에 대한) 결합 시트
16: (10에서 12와 14 사이의) 전력용 반도체 구성 요소
18: (16에서) 컬렉터
20: (16에서) 이미터
22: (16에서) 게이트
24: (14에서) 전기 절연성 합성 수지 시트
26: (24에 대한) 회로 구조의 논리 금속층
28: (24에 대한) 회로 구조의 전력용 금속층
30: (14에서 16에 대한) 돌기
32: (26 및 28 사이의) 접촉 통공
34: (24에서 40에 대한) 공간
36: (26에서 40에 대한) 자유 영역
38: (40에서) 유연성 부분
40: (26 및 28 사이의) 얇은 배선
42: (40에서) 제1 말단부
44: (42에서 40과 26 사이의) 접합 부위
46: (40에서) 제2 말단부
48: (46에서 40과 28 사이의) 접합 부위
본 발명은 기판; 회로 구조의 논리 금속층과, 상기 논리 금속층에 비해 두꺼운 회로 구조의 전력용 금속층, 및 그 사이의 얇은 전기 절연성 합성 수지 시트를 포함하는 결합 시트; 및 상기 기판과 결합 시트 사이에 적어도 하나의 전력용 반도체 구성 요소를 포함하는 전력용 반도체 모듈로서, 상기 결합 시트에는 적어도 하나의 반도체 구성 요소와 접촉하기 위한 접촉 돌기가 형성되어 있으며, 상기 논리 금속층 및 상기 전력용 금속층 사이에는 접촉 통공이 제공되어 있는 전력용 반도체 모듈에 관한 것이다.
상기 유형의 전력용 반도체 모듈이 본 출원인이 출원한 DE 103 55 925 A 1에 공지되어 있다. 상기 공지된 전력용 반도체 모듈은 예를 들면 레이저 천공술 및 도전성 재료를 사용하는 후속 레이저 충전법에 의해 제조된다. 이를 위해, 수백 ㎛의 직경을 가진 접촉 통공이 요구된다. 이러한 접촉 통공의 제조는 무시할 수 없는 비용이 소요된다. 이외에도, 도전성 재료에 의한 충전시 열 팽창 계수와 같은 재료 특성을 갖는 충전-재료가 결합 시트의 재료에 대해 적절히 조정되어야 한다는 점을 고려하여야 한다.
이러한 여건을 감안하여, 본 발명의 과제는 상술한 기술의 전력용 반도체 모듈을 토대로 단순하고 비용 절감을 달성할 수 있으며, 접촉 통공을 단순하고 신뢰성있게 구현할 수 있는 전력용 반도체 모듈을 제공하는데 있다.
본 발명에 따른 상기 과제는, 상술한 기술 분야의 전력용 반도체 모듈에서 합성 수지 시트층에는 각 접촉 통공의 영역에 논리 금속층의 자유 영역에 대한 공간이 형성되어 있으며, 얇은 배선의 유연성 부분이 상기 논리 금속층의 자유 영역 및 상기 공간을 통해 상기 합성 수지 시트로 연장되어 있고, 상기 논리 금속층 및 상기 전력용 반도체층과 접합을 통해 접촉됨으로써 달성된다.
본 발명에 따른 전력용 반도체 모듈은 상기 논리 금속층의 회로 구조 및 전 력용 금속층의 회로 구조가 공정에 의해, 즉 에칭에 의해 동시에 제조되는 것이 바람직하다. 상기 에칭 공정은 공지의 방법으로 실시된다. 경우에 따라, 순환 연속적으로 실시되는 결합 시트의 마스크 에칭 공정인 것이 유리할 수 있다.
본 발명에 따른 반도체 모듈의 논리 금속층은 구리층인 것이 바람직하고, 전력용 금속층은 알루미늄층인 것이 바람직하다. 상기 논리 금속층과 전력용 금속층 사이의 합성 수지 시트는 폴리이미드로 제조되는 것이 바람직하다.
본 발명의 반도체 모듈의 결합 시트는 논리 금속층, 전력용 금속층 및 이들 층과 바람직하게는 대면 접착된 합성 수지 시트로 구성된다.
본 발명에 따른 전력용 반도체 모듈의 결합 시트의 합성 수지 시트 내 공간은 바람직하게는 레이저에 의해 형성된다. 이를 위해, 예를 들면 CO2-표식(marking) 레이저가 충분히 사용가능하다.
각 접촉 통공의 얇은 배선은 바람직하게는 알루미늄으로 구성되며, 예를 들면 25~100 ㎛의 직경을 가질 수 있다. 상기 얇은 배선의 회로 구조의 얇은 논리 금속층과 또한 회로 구조의 두꺼운 전력용 금속층과의 접합은 적절한 방법으로 표준의 얇은 배선-결합제를 사용하여 수행될 수 있다.
본 발명에 따른 전력용 반도체 모듈의 이점은 각각의 접촉 통공이 매우 유연하고 신뢰성이 있으며, 논리 금속층과 전력용 금속층의 결합을 위한 얇은 배선이 상기 논리 금속층과 전력용 금속층의 유연성을 고려하여 유연성을 갖는다는데 있다.
각 접촉 통공은 얇은 배선의 접합 후 논리 금속층 및 전력용 금속층에 대해 압인할 수 있고, 필요한 경우 적절한 절연성 물질에 의해 코팅될 수 있다.
본 발명에 따른 전력용 반도체 모듈의 개략적이고 그 축척이 정확하지 않게 도시되어 있는 실시예의 후술하는 기술 내용으로부터 본 발명의 상세한 내용, 특징 및 이점이 명확해진다.
도 1은 기판(12), 결합 시트(14) 및 기판(12)과 결합 시트(14) 사이에 제공되는 전력용 반도체 구성 요소(16)를 포함하는 전력용 반도체 모듈(10)의 형태를 단면적으로 나타낸다. 전력용 반도체 구성 요소(16)는 컬렉터(18), 이미터(20) 및 게이트(22)를 갖는다.
상기 결합 시트는 얇은 전기 절연성 합성 수지 시트(24)를 포함하며, 합성 수지 시트(24)의 주요 면에는 회로 구조의 얇은 논리 금속층(26)이 제공되고, 반대 면에는 회로 구조의 전력용 금속층(28)이 제공되어 있다.
결합 시트(14)에는 전력용 반도체 구성 요소(16)와 접촉을 위해 사용되는 돌기(30)가 형성되어 있다.
회로 구조의 얇은 논리 금속층(26)과 회로 구조의 전력용 금속층(28) 사이에 접촉 통공(32)이 제공되어 있으며, 도 1에는 하나의 접촉 통공(32) 만이 도시되어 있으며, 도 2에는 확대된 크기로 도시되어 있지만 그 축척이 정확하지는 않다. 도 2에 명백히 나타낸 바와 같이, 각각의 접촉 통공(32)의 영역에는 전기 절연성 합성 수지 시트(24)가 공간(34)과 함께 형성되어 있다. 공간(34)은 논리 금속층(26)의 구조화를 통해 자유 영역(36)의 하부에 형성되어 있다.
얇은 배선(40)의 유연성 부분(38)은 말단부(42)에 의해 회로 구조의 논리 금속층(26)에 견고하게 접합된다. 이러한 접합 부위는 부호 44에 의해 표시된다. 상기 접합 부위의 반대편에는 얇은 배선(40)의 제2 말단부(46)가 회로 구조의 전력용 금속층(28)에 견고하게 접합된다. 상기 접합 부위는 부호 48에 의해 표시된다.
도 1 및 도 2에서 동일한 구성 요소는 동일한 부호에 의해 표시되므로, 도 1에 기재되어 있는 도 2의 구성 요소에 대해 상세하게 각각 기재할 필요가 없다.
이상 설명한 바와 같이, 본 발명의 전력용 반도체 모듈에 의하면, 단순하고 비용 절감을 달성할 수 있으며, 접촉 통공을 단순하고 신뢰성있게 구현할 수 있다.

Claims (9)

  1. 기판(12); 회로 구조의 얇은 논리 금속층(26)과, 상기 논리 금속층에 비해 두꺼운 회로 구조의 전력용 금속층(28), 및 그 사이의 얇은 전기 절연성 합성 수지 시트(24)를 포함하는 결합 시트(14); 및 기판(12)과 결합 시트(14) 사이에 적어도 하나의 전력용 반도체 구성 요소(16)를 포함하며, 결합 시트(14)에는 적어도 하나의 반도체 구성 요소(16)와 접촉을 위한 접촉 돌기(30)가 형성되어 있으며, 논리 금속층(26) 및 전력용 금속층(28) 사이에는 접촉 통공(32)이 제공되어 있는 전력용 반도체 모듈로서,
    합성 수지 시트(24)에는 각 접촉 통공(32)의 영역에 논리 금속층(26)의 자유 영역(36)에 대한 공간(34)이 형성되어 있으며, 얇은 배선(40)의 유연성 부분(38)이 논리 금속층(26)의 자유 영역(36) 및 공간(34)을 통해 합성 수지 시트(24)로 연장되어 있고, 논리 금속층(26) 및 전력용 반도체층(28)과 접합 부위(44, 48)를 통해 접촉되는 것을 특징으로 하는 전력용 반도체 모듈.
  2. 제 1항에 있어서, 논리 금속층(26) 및 전력용 금속층(28)의 회로 구조가 에칭에 의해 동시에 형성되는 것을 특징으로 하는 전력용 반도체 모듈.
  3. 제 1항에 있어서, 논리 금속층(26)이 구리층이고, 전력용 금속층(28)이 알루미늄층인 것을 특징으로 하는 전력용 반도체 모듈.
  4. 제 1항에 있어서, 합성 수지 시트(24)가 폴리이미드로 제조되는 것을 특징으로 하는 전력용 반도체 모듈.
  5. 제 1항 내지 제 4항 중 어느 한 항에 있어서, 논리 금속층(26) 및 전력용 금속층(28)이 합성 수지 시트(24)와 대면 접착되는 것을 특징으로 하는 전력용 반도체 모듈.
  6. 제 1항에 있어서, 합성 수지 시트(24) 내 각 공간(34)이 레이저에 의해 형성되는 것을 특징으로 하는 전력용 반도체 모듈.
  7. 제 1항에 있어서, 얇은 배선(40)이 알루미늄으로 구성되는 것을 특징으로 하는 전력용 반도체 모듈.
  8. 제 1항에 있어서, 얇은 배선(40)이 25~100 ㎛의 직경을 갖는 것을 특징으로 하는 전력용 반도체 모듈.
  9. 제 1항 내지 제 8항 중 어느 한 항에 있어서, 접촉 통공(32)이 절연성 물질로 코팅되는 것을 특징으로 하는 전력용 반도체 모듈.
KR1020060107601A 2005-11-09 2006-11-02 전력용 반도체 모듈 KR101271283B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005053398A DE102005053398B4 (de) 2005-11-09 2005-11-09 Leistungshalbleitermodul
DE102005053398.1 2005-11-09

Publications (2)

Publication Number Publication Date
KR20070049964A true KR20070049964A (ko) 2007-05-14
KR101271283B1 KR101271283B1 (ko) 2013-06-04

Family

ID=37845306

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060107601A KR101271283B1 (ko) 2005-11-09 2006-11-02 전력용 반도체 모듈

Country Status (10)

Country Link
US (1) US7638872B2 (ko)
EP (1) EP1786034B1 (ko)
JP (1) JP5134811B2 (ko)
KR (1) KR101271283B1 (ko)
CN (1) CN1964039B (ko)
AT (1) ATE497635T1 (ko)
BR (1) BRPI0604540A (ko)
DE (2) DE102005053398B4 (ko)
DK (1) DK1786034T3 (ko)
ES (1) ES2359256T3 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007044620A1 (de) 2007-09-19 2009-04-16 Semikron Elektronik Gmbh & Co. Kg Anordnung mit einer Verbindungseinrichtung und mindestens einem Halbleiterbauelement
DE102009017733B4 (de) * 2009-04-11 2011-12-08 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul mit einer Verbindungseinrichtung und mit als Kontaktfeder ausgebildeten internen Anschlusselementen
DE102010011719A1 (de) 2010-03-17 2011-09-22 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Herstellung einer elektrisch leitenden Verbindung eines Kontaktes mit einem Gegenkontakt
DE102010012457B4 (de) 2010-03-24 2015-07-30 Semikron Elektronik Gmbh & Co. Kg Schaltungsanordnung mit einer elektrischen Komponente und einer Verbundfolie
EP2688101A1 (en) * 2012-07-20 2014-01-22 ABB Technology AG Method for electrically connecting vertically positioned substrates
DE102013114438A1 (de) 2013-12-19 2015-06-25 Karlsruher Institut für Technologie Leistungselektronikmodul und Verfahren zur Herstellung eines Leistungselektronikmoduls

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3361869A (en) * 1965-04-16 1968-01-02 Western Electric Co Circuit board and method of connecting connectors thereto
US3474297A (en) * 1967-06-30 1969-10-21 Texas Instruments Inc Interconnection system for complex semiconductor arrays
US4064552A (en) * 1976-02-03 1977-12-20 Angelucci Thomas L Multilayer flexible printed circuit tape
JPH01110742A (ja) * 1987-10-23 1989-04-27 Ibiden Co Ltd 電子部品搭載用両面フィルムキャリア
US5573632A (en) * 1989-02-23 1996-11-12 Fuji Xerox Co., Ltd. Multilayer printed-circuit substrate, wiring substrate and process of producing the same
JP2801810B2 (ja) * 1992-04-14 1998-09-21 株式会社東芝 樹脂封止型半導体装置
US5412539A (en) * 1993-10-18 1995-05-02 Hughes Aircraft Company Multichip module with a mandrel-produced interconnecting decal
DE19617055C1 (de) * 1996-04-29 1997-06-26 Semikron Elektronik Gmbh Halbleiterleistungsmodul hoher Packungsdichte in Mehrschichtbauweise
US6773965B2 (en) * 1999-05-25 2004-08-10 Micron Technology, Inc. Semiconductor device, ball grid array connection system, and method of making
JP3679687B2 (ja) 2000-06-08 2005-08-03 三洋電機株式会社 混成集積回路装置
DE10065495C2 (de) * 2000-12-28 2002-11-14 Semikron Elektronik Gmbh Leistungshalbleitermodul
JP2002319596A (ja) 2001-04-20 2002-10-31 Denso Corp ワイヤボンディングを用いた接続方法および接続構造
DE10121970B4 (de) * 2001-05-05 2004-05-27 Semikron Elektronik Gmbh Leistungshalbleitermodul in Druckkontaktierung
DE10205450A1 (de) * 2002-02-08 2003-08-28 Infineon Technologies Ag Schaltungsträger und Herstellung desselben
DE10355925B4 (de) * 2003-11-29 2006-07-06 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul und Verfahren seiner Herstellung

Also Published As

Publication number Publication date
US20070102796A1 (en) 2007-05-10
CN1964039A (zh) 2007-05-16
DK1786034T3 (da) 2011-04-18
JP2007134715A (ja) 2007-05-31
DE102005053398A1 (de) 2007-05-16
DE502006008846D1 (de) 2011-03-17
US7638872B2 (en) 2009-12-29
DE102005053398B4 (de) 2008-12-24
KR101271283B1 (ko) 2013-06-04
ES2359256T3 (es) 2011-05-19
EP1786034A3 (de) 2008-07-09
BRPI0604540A (pt) 2007-08-28
EP1786034B1 (de) 2011-02-02
CN1964039B (zh) 2010-11-10
JP5134811B2 (ja) 2013-01-30
ATE497635T1 (de) 2011-02-15
EP1786034A2 (de) 2007-05-16

Similar Documents

Publication Publication Date Title
KR100560009B1 (ko) 반도체 장치
CN100530581C (zh) 一种利用互连结构制造半导体模块的方法
KR101319208B1 (ko) 전자 부품용 접속 소자
KR960009074A (ko) 반도체 장치 및 그 제조방법
KR960012397A (ko) 칩 사이즈 패키지형 반도체 장치의 제조 방법
KR101271283B1 (ko) 전력용 반도체 모듈
JP2006310630A (ja) 光半導体装置、及び光半導体装置製造方法
TW200504952A (en) Method of manufacturing semiconductor package and method of manufacturing semiconductor device
JP4111158B2 (ja) 圧力センサ
JP6733585B2 (ja) 半導体装置およびその製造方法
JP2007227452A (ja) フレキシブル配線基板及びそのはんだ接合方法並びにこれを用いた光送信パッケージ
US20040036158A1 (en) Tab tape, method of making same and semiconductor device
CN107785332A (zh) 半导体结构
JPH10125725A (ja) 半導体装置およびその製造方法
JP3293202B2 (ja) 半導体装置及びその製造方法
JPH0951018A (ja) 半導体装置およびその製造方法
JP2005072098A (ja) 半導体装置
US7601560B2 (en) Method for producing an electronic circuit
JP2000077465A (ja) 電子ユニット
JPH1146097A (ja) 樹脂成形回路基板
JPH09246331A (ja) 半導体装置の製造方法及びこれに用いる配線パターンフィルム
JP4111157B2 (ja) 圧力センサ
US8759981B2 (en) Method for the production of a fixed connection between two layers of a multilayer system, and multilayer system
JPH1145905A (ja) Icチップの接点変換構造と該接点変換構造の形成法
JP2004228603A (ja) 半導体装置および半導体装置の製造方法

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20160422

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20190422

Year of fee payment: 7