TW583758B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW583758B
TW583758B TW091134580A TW91134580A TW583758B TW 583758 B TW583758 B TW 583758B TW 091134580 A TW091134580 A TW 091134580A TW 91134580 A TW91134580 A TW 91134580A TW 583758 B TW583758 B TW 583758B
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Taiwan
Prior art keywords
electrode pads
wafer
semiconductor device
electrode
terminals
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TW091134580A
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English (en)
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TW200303605A (en
Inventor
Koichi Hirata
Tsutomu Aono
Osamu Isaki
Toshikazu Hirai
Tetsuro Asano
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Sanyo Electric Co
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Publication of TW200303605A publication Critical patent/TW200303605A/zh
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Publication of TW583758B publication Critical patent/TW583758B/zh

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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

583758
[發明所屬之技術領域] 本發明係有關於化合物半導體裝置者，尤係有關於可 使封件外形小形化之化合物半導體裝置者。 [先前技術] 行動電話等移動通信機器，係以使用GHz頻帶的微波 者多’且在天線之切換電路或在送收信之切換電路，多使 用切換此等南頻信號用之切換元件（例如特開平9 _丨8丨6 4 2 號）°此種元件’由於係使用於高頻，故以採用由珅化鎵 (GaAs)形成之場效電晶體（以下稱為FET)為多，隨著亦有 將上述切換電路予以積體化之單石微波積體電路（MM丨c )及 實現低失真或寬頻帶動作之混合用途之積體電路研發。 第6圖為習用之化合物半導體切換電路裝置電路圖。 該電路中，係在進行切換之FET1與FET2之輸出端〇UT1與 01^2與接地間連接分路（3]111111:扞£丁3、？£丁4，且在分路、 FET3、FET4之閘極施加與FET2及FET1控制端Ctl-2、CU-1 為互補之信號。其結果，在FET1為ON時，使分路FET4g ON，而FET2及分路FET3則為OFF者。 ” 在此電路中，若共用輸入端IN-輸出端OUT 1之信號通 路為ON，且將共用輸入端IN—輸出端out 2之信號通路為U 時，因為分路FET4為ON，故洩漏於輸出端0UT2之輸人作 號’將介由接地電容器C接地，因而可提昇隔絕性。° 第7圖係表示，該化合物半導體切換電路裝置積體化 之化合物半導體晶片示例。
將進行切換之FET1及FET2配置於GaAs基板左右之中央 部’而將分路FET3及分路FET4配置在左右之下方角落附X
314217.ptc 第8頁 583758 -案號91134^___h年/r月%日 倏正 五、發明說明（2) 近’並在各F Ε Τ之閑極連接電阻r 1、r 2、R 3及r 4。又將對 應於共用輸入端子IN、輸出端子〇un、〇υτ2、控制端子 CU-卜Ctl-2、及接地端子GND之焊墊（b〇nding pad)][、 (Η、02、Cb C2、G設置於基板周邊。且將分路FET3及分 路FET4之源極藉由接地電容器ca連接於接地端子GND。 第8圖係表示將第7圖中之晶片裝於導線架之圖。如第 8圖（A)所示，係由6接點之導線架所構成，在中央部配置 承座（header )40，且在承座40固定化合物半導體晶片4卜 該化合物半導體晶片4 1，具有如第7圖所示之圖案 (p a 11 e r η )延伸於一端之3條導線板4 2、4 3、4 4分別以焊接 線（bonding wire)連接於化合物半導體晶片41之控制端子 Ctl-2、共用輸入端in、控制端子ctl-1用之電極焊墊 (pad)C2、I、C卜導出於另一端之2條導線板45、47，則 分別以焊線連接化合物半導體晶片41之輸出端子0UT2、輸 出端子0 U T 1用之電極烊塾〇 2、0 1，而中央導線4 6則連接於 承座40作為接地端子GND。 如第8圖（B )(C )所示，半導體晶片係以導電焊膏8 5固 定於承座，並將各導線42、43、44、45、46、4 7之尖端露 出’而以下注模鑄（t r a n s f e r m ο 1 d )形成之樹脂層8 1予以 模塑。 發明所欲解_迭之課題 目前化合物半導體晶片係向小型化方向發展中，如第 9圖顯示，將上述半導體晶片之晶片尺寸予以縮小之構 造。其中，第9圖（A)為等效電路圖，而第9圖（B)係表示積 體化之晶片之一例。將電容以外加方式，或將F E T尺寸及
314217.ptc 第9頁 583758 月祝日 案號 91134fj«n 修正 五、發明說明（3) 配置合理化方式降低晶片尺寸者。可將習用 1. 07χ 〇· 5min降低到如第9圖（β) 0片尺寸 導體晶片，係沿晶片一邊配置於田5X 〇· 5mm。該半 用輸入端子用電極焊墊I、控制m子^電極焊墊c卜共 知斟的曰κ、嘉航里认f ?制知子用電極焊墊C2，而沿 相對的曰曰片邊配置輸出端子用電極焊墊 極焊墊CP、及輸出端子用電 逼谷知子用電 1 V川电徑乂于墊〇 2。由於 加，所以GND端子用電極焊墊g係由雷裳 替代，其餘構成元件則盘第^斤由_電//门子用電極焊藝cp 丁⑴兴弟〖圖所不者相同，故省略其說 日月0 八 第1 0圖顯示，將晶片固著於導線架之狀態。在此情 形，可將晶片尺寸縮小，以降低晶片成本，但是晶片料由 方向之尺寸（〇· 5mm)仍與第7圖所示之習用晶片相同。半導 體晶片+ 4 1 ’係以銀焊膏8 5等導電性黏合劑或非導電性黏合 劑固著=承座，而各焊墊電極由此處將焊接線8〇以放射狀 延伸’为別與各對應之導線連接。尤其，電容端子用電極 鮮塾cp係$承座以焊接線連結，並且連接於電容端子c， 唯用以固定晶片之銀焊膏的擴散難予控制，為了安定生 產 考慮银干賞之擴散而將導線予以擴大固定。亦即，雖 然使晶片尺寸縮小，仍然有為了安全性之問題而不能使整 個封裝體也隨之縮小。 現，’由於化合物半導體晶片尺寸之小型化進步且將 以廉價提供，所以在價格競爭上亦有勝於矽半導體晶片之 製品。然而，即使晶片之小型化進步，封裝體外形仍無法 予以小型化而維持原來之大尺寸，則其用途亦受到限制， 口而升y成無去將晶片尺寸之小型化反應於封裝體外形小型
314217.ptc 第10頁 583758 月如曰 修正 五、發明說明（4) 化之問題。 [發明内容] 本發明係有鑑於上述諸狀 裝置，具有：半導體a # . / ，‘、、， 提供—種半導體 於上述晶片之電用以固定該晶片之承座，·對應 連接上述電極焊墊及連結上述導 = = =yead);用以 I封固上述晶片、承座及導線板之樹浐声，衣置以及用以 置至少一個延伸於上述2條導 '曰於上述承座設 上述電極銲墊h何—，將連接於 部或上述突出部附近。 ’L 衣固疋於上述突出 由此，即使將承座做小 所以可提供可安定生產亦能使 線連結領域， 置。 1更封衣體小型化之半導體裝 [實施方式] ^恥第1圖至第5圖說明本發明之實施例如下. f 1圖係表示在導線架上固定化合物· :說導體晶片係與第9圖⑻所示者相^ 如第1圖所示，導線架係具有6接點之導線板，且在中 二在二…0上固定化合物半導體晶片 sk Ϊ ： 11 ： ： V：； .5Γ ^^ 丨U 口视千V體日日片51之控制端子Ctl — 2、共用輸 入端子IN、控制端子cu — i用電極焊墊C2、卜c卜又在導 ΐίΐ端之2條導線板55、57,則分別以焊接線連接於化 口 ‘體晶片51之輸出端子0UT2、輸出端子ουτί用電極
314217.ptc 第11頁 583758
焊墊02、0卜又將中央之導線板56,連結於承座5〇。且盥 化合物半導體晶片5 1之電容端子用電極焊墊cp連接。” 本發明之第1項特徵，係在於承座之形狀及承座線焊 接位置。而在承座5 0，係於各導線板間設置至少丨處突出 部1 ο〇插入其間。然後，將電容端子用電極焊墊2丈曰 接線連接於電容端子C之承座突出部丄〇 〇或突出部上〇 〇附于 近。 、 第2項特徵，係在於晶片固定位置。化合物半導體 51，並非固定於承座50中央，而係固定於偏離突出部" 之方向，所以可充分確保焊接於承座5〇之焊接線與苴兩 焊接線間之空間。 μ 第3項特徵，係在於橫跨晶片形成線焊接。先前技 術，係將焊接線，由各電極焊墊以放射狀固定於配置在其 外側之導線板，但是，以本發明之構造，係將固定於電^ 焊墊（在此處為電容端子用電極焊墊cp)以連接承座5 〇之焊 接線橫跨晶片上面延伸至固定在承座突出部1 〇 〇或其附 近。 f即，由於上述構造，在橫方向（χ軸方向）細小之承 座亦得以在突出部附近以焊接線連結。因而，即使在承座 上部之銀焊膏8 5擴散，仍可由焊接線連結於可確保焊接領 域之承座附近，所以可縮小承座尺寸，而使封裝體小型 化，且可安定生產。 在本實施形態中，係在承座設置多個突出部，且配置 於各導線板間。而將提供電容端子C之導線板5 6藉由外設 電容予以接地，且將連接控制端子Ct 1-1、Ct 1-2之導線板
314217.ptc 第12頁 583758 修正 案號 91134580 五、發明說明（6) 5 4、5 2 ’構成為僅施加直流之d C接點（p i n )，對高頻與接 地為等效’而於成為共用輸入端子〇之導線板53，成為輸 出端子OUT1之導線板57，及成為輸出端子out2導線板55 間’配置成對高頻為接地或接近接地之導線板或承座之突 出部’以提昇各高頻信號端子I N、〇UT1、⑽以間之隔絕 性。唯如特性上無問題，則承座之突出部，得僅作為一個 部位成為焊接線領域。 ffl 圖J系表不，將第1圖之晶片予以塑固之平面圖（第2 ΐ ΓίΓΐ圖（第2圖（B)、（C))。晶片51，係以導電焊 ^ 非導電焊膏固定於承座，將各導線52、53、54、 5 7之尖端露出，以下注模镇法、 塑固。此封裝體即稱為MCP6，小型化【s’曰' u 9_之尺寸。較第所_夕门j圣化為2. 0mmx 2. Immx 0. 寸為2 f 圖所不之同一晶片封襞體先前之封裝尺 寸為二.9mmx 2·8瞧已縮小許多。 間距，ΐ將突出部或其附近焊接之線需要適度之 度，因雖使長度較長但可限制高 又如^日片之溥形化有所貢獻。 此種封巢’ ^寻將晶片予以顛倒固定之構造。 若包括導線ΐ i rr:則:固部㈣^ 本菸明1 Γ 寸則與MCP6為同—尺寸。 限於電容端子用電極焊墊，而；;二!ίΐ】；：墊亦* 丨…丨咖珂冤極焊墊。如第
突出部或突出部附近，以^ f線領域確保於設在承座之 小型化者。因❿，只要可尺寸之縮小及封裝體之 在承座中央等任何位置。且;、領域，則可將晶片固定 583758 五、發明說明（7) 9圖（A)所示之電路圖中，因不需將外 容端子C之上，該端子可直接接地，而验二附s又在外加電 GND端子，X，相對於施加在附有外加電=::T = 1信號0/ + 3V，，亦有於控制端子施加〇/_3v控制信、號之之^換 第3圖係表示，本發明之第2實施 4項特徵’其與承座連接之電極焊塾 ’'置 '明之第 之同-線上，係、配置於較同一邊其他電極不焊配墊置之^ 片中央之位置。如第3圖（A)所示之晶片 =於晶 電極焊墊CP偏於晶片中央之外，其餘係與第啯電:第':用 (B)之構造完全相同。由此’如第3圖（B)所示， 9圖 =線連接之角度範圍得以擴大，因此焊接線位置之只施烊 棱昇，於是得將焊接線之不良率大幅度降低。 自由度 且將鄰接於電容端子用電極焊墊cp之電極 ，將0UT2端子用電極焊墊02，與悍接線離間距離大在此 侍以抑制插入損失之劣化。 、人，故 再以第4圖及第5圖表示，本發明第3實施形雜 GaAs & FET之混頻器（mixer)用積體電路裝置之=壯吏用 第4圖（A)係表示，混頻器積體電路裝置雷衣例。 將第1及第4之FET卜4之問極連接於共用間極 ^。係 將第2與第3之FET2、3之間極連接於共用間極’而 將第丨與第2之FEn、2之源極（或没極）連接於丘用且 :S2,而將第3與第eFET3、4之源極（或及極）則端 共用源極端子S1。並且，將第1與第3之FET1、 樓於 源極）與共用没極端子D1連接，而將第2與第把
314217.ptc 第14頁 —1 " .......... 4-^^.
/DO /DO 號 91134，(
修正 五、發明說明（8) 汲極（或源極）連接於Α田、 此種混頻器積體^路=極端子D2。 此種電路構成之混頻哭衣置，係用以變換頻率之裝置， 之平衡-不平衡變換哭°。 c破稱為雙平衡混頻器，係以外加 180。相位倒置之各^信號、L0信號、IF信號予以 壓，因而適合於需要^。u ’所以偶數次高諧波成分被抑 無線通信。且可使用磨失真之移動體通信機器等高頻數位 路用之混頻器。其動二，頻帶、’所以最適合於CATV調諧電
在閘極卜閘極2輸入LfVfi。’在源極1、源極2輸入RF信號而 信號。 ^號’然後由汲極1、汲極2取出I F 第4圖（B)係表示，g — 頻器電路裝置予以積體ί = f弟4圖ΛΑ)之化合物半導體混 在GaAS基板之中央部配二？半導體晶片之示例。 而將對應於問極端子Jat 1' FET2' FET3' FET4° 墊G2、S2配置於沪日片^源極端子S〇urce2之各電極焊 夕濟朽踹+ ς 邊之同一線上，且將連接於承座 用電極銲塾si配置於較該兩電極ΐί 曰曰片”，部。且將對應於間極端子…以、“3 = 科 端子Drain2之電極焊墊G卜Dl、D2配置於 沿晶片相對方之一邊之同一線上。 -置於 各端子用電極焊墊，如第4圖（ 有兩個：源極、汲極、及間極分別為共用、」I:個 州G1、G2及兩個源極端子用電極焊塾 S卜S2以及兩個汲極端子用電極焊墊M、s 二…V圖之晶片予以組裝後之-例。 ® )所不，ν線架（f rame)具有6接點之導線
583758 修正 案號91134如〇 五、發明說明（9)
半導^ ΐ :=。配乂置―承山座150 ’並在該承座150固定化合物 以r iT曰Γ * 。在一端之3條導線板1 5 2、1 5 3、1 5 4分別 接線連接於化合物半導體晶片51之 J 極端子用電極焊墊D1、汲極端子用電極焊墊/ 15=上1上6則與承座150連結，並與化合物半導體晶片 1之源極知子用電極焊墊s丨連接。 並將愈，Π至田夕5又置1處突出部2 〇 〇介入各導線板間， 部或突出部料。 斗接之焊接線固定於該突出 化合物半導體晶片，並不固定於承座中 偏離突出部方向位置，以充分 中央而固疋於 兩鄰焊接線間之空間。承^之焊接線與其 枝烊墊以放射狀固定於配置在其外 分电 明之構造，係固定於焊接在承 V Λ板，唯於本發 極端子用雷椏γ、妾在豕座電極焊墊（在此處為源 定)之銲線係橫跨於晶片上面而延伸固 疋於犬出〇卩或其附近。經由此部分 = 膏擴散仍可確保焊接線連、:領域領：以使 ^女疋組^生產’且可縮小承座之尺寸以實現封裝體小型 線上且接之電極焊塾，不配置於晶片邊之同- 中央之位置。由此，可將焊接線連 近曰曰片 可焊接線位置之自由度擴大而 n =，所以 不良率。 r田没|牛低烊接線連接時之 如第5圖⑻所示’各導線板152、153、154、出、
314217.ptc 第16頁 583758 案號 修」 五、發明說明（10) 1 5 6、1 5 7係將其尖端％ , 予以塑固。此種封麥二出而以下注模鑄法形成之樹脂層81 2_0m恥< 2.1mnp< 〇.9\^%4MCP6,其尺寸已小型化為 而且，因用以固定 、 度之間距，可做成M字；大出0部或其附近之焊接線需要適 制其高度而使晶片薄形’化狀之環狀’ I長度較長而仍可抑 上述混頻器用穡辦^ ° n 甘雙電路裝置，其晶片尺寸可為η κ x0.45mm’其先所裝罢 ^ ^ · 4 5 m m 罝係與第8圖相同之大型封株 ， 用本發明，則可利用 〃 i 了仵。如採 .^ 、笫1或第2實施例中之切換雷敗壯 相同之導線架，組裝於心伏电路装置 ^ ^ 衣於MCP6或MCPH6之已經小型化之私壯 體，所以可滿足行動+ — < 土1ϋ之封裝 求。而且，若共用=手機或catv調譜電路用途之需 成本。 換電路裝置之導線架，則可節省沖模 上述本毛明之貫施形態係以化 予以說明，但本發明甘丁阳6 — 丁〒瓶日日片為例 么土 L ^ 乃亚不限定於此實施形態，只要Λ捏垃 線連結於承座之晶片，心你Α丄…音Α 八聲為知接 果。 片 即使石夕半導體晶片亦可獲得同樣效 [發明之效果] t上所述，本發明可獲得如下各種效果。 可對：上：;由之在ί承f突出部或突出部附近連接焊接線， 日了 = ΐ 有所貢獻。先前在承座桿接焊接線 ^ , ^ ^ IV m ^电枉纟干墊將知接線以放射狀之最短距離
延伸而予以固定，但由於郃、卩曰AW ^ , _ . + π —由於銀烊肩擴散，致使晶片尺寸雖在 杈方向縮小，亦因連社捏垃綠、* 4立M d ^ „ ^ ^ ^4. "钚接線連接領域難於確保，導致封 I體之外形變大。然而，其拉士义 ^ 右私：本發明，可使焊接線橫跨晶
3l42l7.ptc 第17頁 583758 案號 911345Sn 五、發明說明（11)
修正 二上：延伸，因而可在承座突 域，所以承座可不必使用大型者。4其附近確保固定領 座中心部往突出部方向偏移固定j且因晶片位置，係由承 電極焊墊位置較其他電極焊墊$近使焊接線連結於承座之 之焊接線與其兩鄰之焊接線間確保充=，以使連接於承座 如此’使得先前為安定生產而不 ]封裝體尺寸縮小到2· Ommx 2. lmmx n 0 ^ u · 9 m m。且 m 曰 y 土仏 於中央而形成焊接線距離加長，但將焊接線纟M曰曰月禾位 形，使得對於薄形化有所貢獻。 、、做成M字狀環 第2，於組裝切換電路裝置時，承座突出部 線板間，因而與電容端子C連結導線板由外加g =伸於導 而且，與控制端子Ct 1-1、Ct 1-2連接之導線板各接地，’構成僅施 之較大尺寸 加直流之DC接點，在高頻與接地為等效，且在共 子I N之導線板、及輸出端子0 U T 1之導線板、以及 用輪 輪出 入 z八取 端 OUT2之導線板間，配置高頻時接地或近乎接地$ =出端子 承座突出部，所以，可提昇各高頻信號端子I N線板及 OUT2間之隔絕性。 Tl ' 第3，於組裝混頻器積體電路裝置時，可與G I c共用附裝有突出部之導線架。經由使導線架共換 降低沖壓模型成本，以實現裝配時之生產安定遍^ ’則可 型化之混頻器積體電路裝置。 衣懸小
314217.ptc 第18頁 583758 案號 91134580
圖式簡單說明 [圖式簡單說明]
第1圖：用以說明本發明之平面圖。 第2圖：用以說明本發明之（A)平面圖、 (C)剖視圖。 几’I視圖、 第3圖（A)及（B ):用以說明本發明之平面圖。 第4圖：用以說明本發明之（A)電路圖、^ ί- V 13 J 十 。 =圖：用以，明本發明之（A)平面圖、（B)剖視圖。 第6圖·用以說明習用技術之電路圖。 弟7圖·用以說明習用技術之平面圖。 第8圖：用以說明習用技術之（A)平面圖、（B)平面 圖、（C)剖視圖。 第9圖：用以說明先前技術之（a )電路圖、（B)平面 圖。 第1 0圖：用以說明先前技術之平面圖。 42、 43、 44、 45、 46、 47、 52、 53、 54、 55、 56、 57 152、153、154、155、156、157 導線板 50、 150 承座（header) 5 1、1 5 1 化合物半導體晶片 80 焊接線（bonding wire) 85 銀焊膏 100、 200 突出部
Dl、D2 没極端子用電極焊墊 G 1、G 2 閘極端子用電極焊墊 51、 S 2 源極端子用電極焊墊
314217.ptc 第19頁

Claims (1)

  1. 583758 _案號91134580_Λ年/P月抑曰 修正_ 六、申請專利範圍 1 . 一種半導體裝置，係具備： 半導體晶片； 用以固定該晶片之承座， 對應於上述晶片之電極焊墊配置之複數個導線 板； 用以焊接上述電極焊墊及上述導線板之連結機 構，以及， 用以封裝上述晶片、承座以及導線板樹脂層’ 且於上述承座至少設置一個延伸於上述兩條導線 板間之突出部，連接於上述任一電極焊墊之上述連結 機構固定於上述突出部或上述突出部附近者。 2. —種半導體裝置，具備： 設在半導體基板上之4個FET、兩個閘極端子用電 極焊墊、兩個源極端子用電極焊墊、兩個汲極端子用 電極焊墊，構成半導體混頻器積體電路之半導體晶 片； 用以固定該晶片之承座， 對應於上述晶片之電極焊墊而配置之複數個導線 板， 用以連接上述電極焊墊及上述導線板之連結機 構，以及 用以封裝上述晶片及承座以及導線板之樹脂層； 且係於上述承座至少設置一個延伸於上述兩條導 線板間之突出部，與任一上述電極焊墊連接之上述連
    314217.ptc 第20頁 583758 _案號 91134580_> 年 /p 月曰__ 六、申請專利範圍 結機構固定於上述突出部或上述突出部附近者。 3. 如申請專利範圍第2項之半導體裝置，其中，上述任一 電極焊墊為上述源極端子用電極焊墊之一者。 4. 一種半導體裝置，具備： 在半導體基板設置上至少具有兩個FET、一個輸入 端子用電極焊塾、至少一個控制端子用電極焊墊、兩 個輸出端子用電極焊墊及一個接地端子用電極焊墊或 電容端子用電極焊墊，以構成切換電路之半導體晶 片； 用以固定該晶片之承座， 對應於上述晶片之電極焊墊而配置之複數個導線 板， 用以連接上述電極焊墊及上述導線板之連結機 構，以及， 用以封裝上述晶片及承座以及導線板之樹脂層， 而在上述承座至少設置一個延伸於上述兩條導線 板間之突出部，以將連接於上述接地端子用電極焊墊 或電容端子用電極焊墊之上述連結機構固定於上述突 出部或上述突出部附近者。 5. 如申請專利範圍第1或第2或第4項之半導體裝置，其 中，係將上述晶片固定於上述承座上之偏離上述突出 部方向位置者。 6. 如申請專利範圍第1或第2或第4項之半導體裝置，其 中，係將固定於上述突出部或上述突出部附近之上述
    314217.ptc 第21頁 583758 案號91134580 A年A月日 修正 寸 六、申請專利範圍 連結機構延伸於上述晶片上面者。 7. 如申請專利範圍第1或第2或第4項之半導體裝置，其 中，與上述突出部或與上述突出部附近連接之上述電 極焊墊，係較沿上述晶片邊配置之其他電極焊墊配置 於靠近上述晶片中央部者。 8. 如申請專利範圍第1或第2或第4項之半導體裝置，其 中，係將連接上述突出部或上述突出部附近與上述電 極焊墊之連結機構以Μ字狀之環狀固定者。 9. 如申請專利範圍第1或第2或第4項之半導體裝置，其 中，係將上述晶片以導電性膠合劑或非導電性膠合劑 固定於上述承座者。 1 0 .如申請專利範圍第1或第4項之半導體裝置，其中，係 將挾住上述突出部而配置之上述導線板因上述突出部 而於高頻形成分離者。
    314217.ptc 第22頁
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