CN100353531C - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN100353531C
CN100353531C CNB031044468A CN03104446A CN100353531C CN 100353531 C CN100353531 C CN 100353531C CN B031044468 A CNB031044468 A CN B031044468A CN 03104446 A CN03104446 A CN 03104446A CN 100353531 C CN100353531 C CN 100353531C
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lead
electrode pad
chip
jut
base
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CN1441485A (zh
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平田耕一
伊佐木治
青野勉
平井利和
浅野哲郎
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Semiconductor Components Industries LLC
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Sanyo Electric Co Ltd
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Abstract

在底座上具有导线键合的电极焊盘的半导体芯片的情况下，由于不能控制Ag膏的扩散，难以确保固定区域，因而存在不能稳定生产的问题。另外，还如果实现了稳定生产，则封装外形就被不必要地变大的问题。本发明在底座上设置突起部，将芯片配置在与从突起部离开的方向错开的位置上，从而确保键合导线的固定区域。在底座上连接的电极焊盘比同一芯片边的其他电极焊盘配置得更靠近芯片中央，从这里开始到突起部或其附近使导线横切芯片地延伸、固定。由此实现封装的小型化和稳定生产。

Description

半导体器件
技术领域
本发明涉及化合物半导体器件，特别是可使封装外形小型化的化合物半导体器件。
背景技术
在携带电话等移动体用的通信仪器中，使用GHz频带的微波的情况很多，在天线的切换电路或发送接收的切换电路等中，很多使用用于切换这些高频信号的开关元件(例如特开平9-181642号)。由于是对高频进行操作，因而使用采用镓、和砷(GaAs)的场效应晶体管(以下称为FET)作为该元件的情况很多，与此相应，正在进行将所述开关电路本身集成化的单片微波集成电路(MMIC)或实现低失真或宽频带工作的混频器用途的集成电路的开发。
图6是到目前为止被实用化的化合物半导体开关电路装置的电路图。在该电路中，在进行开关的FET1和FET2的输出端子OUT1和OUT2与地之间连接分流FET3、FET4，在该分流FET3、FET4的栅极上施加送到FET2和FET1的控制端子Ct1-2、Ct1-1的互补信号。结果当FET1导通(ON)时分流FET4导通，FET2和分流FET3截止(OFF)。
在该电路中，在公共输入端子IN-输出端子OUT1的信号路径导通、公共输入端子IN-输出端子OUT2的信号路径截止的情况下，由于分流FET4导通，输入信号向输出端子OUT2的泄漏通过接地电容C流入地，可提高隔离性(Isolation)。
图7展示了将这种化合物半导体开关电路装置集成化的化合物半导体开关的一个例子。
在GaAs衬底上的左右中央部配置进行开关的FET1和FET2，将分流FET3和FET4配置在左右的下角部附近，在各FET的栅极连接电阻R1、R2、R3、R4。此外，与公共输入端子IN、输出端子OUT1、OUT2、控制端子Ct1-1、Ct1-2、接地端子GND对应的焊盘I、O1、O2、C1、C2、G设置在衬底的周边。而且，分流FET3和FET4的源极连接，并通过用于接地的电容CA连接到接地端子GND。
在图8中示出了将图7的芯片安装到框架上的图。如图8(A)所示，用6个管脚的引线框架构成，在中央部配置底座40，在该底座40上固定化合物半导体芯片41。化合物半导体芯片41具有图7所示的图形。借助于各键合导线80，在一端引出的三条引线42、43、44与化合物半导体芯片41的控制端子Ct1-2、公共输入端子IN、控制端子Ct1-1用的电极焊盘C2、I、C1连接。此外，借助于各键合导线，在另一端引出的两条引线45、47上连接化合物半导体芯片41的输出端子OUT2、输出端子OUT1用的电极焊盘O2、O1，中央的引线46与底座40连结，从而被提供给接地端子GND。
此外，如图8(B)、(C)所示，半导体芯片由导电膏85固定在底座上，将各引线42、43、44、45、46、47的前端露出，利用通过传递模塑法形成的树脂层81进行模制。
化合物半导体芯片正在向小型化方向发展。例如在图9中示出了缩减上述半导体芯片的芯片尺寸的结构，图9(A)是等效电路图，图9(B)示出了集成化的芯片的一个例子。它通过使电容外附，将FET尺寸或布局方法最佳化，使芯片尺寸减小，相对于以往的芯片尺寸1.07×0.5mm，图9(B)中芯片尺寸减小为0.55mm×0.5mm。这种半导体芯片沿芯片的一边配置控制端子用电极焊盘C1、公共输入端子用电极焊盘I、控制端子用电极焊盘C2，沿相对方向的芯片的边配置输出端子用电极焊盘O1、电容端子用电极焊盘CP、输出端子用电极焊盘O2。通过另外附加电容，GND端子用电极焊盘G变为电容端子用电极焊盘CP，此外的构成要素与图7相同，因而省略说明。
图10中示出将该芯片固定到框架上的图。在此情况下，作为芯片尺寸变小，可降低作为芯片的成本，但芯片沿Y轴方向的尺寸(0.5mm)与图7所示的以往芯片相比不变。半导体芯片41通过Ag膏85等导电性粘合剂或非导电性粘合剂固定在底座上，各焊盘电极从此处成放射状地延伸有键合导线80，从而与各自对应的引线连接。特别是，将电容端子用电极焊盘CP与底座导线键合，连接到电容端子C，但固定芯片的Ag膏的扩散难以控制，为稳定地生产，考虑到Ag膏的大量扩散而对导线进行固定。即，即使芯片尺寸变小，但仍存在为了稳定生产，不能使用尽可能利用芯片尺寸变小了的尺寸状态的小封装的问题。
现在，由于化合物半导体芯片尺寸进行了小型化、能够以低价格提供，因而在与硅半导体芯片的价格竞争中也有胜出的产品。但是，即使进行芯片的小型化，由于封装外形仍旧较大而限制了用途，因而还是存在芯片尺寸缩小化不能反应到封装缩小化的问题。
发明内容
本发明是鉴于上述各情况提出的，其特征在于包括半导体芯片，固定该芯片的底座，与所述芯片的电极焊盘对应地配置的多个引线，连接所述电极焊盘和所述引线的连接装置，以及密封所述芯片以及底座和引线的树脂层，在所述底座上至少设置一个在所述两条引线之间延伸的突起部，连接到所述电极焊盘的任意一个上的所述连接装置固定在所述突起部，所述芯片固定在所述底座上的与从所述突起部离开的方向错开的位置上。
由此即使底座较小也可确保导线键合区，所以可提供实现稳定生产，同时能够提供封装的小型化的半导体器件。
本发明还提供一种半导体器件，包括：半导体芯片，构成半导体混频器集成电路，其中，在半导体衬底上设置有4个FET，2个栅极端子用电极焊盘，2个源极端子用电极焊盘和2个漏极端子用电极焊盘；固定该芯片的底座；与所述芯片的电极焊盘对应地配置的多个引线；连接所述电极焊盘和所述引线的连接装置；以及密封所述芯片及底座及引线的树脂层；在所述底座上设置至少一个在所述两条引线之间延伸的突起部，与所述电极焊盘的任意一个连接的所述连接装置固定在所述突起部或所述突起部附近，其特征在于，所述芯片固定在所述底座上的与从所述突起部离开的方向错开的位置上。
本发明还提供一种半导体器件，包括：半导体芯片，构成开关电路，其中，在半导体衬底上设置有至少两个FET，1个输入端子用电极焊盘，至少一个控制端子用电极焊盘，2个输出端子用电极焊盘以及1个接地端子用电极焊盘或电容端子用电极焊盘；固定该芯片的底座；与所述芯片的电极焊盘对应地配置的多个引线；连接所述电极焊盘和所述引线的连接装置；以及密封所述芯片及底座及引线的树脂层；在所述底座上设置至少一个在所述两条引线之间延伸的突起部，与所述接地端子用电极焊盘或电容端子用电极焊盘连接的所述连接装置固定在所述突起部，其特征在于，所述芯片固定在所述底座上的与从所述突起部离开的方向错开的位置上。
附图说明
图1是用于说明本发明的平面图。
图2(A)是用于说明本发明的平面图，图2(B)是剖面图，图2(C)是剖面图。
图3是用于说明本发明的平面图。
图4(A)是用于说明本发明的电路图，图4(B)是平面图。
图5(A)是用于说明本发明的平面图，图5(B)是剖面图。
图6是用于说明现有技术的电路图。
图7是用于说明现有技术的平面图。
图8(A)是用于说明现有技术的平面图，图8(B)是平面图，图8(C)是剖面图。
图9(A)是用于说明现有技术的电路图，图9(B)是平面图。
图10是用于说明现有技术的平面图。
具体实施方式
以下参照图1到图5对本发明的实施例进行说明。
图1示出了将化合物半导体芯片固定到引线框架的一个例子。此外，由于化合物半导体芯片与图9(B)相同，因而省略说明。
如图1所示，框架具有6个管脚的引线，底座50配置在中央部，化合物半导体芯片51固定在该底座50上。借助于各键合导线80，在一端引出的三条引线52、53、54与化合物半导体芯片51的控制端子Ct1-2、公共输入端子IN、控制端子Ct1-1用的电极焊盘C2、I、C1连接。此外，借助于各键合导线，分别在另一端引出的两条引线55、57上连接化合物半导体芯片51的输出端子OUT2、输出端子OUT1用的电极焊盘O2、O1。此外，中央的引线56与底座50连结，与化合物半导体芯片51的电容端子用电极焊盘CP连接。
本发明的第1特征在于底座的形状和底座导线键合的位置。底座50设置有突起部100，使之在各引线之间至少插入1处。而且，借助于键合导线电容端子用电极焊盘CP连接到与电容端子C连接的底座的突起部100或突起部100附近。
此外，第2特征在于芯片的固定位置。化合物半导体芯片51不在底座50的中央，与从突起部100离开的方向错开地固定，可充分地确保连接到底座50的键合导线和其两个邻近的键合导线的间隔。
再有，作为第3特征，在于横切芯片进行导线键合。以往用于连接的键合导线固定在自各电极焊盘成放射状地配置在其外侧的引线上，而按照本发明的结构，在连接在底座50上的电极焊盘(在此为电容端子用电极焊盘CP)上固定的键合导线横切芯片上方而延伸，固定在底座的突起部100或其附近。
即，按照上述结构，即使是作为在横方向(X轴方向)上较小的底座也可能在突起部附近进行导线键合。因此即使在底座上Ag膏85扩散，由于可在可确保固定区域的底座的突起部附近进行导线键合，因而可缩小底座的尺寸，在可实现封装小型化方面，稳定生产变得可能。
在本实施例中，在底座上设置多个突起部，配置在各引线之间。即，提供电容端子C的引线56通过外附电容接地，与控制端子Ct1-1、Ct1-2连接的引线54、52构成只施加直流的DC管脚，与在高频状态下的接地等效，在成为公共输入端子IN的引线53、成为输出端子OUT1的引线57和成为输出端子OUT2的引线55之间配置在高频状态下接地或近似接地的引线或底座的突起部，由此可提高各高频信号端子IN、OUT1、OUT2之间的隔离性。但是如果没有特性方面的问题底座的突起也可以成为导线键合区域的1个部位。
在图2中示出了将图1的芯片模制的平面图(图2(A))和剖面图(图2(B)、(C))。芯片51由导电膏85或非导电膏固定在底座上，将各引线52、53、54、55、56、57的前端露出，利用通过传递模塑法形成的树脂层81进行模制。如果说该封装为MCP6，则被小型化为2.0mm×2.1mm×0.9mm。与图8所示的同一芯片的封装在以往为2.9mm×2.8mm×1.1mm的情况相比可大幅度缩小。
而且，由于在突起部或其附近固定的导线需要距离，通过做成M字形状的弯曲线，即使距离长也可限制高度，也可提供芯片的薄型化。
此外，如图2(C)，也同样可实现将芯片反向固定的结构。该结构如果说是MCPH6，尽管树脂模制部分比MCP6还大，但作为到引线前端为止所包含的尺寸为与MCP6相同的尺寸。
本发明要点是，通过确保在底座上设置的突起部或突起部附近的导线键合区域，实现底座尺寸的缩小或封装的小型化。因此，只要可确保足够的区域，芯片固定在底座上的中央等任何位置都可以。此外，与底座固定的电极焊盘也不限于电容端子用电极焊盘，哪个电极焊盘都可以。例如在图9(A)的电路图中，通过不在外附电容端子C上附加外附电容，而将该端子直接接地，使该端子名为GND端子，尽管向附加了外附电容的开关IC施加的控制信号是0/+3V，也有向控制端子施加0/-3V控制信号的开关IC。
图3中示出本发明的第2实施例。这也是本发明的第4特征，与底座连接的电极焊盘不在芯片边的同一条线上，而是比同一边侧的其它电极焊盘配置得更靠近芯片中央。图3(A)的芯片除电容端子用电极焊盘CP靠近芯片中央以外，与图1或图9(B)的结构完全相同。由此，如图3(B)，由于可导线键合的角度范围变大，所以导线键合位置的自由度扩大，可大幅度降低导线键合时的不良。
再有，由于可得到与电容端子用电极焊盘CP邻接的电极焊盘、这里是OUT2端子用电极焊盘O2和导线键合之间的间隔距离，因而可抑制插入损耗的劣化。
此外，使用图4和图5展示作为第3实施例的的例子，该例安装了采用GaAsFET的混频器用集成电路装置。
图4(A)中示出了混频器集成电路装置的电路图。第1和第4的FET1和FET4的栅极连接到公共栅极端子G1，第2和第3的FET2和FET3的栅极连接到公共栅极端子G2。此外，第1和第2的FET1和FET2的源极(或漏极)连接到公共源极端子S2，第3和第4的FET3和FET4的源极(或漏极)连接到公共源极端子S1。而且，第1和第3的FET1、FET3的漏极(或源极)与公共漏极端子D1连接，第2和第4的FET2、FET4的漏极(或源极)与公共漏极端子D2连接。
该混频器集成电路装置是进行频率变换的器件，该电路结构的混频器IC是被称为双平衡混频器的混频器，由于RF信号、LO信号、IF信号通过外附平衡-不平衡转换器分别变为反转了180°相位的各2信号，因而偶数次高频成分被抑制，特别是最适合于要求低失真的移动体通信仪器等的高频数字无线通信。而且由于可在宽的频带使用，因而最适合作为CATV调谐器用的混频器。形成向源极1、源极2输入RF信号，向栅极1、栅极2输入LO信号，从漏极1、漏极2取出IF信号的动作。
图4(B)示出了将图4(A)所示的化合物半导体混频器电路装置集成化的化合物半导体芯片的1个例子。
在GaAs衬底的中央部配置FET1、FET2、FET3、FET4。此外，与栅极端子Gate2、源极端子Source2对应的各电极焊盘G2、S2沿芯片的1个边配置在同一条线上，与底座连接的源极端子Source1用电极焊盘S1被配置成比这两个电极焊盘更靠近芯片中央。此外，与栅极端子Gate1、漏极端子Drain1、漏极端子Drain2对应的电极焊盘G1、D1、D2沿相对的芯片的1个边配置在同一条线上。
各端子用电极焊盘如图4(B)所示那样，在4个FET中，2个FET的源极、漏极、栅极分别共用，与2个栅极端子用电极焊盘G1、G2和2个源极端子用电极焊盘S1、S2以及2个漏极端子用电极焊盘D1、D2连接。
图5中示出了安装有图4的芯片的一个例子。
如图5(A)所示，框架具有6个管脚的引线，底座150配置在中央部，化合物半导体芯片151固定在该底座150上。借助于各键合导线，在一端引出的三条引线152、153、154与化合物半导体芯片51的栅极端子用电极焊盘G1、漏极端子用电极焊盘D1、漏极端子用电极焊盘D2连接。此外，借助于各键合导线，在另一端引出的两条引线155、157与化合物半导体芯片151的栅极端子用电极焊盘G2、源极端子用电极焊盘S2连接。此外，中央的引线156与底座150连结，与化合物半导体芯片151的源极端子用电极焊盘S1连接。
这里，底座150设置有突起部200，其在各引线之间插入至少1处，与源极端子用电极焊盘S1连接的键合导线固定在该突起部或突起部附近。
化合物半导体芯片不在底座的中央，与从突起部离开的方向错开地固定，可充分地确保连接到底座的键合导线和其两邻近键合导线之间的间隔。以往用于连接的键合导线固定在引线上，该引线从各电极焊盘成放射状地配置在其外侧，而如果按照本发明的结构，在被导线键合在底座上的电极焊盘(在此为源极端子用电极焊盘S1)上固定的键合导线被延伸并固定在突起部或其附近，从而横切芯片上方。通过确保在该部分上的导线键合区域，即使在底座上Ag膏85扩散，也可确保导线键合区域，在生产上和可稳定地组装上，可缩小底座的尺寸，可实现封装的小型化。
此外，与底座连接的电极焊盘不在芯片边的同一线上，而是比同一边侧的其它电极焊盘设置得更靠近芯片中央。由此，由于获得较大的导线键合可能的角度范围，所以导线键合位置的自由度扩大，可大幅度降低导线键合时的不良。
此外，如图5(B)所示，将各引线152、153、154、155、156、157的前端露出，利用通过传递模塑法形成的树脂层81进行模制。如果说该封装为MCP6，则被小型化为2.0mm×2.1mm×0.9mm。
而且，由于在突起部或其附近固定的导线需要距离，因而通过做成M字形状的弯曲线，即使距离长也可限制高度，可提供芯片的薄型化。
上述混频器用集成电路装置的芯片尺寸为0.45mm×0.45mm，在以往被安装到与图8同样大型的封装上。但是，如果应用本发明，可利用与第1或第2实施例的开关电路装置同样的框架，可安装在MCP6或MCPH6的小型化的封装中，所以可适应于作为携带电话终端或CATV调谐器的用途的需要。而且，通过和开关电路装置通用框架，可抑制冲压成形金属模的投资。
以上在本发明的实施例中作为例子说明了化合物半导体芯片，但并不限于此，只要是导线键合到底座上的芯片，即使是硅半导体芯片也可获得同样的效果。
如以上详细描述的，按照本发明获得以下种种效果。
第1，通过在底座的突起部或突起部附近进行导线键合，可提供封装的小型化。以往，在底座上进行导线键合的情况下，引线从对应的电极焊盘开始以最短的距离成放射状地延伸、固定，但由于Ag膏扩散，即使可在横方向上缩小芯片尺寸，也难以确保导线键合区域，使封装的外形变大。但是，按照本发明，由于使键合导线在芯片上方横切地延伸，确保在底座的突起部或其附近的固定区域，因而不使用大的底座也可以解决问题。而且，通过使芯片位置与从底座中心部开始的突起部离开的方向错开固定，在底座上导线键合的电极焊盘位置比其他电极焊盘更靠近中央，可充分地确保连接到底座的键合导线与其两个相邻键合导线之间的间隔。
由此，在以往为稳定生产采用了大一圈的封装，封装外形可小型化为2.0mm×2.1mm×0.9mm。此外，尽管由于芯片不在中央，使导线的距离变远，但由于将键合导线作成M字形状的弯曲线，也可提供薄型化。
第2，在安装开关电路装置的情况下，由于底座的突起部在引线之间延伸，所以在提供电容端子C的引线通过外置电容接地方面，与控制端子Ct1-1、Ct1-2连接的引线构成只施加直流的DC管脚，在高频时与接地等效，在成为公共输入端子IN的引线、成为输出端子OUT1的引线和成为输出端子OUT2的引线之间配置对于高频来说接地或近似接地的引线或底座的突起部，由此可提高各高频信号端子IN、OUT1、OUT2之间的隔离性。
第3，在安装混频器集成电路装置的情况下，附有突起部的框架可与GaAs芯片IC共用。即，通过使框架通用，可抑制冲压形成金属模的投资，可实现兼备组装时的稳定生产和封装小型化的混频器集成电路装置。

Claims (9)

1.一种半导体器件，包括：
半导体芯片；
固定该芯片的底座；
与所述芯片的电极焊盘对应地配置的多个引线；
连接所述电极焊盘和所述引线的连接装置；以及
密封所述芯片及底座及引线的树脂层；
在所述底座上设置至少一个在所述两条引线之间延伸的突起部，连接到所述电极焊盘的任意一个的所述连接装置固定在所述突起部，其特征在于，
所述芯片固定在所述底座上的与从所述突起部离开的方向错开的位置上。
2.一种半导体器件，包括：
半导体芯片，构成半导体混频器集成电路，其中，在半导体衬底上设置有4个FET，2个栅极端子用电极焊盘，2个源极端子用电极焊盘和2个漏极端子用电极焊盘；
固定该芯片的底座；
与所述芯片的电极焊盘对应地配置的多个引线；
连接所述电极焊盘和所述引线的连接装置；以及
密封所述芯片及底座及引线的树脂层；
在所述底座上设置至少一个在所述两条引线之间延伸的突起部，与所述电极焊盘的任意一个连接的所述连接装置固定在所述突起部，其特征在于，
所述芯片固定在所述底座上的与从所述突起部离开的方向错开的位置上。
3.如权利要求2的半导体器件，其特征在于，所述电极焊盘的任意一个是所述源极端子用电极焊盘中的一个。
4.一种半导体器件，包括：
半导体芯片，构成开关电路，其中，在半导体衬底上设置有至少两个FET，1个输入端子用电极焊盘，至少一个控制端子用电极焊盘，2个输出端子用电极焊盘以及1个接地端子用电极焊盘或电容端子用电极焊盘；
固定该芯片的底座；
与所述芯片的电极焊盘对应地配置的多个引线；
连接所述电极焊盘和所述引线的连接装置；以及
密封所述芯片及底座及引线的树脂层；
在所述底座上设置至少一个在所述两条引线之间延伸的突起部，与所述接地端子用电极焊盘或电容端子用电极焊盘连接的所述连接装置固定在所述突起部，其特征在于，
所述芯片固定在所述底座上的与从所述突起部离开的方向错开的位置上。
5.如权利要求1或2或4的半导体器件，其特征在于，固定在所述突起部或所述突起部附近的所述连接装置在所述芯片上方延伸。
6.如权利要求1或2或4的半导体器件，其特征在于，与沿所述芯片的边配置的其他电极焊盘相比，将与所述突起部或所述突起部附近连接的所述电极焊盘配置得更靠近所述芯片的中央部。
7.如权利要求1或2或4的半导体器件，其特征在于，连接所述突起部或所述突起部附近与所述电极焊盘的连接装置被按M字形状的弯曲线固定。
8.如权利要求1或2或4的半导体器件，其特征在于，所述芯片由导电性粘接剂或非导电性粘接剂固定在所述底座上。
9.如权利要求1或4的半导体器件，其特征在于，以夹持所述突起部的方式配置的所述引线被所述突起部高频分隔。
CNB031044468A 2002-02-27 2003-02-14 半导体器件 Expired - Fee Related CN100353531C (zh)

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EP1347514A3 (en) 2005-10-19
US6894371B2 (en) 2005-05-17

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