TW583722B - Circuit board and method for manufacturing same - Google Patents

Circuit board and method for manufacturing same Download PDF

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Publication number
TW583722B
TW583722B TW91114739A TW91114739A TW583722B TW 583722 B TW583722 B TW 583722B TW 91114739 A TW91114739 A TW 91114739A TW 91114739 A TW91114739 A TW 91114739A TW 583722 B TW583722 B TW 583722B
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Taiwan
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metal layer
circuit board
layer
patent application
metal
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TW91114739A
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English (en)
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Nobuyoshi Tatoh
Jun Yorita
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Sumitomo Electric Industries
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/11831—Reworking, e.g. shaping involving a chemical process, e.g. etching the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0597—Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1184—Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Metallurgy (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Description

五、發明說明（1 ) 發明領域 本發明揭示一種用於半導體裝置之陶瓷電路板，及一種 製造本電路板之方法，及一種高輸出模組。 半導體元件包括LD(雷射二極體成半導體雷射）、APD (雪崩光二極體）及其他此種光半導體元件；HEMT(高電子 移動電晶體）、HBT(外差雙極電晶體）、及其他使用GaAs (砷化鎵）、Inp(磷化銦）等之此種半導體元件可以高速來作 業；IGBT(絕緣閘極雙極電晶體）及其他此種反相器/電源轉 換器矽裝置；及BiTe(碲化鉍）及其他此種熱電半導體元件 ’而在這些領域中所使用電路板需要要有低電阻、良好熱 幅射、良好匹配之熱膨脹及超細微配線圖型用於更高整合 性及速度。 置用技術之說明 參照第4A-4F圖來說明習用路板。如第4A-4E圖所示 之迄今加工過程如下所述。在陶瓷基體1上施加金屬罩幕 或光罩2 (第4 A圖），以汽相沉積法（v a ρ 〇 r d e ρ 〇 s i t i ο η)或濺 射法來形成第一金屬層3,而且移去金屬罩幕或光罩2 (第4Β圖），隨後形成光阻層4(第4C圖），然後，以汽相 沉積法或濺射法來形成第二金屬層5，而且移除光阻層來 獲得一完整之產品（第4Ε圖）。 陶瓷基體1是由Α1Ν(氮化鋁）或氧化鋁來製成。例如， 在曰本專利公報第2-27 1 5 85號中所發表。第一金屬層使用 做爲電阻器，而其中大致使用TaN(氮化鉅）、NiCr(鉻化鎳） 或W(鎢）。第二金屬層使用爲配線或電感，而且具有包含 五、發明說明（2) Ti(鈦）/Mo(鉬）/Au(金）、Ti/pt(鉑）/Au、Cr/Mo/Au 或 Ti/V (釩）/Au之積疊結構（laminate structure)。本層使用鉅或鉻 來接觸陶瓷基體之原因，在增加對基體之黏著強度。因爲 鉑、鉬或釩在中間層具有高熔點（melting point)，所以它 被插置是爲了防止頂層（top layer)和金屬即上述接觸部份 所使用之鉅或鉻形成合金。金使用於頂層，其選擇是爲了 成功地實施接線搭接或打接（wire bonding或die bonding) 。第4F圖表示完成產品之材料組合實例。 利用功率半導體之基體以汽相沉積法電鍍法或熔化來施 加銅或金在陶瓷基體之整個頂表面上，然後以蝕刻來形成 配線圖型。 爲產生高輸出模組，在這些電路板上以打接（die bonding) 來固定半導體元件。 今曰之高輸出模組，除了僅縮減最後裝置之尺寸使得模 組更小之外，也需要使得配線圖型隨著縮減尺寸而更細微 ，使得可處理更高的頻率。而且也必需降低配線的金屬部 份之電阻，使得高頻特性損失降低而減少功率捎耗，爲本 目的，厚膜技術（thick-film techniques)來增加配線圖型之 厚度已變成必要。 爲同時滿足這兩者需求，使用於配線之金屬層厚度必需 至少5μιη(微米），而且在鄰接配線圖型線間之配線厚度Dhm) 及距離 L(pm)間的深寬比（aspect ratio)(D/L)爲 D/L> 0.4， 但是習用電路板不能受到加工處理來滿足這兩個要求。 原因在於已被塗覆有一厚膜光阻層之基體上，無法依賴以 -4- 583722 五、發明說明（3) 習用方式細微配線過程之金屬罩幕或光罩的汽相沉積法來 形成細微圖型，而且另一個原因在於汽相沉積必需連續長 時間以致獲得厚膜，所以實際的應用有困難。而且，當以 蝕刻法來形成配線圖型時，則實施小於配線厚度之配線圖 型的細微加工處理困難，因爲發生側蝕刻（side etching)， 而且蝕刻去除尤其困難之故。結果，不能獲得小型化、高 性能、高輸出模組。 發明之槪沭 本發明目的在提供一種具有厚膜細微配線圖型之電路板 ，及獲得小型化高性能高輸出模組。 爲解決上述問題，本發明的架構如下： (1) 電路板包含：第一金屬層，形成在陶瓷基體上之 圖型中；第二金屬層，形成在第一金屬層上之圖型中；及 第三金屬層，形成來覆蓋第二金屬層之整個頂表面及其大 部份之側表面；其中第三金屬層沒有覆蓋之第一金屬層及 局部第二金屬層以蝕刻法來縮減寬度。 (2) 根據上述（1)項之電路板，其中第一、第二及第三金 屬層之組合厚度D(pm)及鄰接圖型線路之間的距離ί(μηι) 滿足下列公式之關係。 D/L> 0.4 (3) 根據上述（1)或（2)項之電路板，其中第一、第二及第 三金屬層之組合厚度至少5 μηι。 (4) 根據上述（1)至（3)中任一項之電路板，其中第二金屬 層包括選自銅、鎳、銀及鋁所構成族群中之至少其一。 五、發明說明（5) 第4A-4E圖是製造習用電路板之步驟圖示；及 第4F圖表示所完成電路板中材料組合之圖示。 較佳實施例之詳細說明 本發明之電路板以下列步驟來製造。第一，在陶瓷基體 上，以汽相沉積或濺射對基體具有良好黏著力之第一金屬 層，諸如Ti/Mo/Ni。使用光罩以在第一金屬層上形成光阻 層圖型（photoresist pattern)。在本狀態中，該基體之整個 表面可做爲電極，所以在沒有光阻層之位置處以電鍍選擇 性地形成第二金屬厚膜。然後，光阻層變成薄膜層。第三 金屬層諸如金、Ni/Au或具有例如鈀、鉑、鉬、鎢或釩之 中間層（防止金擴散之層）插置在鎳及金層間的多層結構層 ，諸如Ni/Pt/Au層，以電鍍來覆蓋第二金屬層上。使得光 阻層變成上述薄膜層，允許電鍍來覆蓋第二金屬層之整個 頂表面及光阻層已移除之側面。然後，完全地移除光阻層。 然後，以蝕刻法來移除不被該第三金屬層所覆蓋的第一 金屬層。如果第三金屬層之最外層是不被在第一金屬層上 所使用触刻溶液所蝕刻的-層，則被第三金屬層所覆蓋的 該部份不會被蝕刻，其允許選擇性飩刻。例如，如果第三 金屬層之最外層是金，而且第一金屬層由Ti/Mo/Ni所構成 時，則金不會被用於鎳及鉬之蝕刻溶液所蝕刻，所以金在 本蝕刻中可使用做爲罩幕。鉅僅溶解在分離之氫氟酸基蝕 刻溶液中，但是因爲即使以本鈾刻溶液也不會蝕刻金，所 以其能作用於選擇性蝕刻之罩幕。 五、發明說明（7) 直立（straight upright)側之細微配線圖型。SOR(同步加速 器軌道照射）光使用於曝光。形成本厚膜光阻層，會使得 上述覃狀減至最小。 使用於電鍍之光阻層圖型精準度，是由次微米到1 〇奈 米之範圍。在光阻層線路間之微小間隔部份，可使用表面 活化劑（surfactant)來鍍敷。使得光阻層變成薄層，可以灰 化（ashing)等來獲得。 以本發明之電路板，第二金屬層較佳地包含至少選擇自 銅、鎳、銀及鋁之金屬中的其一金屬。以電鍍可形成至少 5μηι之厚膜。例如，即使是200μηι也可能。保持第二金 屬層之厚度在至少5μηι，降低配線之電阻，而且例如，可 適用於需要厚配線之熱電（thermoelectric)半導體元件，使 得熱應力降低，諸如Peltier元件。第二金屬層之實例包 括銅、Cu/Ni、Ni/Cu/Ni、鋁、Ni/Al/Ni、Al/Ni 及銀。如 果合金處理是隨後來實施而提高黏著力，則只有銅就可以 ;但是如果錬施加在銅之頂部至少〇 · 5 μ m厚度時，則黏著 在金或Ni/Au將較好。 最佳地使得第二金屬層之側表面儘可能地爲第三金屬層 所覆蓋。較佳地第三金屬層覆蓋第二金屬層之側表面至少 80%。覆蓋第二金屬層之側表面至少80%，導致在蝕刻第 一金屬層期間造成很微小側蝕刻。如果全部第二金屬層受 到覆蓋，則必需減少形成第二金屬層所使用之光阻層厚度 。然而，困難在均勻地減少光阻層厚度到第一金屬層的程 度。因此，在形成第三金屬層中，所使用於形成第二金屬 583722 五、發明說明（8) 層之光阻層做爲局部罩幕，所以整個第二金屬層沒有完全 爲第三金屬層所覆蓋。 第三金屬層之實例包含金、Ni/Au及其中中間層（用於防 止金擴散之層）諸如纟E、鉑、鉬、鎢或釩插置在鎳及金屬間 的多層結構諸如Ni/Pt/Au。第三金屬層之最外層可以是不 受使用於第一金屬層的蝕刻溶液所蝕刻的任何金屬，但是 就可較佳地實施後續步驟而言，使用金用於最外層尤佳。 以本發明之電路板，第二金屬層可以電鍍來形成，所以 金屬層可以是厚膜，而且可使用光阻層形成具有直接直立 側之細微配線圖型，因此可實施工作使得在配線圖型線路 間根據μιη之配線厚度D及根據μηι之距離L的深寬比（D/L) 爲D/L> 0.4。在本發明中，配線厚度D是第一、第二及第 三金屬層之結合厚度，線路間隔L表示在第三金屬層所覆 蓋第二金屬層圖型之線路間的距離。 氧化鋁可使用於陶瓷基體，但是因爲高輸出模組之熱幅 射很重要，所以較佳地使用鑽石或CBN、或包含A1N及/ 或Si3N4含量至少90重量百分比之陶瓷。A1N提供低成本 及高洩漏電阻基體。當需要強度時，較佳地使用Si3N4。 A1N及Si3N4之混合物也可使用。而且，如果基體表面太 粗糙時’則因爲所積疊第一金屬層之厚度，所以會產生不 連接，因此要實施表面處理。 本發明也提示一種包含至少一高輸出半導體元件之高輸 出模組，其產生至少1 OmW之熱，經由焊料或導電樹脂來 接合在上述所獲得之電路板上。 現在，本發明之實例將參照附圖來詳細說明。 -10- 五、發明說明（9) 實例1 在第2A圖中，具有A1N含量至少90重量百分比之高熱 幅射陶瓷基體，含釔及具有熱傳導率170W/(m · K )，使用 爲陶瓷基體Π。陶瓷基體之表面經表面處理到小於0.8 μπι 的表面粗糙度Ra。這是因爲後續積疊第一金屬層之厚度爲 0.5 μιη或更小，所以如果表面太粗糙，則可能發生不連接。 金屬罩幕12施加到陶瓷基體11，而形成NiCr金屬層 1 3爲最底金屬層。濺射裝置使用於本目的。雖然本層可 在基體之後續基體切割期間使用爲電阻器或做爲定位罩幕 ，而在此選擇NiCr層做用爲電阻層。第2B圖表示當金屬 罩幕12已經移除時之狀態，隨後做爲最外金屬層之NiCr 圖型保留在陶瓷基體之表面上。 其次，如第2C圖所示，Tr/Mo/Ni多層之第一金屬層14 汽相沉積在陶瓷基體1 1之整個頂表面上。鉬之厚度是 0.0 5μηι，鉬之厚度是0.0 5μηι，而鎳之厚度是0.3μπι。 其上使用光罩來形成光阻層，如第2D圖所示。考慮第二 金屬層之厚度，光阻層15之厚度是120 μηι。 其次，如第2Ε圖所示，由Ni/Cu所構成第二金屬層1 6 以電鍍來積疊。爲改善電鍍之黏著，鎳之厚度是0.5 μηι， 而銅厚度是1 ΟΟμηι。 如第2F圖所示，光阻層之厚度以〇2灰化來減少到ΙΟμηι 。如此處理因爲金鍍敷將實施到第二金屬層之側表面處的 銅部份。在本狀態中，電鍍由Ni/Au所構成第三金屬層致 -11- 583722 五、發明說明（1〇) 使覆蓋銅配線部份。鎳厚度是1.3μηι，而金厚度是1.〇μιτ1。 光阻層如第2G圖所示地移除，然後蝕刻鎳及鉬如第2Η 圖所示。在此，在光阻層去除期間形成鎳氧化膜在表面上， 所以移除本膜，然後，以反應性蝕刻溶液全部立即地蝕刻鎳 及鉬。鉬以氫氟酸基蝕刻溶液來移除。 第一、第二及第三金屬層之結合厚度是ΙΟΟμηι，而在圖型 線路間之距離Μμπι)是40μιη。在配線線路間之電阻是至少 1 ΜΩ，而所獲得電路板也具有優越絕緣。 在本實例中，金屬配線圖型形成在陶瓷基體之一側上， 但是也可施加到兩側。 實例2 具有第3圖所示的圖型之電路板，使用上述實例1之方 法來製造。在此配線層諸如第一金屬層是Ti/Mo/Ni而第二 金屬層是Ni/Cu，第三金屬層是Ni/Au，而電阻器層21是 Ni/Cr 〇高輸出LD(半導體雷射）18具有整合調變器 (i n t e 1· g r a t e d m 〇 d u 1 a t 〇 r)及至少1 0 m W熱產生，以焊料之 打接線來安裝在本電路板上，線打接是使用打接線1 9來 實施而製造第3圖所示之高輸出模組。在安裝LD之後， 模組作業，其中調變特性之SN比是0.1 dB，比較使用習 用電路板更佳。用於安裝LD之電路板大小僅是習用電路 板之1/4，而且速度限度增加到40Gbps或以上。 本發明使得可獲得具有厚膜細微配線圖型之小型化高性 能電路板。因此，可獲得小型化高性能高輸出模組。 -12- 583722 五、發明說明（11 ) 符號說明 卜1 1 陶瓷基體 2、12 金屬罩幕或光罩 3、14 第一金屬層 4、1 5 光阻層 5 第二金屬層 13 最底金屬層 16 第二金屬層 20 配線層 21 電阻器層 18 高輸出雷射二極體 19 打接線 -13-

Claims (1)

  1. 583722
    六、申請專利範圍 第 9 1 1 1 47 39 六申請專利範圍 1 . 一種電路板， 瓷基體上；第 層上；及第三 個頂表面及該 該第三金屬層 刻來縮減寬度 2 .如申請專利範 及第三金屬層 離Lpm，滿足_ 3 .如申請專利範 及第三金屬層 4 .如申請專利範 包括選自由銅 〇 5 .如申請專利範 之最外層是金 6 .如申請專利範 選自由氧化鋁 者且其量爲至 7 .如申請專利範 號「電路板及其製造方法」專利案 (92年1〇月17日修正本） 包含··第一金屬層，以圖型來形成在陶 二金屬層，以圖型來形成在該第一金屬 金屬層，形成來覆蓋該第二金屬層之整 第二金屬層之大部份側表面；其中不爲 所覆蓋之該第一及局部第二金屬層以蝕 〇 圍第1項之電路板，其中該第一、第二 之結合厚度ϋμιη及在鄰接圖型之間的距 f列公式之關係：D / L > 0 . 4。 圍第1項之電路板，其中該第一、第二 之結合厚度至少5μηι。 圍第1項之電路板，其中該第二金屬層 、鎳、銀及鋁所構成族群中之至少其一 圍第1項之電路板，其中該第三金屬層 〇 圍第1項之電路板，其中該電路板包含 、Α1Ν及Si3N4所構成族群中之至少一 少90重量百分比的量。 圍第1項之電路板，其中該電路板是鑽 583722 六、申請專利範圍 石或 c BN。 8 ·如申請專利範圍第1項之電路板，其中至少一產生至少 1 OmW熱量之高輸出半導體元件係經由焊料或電氣導電樹 脂接合於該電路板之上。 9 . 一種製造電路板之方法，包含下列步驟： 在陶瓷基體上汽相沉積或濺射第一金屬層； 形成圖型之光阻層； 使用該光阻層做爲罩幕，以電鍍在該第一金屬層上 來施加第二金屬層； 以電鍍在該第二金屬層之頂表面及該第二金屬層之 大部份側表面上來施加第三金屬層；及 去除該光阻層，然後蝕刻該第一金屬層，使得不爲該 第三金屬層所覆蓋的該第一及局部第二金屬層以蝕刻來 縮減寬度。 583722
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CN1396655A (zh) 2003-02-12
US6759599B2 (en) 2004-07-06
CA2391218A1 (en) 2003-01-05
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