TW569358B - Process for producing a semiconductor chip - Google Patents
Process for producing a semiconductor chip Download PDFInfo
- Publication number
- TW569358B TW569358B TW091133125A TW91133125A TW569358B TW 569358 B TW569358 B TW 569358B TW 091133125 A TW091133125 A TW 091133125A TW 91133125 A TW91133125 A TW 91133125A TW 569358 B TW569358 B TW 569358B
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- Prior art keywords
- wafer
- compound
- wafers
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- model
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 150000001875 compounds Chemical class 0.000 claims abstract description 40
- 239000011241 protective layer Substances 0.000 claims abstract description 21
- 235000012431 wafers Nutrition 0.000 claims description 208
- 239000002131 composite material Substances 0.000 claims description 29
- 239000011248 coating agent Substances 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 13
- 230000008030 elimination Effects 0.000 claims description 9
- 238000003379 elimination reaction Methods 0.000 claims description 9
- 239000010410 layer Substances 0.000 claims description 8
- 238000007639 printing Methods 0.000 claims description 7
- 229920000642 polymer Polymers 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 229920002635 polyurethane Polymers 0.000 claims description 2
- 239000004814 polyurethane Substances 0.000 claims description 2
- 239000002689 soil Substances 0.000 claims 2
- 239000000428 dust Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 229940125773 compound 10 Drugs 0.000 description 5
- ZLVXBBHTMQJRSX-VMGNSXQWSA-N jdtic Chemical compound C1([C@]2(C)CCN(C[C@@H]2C)C[C@H](C(C)C)NC(=O)[C@@H]2NCC3=CC(O)=CC=C3C2)=CC=CC(O)=C1 ZLVXBBHTMQJRSX-VMGNSXQWSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- QBWKPGNFQQJGFY-QLFBSQMISA-N 3-[(1r)-1-[(2r,6s)-2,6-dimethylmorpholin-4-yl]ethyl]-n-[6-methyl-3-(1h-pyrazol-4-yl)imidazo[1,2-a]pyrazin-8-yl]-1,2-thiazol-5-amine Chemical compound N1([C@H](C)C2=NSC(NC=3C4=NC=C(N4C=C(C)N=3)C3=CNN=C3)=C2)C[C@H](C)O[C@H](C)C1 QBWKPGNFQQJGFY-QLFBSQMISA-N 0.000 description 2
- 229940125846 compound 25 Drugs 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- AOSZTAHDEDLTLQ-AZKQZHLXSA-N (1S,2S,4R,8S,9S,11S,12R,13S,19S)-6-[(3-chlorophenyl)methyl]-12,19-difluoro-11-hydroxy-8-(2-hydroxyacetyl)-9,13-dimethyl-6-azapentacyclo[10.8.0.02,9.04,8.013,18]icosa-14,17-dien-16-one Chemical compound C([C@@H]1C[C@H]2[C@H]3[C@]([C@]4(C=CC(=O)C=C4[C@@H](F)C3)C)(F)[C@@H](O)C[C@@]2([C@@]1(C1)C(=O)CO)C)N1CC1=CC=CC(Cl)=C1 AOSZTAHDEDLTLQ-AZKQZHLXSA-N 0.000 description 1
- KQZLRWGGWXJPOS-NLFPWZOASA-N 1-[(1R)-1-(2,4-dichlorophenyl)ethyl]-6-[(4S,5R)-4-[(2S)-2-(hydroxymethyl)pyrrolidin-1-yl]-5-methylcyclohexen-1-yl]pyrazolo[3,4-b]pyrazine-3-carbonitrile Chemical compound ClC1=C(C=CC(=C1)Cl)[C@@H](C)N1N=C(C=2C1=NC(=CN=2)C1=CC[C@@H]([C@@H](C1)C)N1[C@@H](CCC1)CO)C#N KQZLRWGGWXJPOS-NLFPWZOASA-N 0.000 description 1
- 229940126657 Compound 17 Drugs 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 235000014443 Pyrus communis Nutrition 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LJOOWESTVASNOG-UFJKPHDISA-N [(1s,3r,4ar,7s,8s,8as)-3-hydroxy-8-[2-[(4r)-4-hydroxy-6-oxooxan-2-yl]ethyl]-7-methyl-1,2,3,4,4a,7,8,8a-octahydronaphthalen-1-yl] (2s)-2-methylbutanoate Chemical compound C([C@H]1[C@@H](C)C=C[C@H]2C[C@@H](O)C[C@@H]([C@H]12)OC(=O)[C@@H](C)CC)CC1C[C@@H](O)CC(=O)O1 LJOOWESTVASNOG-UFJKPHDISA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 229940127204 compound 29 Drugs 0.000 description 1
- 229940125877 compound 31 Drugs 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Dicing (AREA)
Description
569358 ⑴ 玖、發明說明 (=說明應敘明:發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) 發明與製造具有在一晶片側邊突出之接觸元件之半導 體晶片的方法相關。 晶圓層級封裝係為製造晶片尺寸封裝之特職本效益之 ^法’即是說晶片之尺寸之組件。這些組件係藉由覆晶技 付之方法’以活動面在底部被焊接或依附地黏合至電路板 ^模組板,而並沒有進一步地被覆蓋(在板上晶片Η皮稱 為”凸塊"之使用之接觸元件,在該情況下係為堅硬的凸塊 (錫錯或金凸塊)或柔軟、具彈性的聚合物凸塊(軟凸塊) 其被父錯連線至晶片之連接塾而連接。 在晶圓層級封裝之背景内,已經知道在晶片被切割該晶 回而分開之前’塗覆個別晶片形成之晶圓之背面,以此方 式為了保護該在分開晶片已經被安裝至電路板或模組板之 後被暴露之背面。此在當駐留在電路板或模組板時處理晶 片之背景内且甚至在該駐留之電路板或該模組板本身係為 特別地有用。然而,時常傷害發生至裸晶片在該提供具有 接觸元件之晶片侧邊之區域中,該傷害係為不好的且可能 導致晶片失敗。 本發明以指定消除前述缺點之可能方式的問題為基礎。 為了解決該問題’在開始時提及之形式之方法中,本發 明提供具有接觸元件之晶片側邊,其以形成保護層之覆蓋 複合物塗覆’其中該突出接觸元件從該保護層突出。 根據本發明目的塗覆具有接觸元件之晶片側邊的方法, 即是施加一保護該塗覆之半導體材料不受傷害之保護層至 -6- 569358
該晶片側邊。同時,必須小心選擇保護層之厚度使得已經 形成之接觸元件仍然突出足夠遠離層表面以為了其隨後可 能製造在該晶片和電路板或模組板之間之可靠接觸。 然而’此之另一選擇,係為其也可能完全地嵌入接觸元 件在該保護層中且之後藉由適當方法(蝕刻、雷射)暴露接 觸元件之接觸點。 在晶圓層級封裝之背景内產生該塗覆係為特別地有利, 即疋說複數個晶片同時以複合物塗覆。在該關聯中,可以 兩種不同方式貫施晶圓層級封裝。首先,使用可由在其上 形成之晶片之晶圓而製造,其中該晶片並沒有被分開且其 之接觸7G件已經產生使得該封裝為”真的,,晶圓層級封裝。 或者,如下面進一步描述,對於複數個分開之晶片被適當 地排列,所以因為其排列形成類晶圓,而被共同地塗覆也 是有可能的。 在該情況下,假如該分開之晶片或晶圓係為起始地在依 附载體上,特別i也’為一膜上排列,在前述之後實施塗覆 ,係為有利的。所以該等個別晶片被該載體固定在其位置 中’在此存在可能性,首先直接排列該晶片在其他晶片之 旁或以任何所需距離將該晶片互相間隔開。當使用個別晶 二片時,假如僅使用該等已測試晶片,且發現在先前功能測 ^中可用的’使得以此方已知良好晶片晶圓被組裝且 包括有用之晶片,使得其可隨後地假設根據本發明方法 所生產之半導體晶片也實際上正常運作,係為特別地有利 功此不運作之晶片因此先前已經被分開。 569358
亚且’其為特別地有用,假如在分開晶片之情況下,除 了该負載接觸元件之晶片側邊之外,該接合側邊邊緣也以 複合物塗覆。所以,在該情況下晶片也在該複合物側邊地 形成且該側邊邊緣也以保護層覆蓋。在該情況下,特別地 ’在晶片側邊之邊緣部份中突出朝向相鄰側邊邊緣之風險 被排除。 為了進一步改進半導體晶片之保護,在分開晶片之情況 下,根據本發明可以提供,在晶片之背側邊,至少在一些 區域,主在在邊緣區域,也額外地以複合物塗覆。所以, 假如負載接觸疋件之晶片側邊、側邊邊緣兩者和晶片背側 邊之至;一些區域被塗覆時,之後該晶片以最大可能範圍 被肷入而提供完全之邊緣保護。 根據第-發明之另一方法,提供分開晶片或附在晶圓之 曰曰片被排列在模型中,該模型之上層模型施加壓力於該等 晶片至下層模型,輕微地壓縮具彈性之接觸元件,在該步 驟之後,ρ通後保護層之複合物被引進該模型且被消除。本 發明之組成設定係以具彈性接觸元件為基礎,即是說,例 如具彈性聚合物凸塊,其在分開晶片上形成而依附地黏合 至載體膜二例如或是在尚未切開之晶圓上。該等分開晶片_ 其不疋在實際上分開之排列或是以具有載體膜之,,已知良 =晶圓”之形式.或是晶圓被插人至模型中,該—半模型施 壓於4專aa片或疋晶圓至另_半模型。此導致具彈性之接 觸元件稍微被壓縮,變形僅有少許微米,例如約5〇微米。 此表示在晶片側邊和對面半模型之間的距離被具彈性接觸 569358 \ J W^SSKSsasBsmm^m 元件之壓縮而稍微減少。之後該複合物引進該模型,主要 為注入’使得其在晶片側邊和該一半模型之間之區域中分 散。在消除複合物之後,該模型被打開且被壓縮之具彈性 接觸元件被釋放。該元件擴張且回復其原始較大形^,其 中該元件之後從被消除之保護層突出。 〃 該方法之另一方法係為,在晶圓插入該模型之前,保蠖 層之複合物可早被引進至該模型中(例如,以粉、糊狀' 小塊,…)。在該情況下,在具彈性接觸元件之晶圓被壓縮 之前’該複合物被銘:化。 雖然描述之本發明之另一方法係使用僅有具彈性接觸元 件之晶片,但是在下描述之發明之另外方法可在具彈性接 觸元件之晶片和具堅硬接觸元件之晶片兩者中使用。根據 本發明之具體實施例,提供分開晶片或附在晶圓之晶片被 排列在模型中,該模型之一半具有突出接觸元件以晶片側 邊稍微與一半模型間隔開之方式與其前面區域接合之凹地 ,在該步驟之後,在模型密合之後,引進複合物且被消除 。排列該凹地以與在晶片上接觸元件之位置對應,使得其 確保一接觸元件實際上也接合在一凹地中。藉由該接合之 方法,該晶片相對於一半模型之表面稍微被降低,使得在 複合物之注入和消除之後,該接觸元件從被消除之保護層 突出’而其前面區域容納在方法中之凹地中。 為了將引進至該模型之分開晶片之側邊邊緣也同時塗覆 ,假如該等分開晶片在載體上,特別地為膜,互相地分開 排列係為有利的。如在開始已經描述,在載體上以任何所 569358
(5) 需的距離排列該晶片以形成"類晶圓"係可能的。假如間隔 開之晶片之排列之後被引進至該模型中,注入之複合物不 · 僅可被散佈在sa片側邊和模型表面之間之區域且也在個別 晶片之間之區域中。以該方式,該等晶片也可在其側邊邊 . 緣之區域中之複合物中嵌入,使得一保護層可被形成。 , 最後,也為了允許該晶片之背側邊以複合物至少部分地 塗覆,假如使用結構化之上層模型係為有利的,因為該模 型作用在晶片背側邊僅在點上,主要在其中心,使得該剩 · 下之空晶片背側邊也以複合物塗覆。所以與晶片背面側邊 相關之一半模型以該注入複合物可覆蓋晶片背面側邊至少 在邊緣之方法結構化,使得也可在該地方產生保護層。 在每個情況下,已經被分開但是互相間隔開排列之該等 晶片,可以說,係藉由複合物所形成之保持框架中之複合 · 物所内嵌。假如之後以此方式注入模型之晶片排列或僅在 晶片側邊塗覆之具有接觸元件之晶圓從該模型移除時,之 後該等晶片,假如需要的話,在載體移除之後,被分開。 此藉由分開形成保持框架之消除複合物或藉由適當方法, 馨 例如切割或雷射切割或喷水切割或該等方法之混和,分開 晶圓而完成。 除了使用模型和注入或預先供給複合物之上述方法,在 印刷方法中,另外複合物也可施加至晶片側邊,假如適當 的話’在側邊邊緣和晶片背側邊之至少一部分。或者,在 分配方法中施加複合物也是可能的。 亚且,假如在被複合物塗覆之前或之後,該晶片背侧邊 · -10- (6) (6)569358 假如適當的話,其仍暴露之地方,以進一步之複合物塗 覆係為有利的。該額外背面保護層可在根據如上所選擇 之方去塗覆之前提供。假如之後實施的話,之後,取決於 使用’根據本發明之另外方法,該晶片背面也可完全地空 或疋至j/部分地主要在邊緣以第一複合物塗覆。此時, =後全地以第二複合物覆蓋背側邊或是同樣地覆蓋仍然 二白之$側邊區域係為可能的。在該情況下,晶片背側邊 之塗覆可在印刷方法、分配方法、賤擊方法或是在注 型中實施。 ^ 除了 5亥方法之外,本發明尚與半導體晶片相關,該晶片 特別地根據描述之方法產生,其具有在一晶片侧邊上突出 之堅硬或具彈性接觸元件。該半導體晶片由下列事實區別 •具有接觸兀件之晶片側邊以形成保護層之覆蓋複合物塗 覆,該突出接觸元件從該層突出。除了晶片側邊本身之外 ^有接觸元件之連接該晶片側邊之側邊邊緣也可以複合 物塗覆。此外,該晶片背面側邊也可以複合物覆蓋,至少 在些區域中,主要在邊緣區域,以形成保護層。為了完 整之封裝,該晶片背側^,假如適當的話,其仍要暴露之 範圍,也可以進一步之滿人你+ ^ ” /之稷a物塗覆。禝合物本身,以 如適田的活’ 5亥進_步複合物係為以聚合物主 性複合物。 开等冤 使用以塗覆具接觸;从+ # s u 觸凡件之该θ曰片側邊之複合物應為較佳 地不良地依附至接觸开I r且踩# 丧觸凡件(具弹性凸塊,例如矽)且
樣地不良地依附至接鰥斤杜夕紅化人U 主接觸兀件之任何金屬塗覆( -11- (7) 569358
吏,從個別接觸元件引導至晶片之接觸墊之交錯線導體執 之彈性不會被實質地傷害。 口圖1顯示前端晶圓丨,在顯示之範例中,3個晶片2在該晶 圓上形成作為範例。該晶圓尚未被分開。例如在印刷方 中’在該前端晶圓1上,在主動晶片側邊,產生軟、具彈性 之接觸元件3,且具有一交錯線層4 ,經由該交錯線層其被
連接至在晶片上之接觸塾。該軟具彈性接觸元件通常由 組成且係為導電或非導電的。 在接觸7L件產生之後,該晶圓可接受晶圓層級測試,以 測試個別晶片關於可㈣。在情況中,有錯之晶片可抑 測0 、 在圖2中,該晶片例如藉由切割從前端晶圓分開。 之後’從該等分開晶片,見圖3,該等被測試為可用之晶 片2依附地黏合至載體5’在此為具自依附表面之載體膜, 其接觸元件指向載體5。如可看見的,該等晶片以互相隔一 ㈣而排列’該距離係比其已經在實際晶圓上產生之間距
還大的夕、&由載體5固^之晶片排列可被稱為類晶圓, 因為整個晶片排列像晶圓一般處理。 該方法之另外選擇係為,減在切割膜上散佈之晶圓也 可使用。在該情況下,在膜上之分開晶片可藉由將膜拉開 ("racking”)而進一步地間隔開。 在根據圖4之步驟中,該晶片排列6之後在模型中排列, 該模型包括-下層一半模型7和上層一半模型8,在此也顯 示-些細節。在晶片之背侧邊9支持之該上層一半模狀 •12- 569358
⑻ 後稍微施壓晶片2至該下層一半模型7,使得該接觸元件3 被稍微地壓縮。變形之程度係為些許微米,例如5〇微米。 作為一選項,一膜也可在上層一半模型和晶片之背側邊之 間被夾住’以產生在該兩半模型之間之防漏連接且防止複 合物10流出。 之後,如圖5顯示,複合物1 〇注入該模型,且在主動晶片 側邊之間散佈,該側邊支持該接觸元件3 ,(空隙)以及在晶
片2之間的區域中。該晶片排列6遺留在該模型中直到該複 合物10已經完全地或至少部分地被消除。該模型之後被打 開,且内嵌在該消除複合物10中之晶片排列6從該模型移除 。該消除複合物10形成保持框架之形式,在其中該等晶片2 被内嵌。如圖6顯示,在負載釋放且從模型移除之後,該接 觸元件3擴張而回覆其原始形式,其中該等接觸元件從複合 物10或從複合物之表面U突出至其較早變形之範圍。可看 見’見圖6,該載體5從複合物之表㈣猶微間隔開,其可 被歸因於接觸元件3之伸展。
假如之後載體5被拿下,其為容易的且可能的,因為由消 除複合物1G所形成之保持框架足夠地穩定,該等個別晶片2 可被切割或分割消除複合物1〇而分開。如可看見,晶片完 全地内嵌在複合物中在其具有接觸元件之主動晶片侧邊, 和在側邊邊緣兩者,該等接觸元件仍然繼續向前足夠地突 出以讓接觸在晶片和電路板或模組板之間可靠地產生。 在此點Ji應、„亥才曰出,有一可能性,在晶片排列已經從 該模型移除之後’在額外方法步驟中以進_步複合物塗覆 -13· 569358
⑺ 晶片背側邊9而也為了以保護覆蓋裝載該侧邊。該步驟在晶 片分開之前有利地實施。 圖8和圖10顯示相似於該描述之方法變化之方法變化,但 疋该最後處理過之前端晶圓12本身被使用,複數個晶片丨3 . 已經同樣地被形成且提供具有接觸元件14,而被放入包括 兩一半模型15、16之模型,當該等一半模型被移在一起時 該接觸元件14在此也稍微被壓縮。之後複合物丨7被注入。 在以包括消除複合物17之保護層之方式在主動側邊塗覆之 · 晶圓12移除之後,施加進一步複合物丨8至晶片背側邊,例 如在印刷方法中,以形成一保護層,在該步驟之後該等個 別晶片13被分開。在此範圍藉由範例方法在此說明之方法 對應至根據圖1 -7之方法,在該方法中,該等接觸元件被稍 — 微壓縮以確保其從隨後產生之保護層突出。為了與從第一 · 次提及之具體實施例中分開晶片區別,在此使用完全晶圓 。然而根據圖1 -7在方法中主動晶片側邊和側邊邊緣可由塗 覆所覆蓋,在根據圖8 -10中僅有主動側邊可被塗覆。 圖11顯示根據本發明之第三方法變化。並且,在此使用 在前端處理且具有在其上形成大數目晶片2〇之晶圓19,該 4曰曰片2 0已經k供具有接觸元件21。之後晶圓丨9插入具有 一上層和下層一半模型22、23之模型,該下層一半模型, 在顯不之範例中,具有凹地24,在其中,見圖12,該等接 觸元件21與其前端區域接合。在該模型已經被關閉之後, 複合物25被注入且充填在前晶片側邊和模型表面之間的空 · 間。在該複合物被消除之後,晶圓丨9從該模型移除,該等 -14- 569358
(ίο) 接觸元件2 1從複合物25突出而在注入成梨期間其區域在凹 地24中容納。並且在此,假如適當的話,在背側邊塗覆之 先前應用之後,隨後實施晶片之分開。 在此,應該指出,在該方法變化中,該等接觸元件2 1可 以是具彈性的或是堅硬的,因為其並不需被變形。
圖13顯示放大詳細檢視之形式的晶片26。可看到該等接 觸元件27如何從複合物29之表面28突出。在該情況下該使 用之複合物應該確保其並不依附至該等接觸元件27,因為 其為實際堅硬或具彈性接觸材料或交錯線,使得其並不妨 礙具彈性接觸元件27之擴張。如圖13顯示,在理想情況下 ,複合物29甚至從接觸元件27稍微分開。 圖14顯示根據本發明之半導體晶片3〇之進一步具體實施 例。後者以複合物3 1,如可看見,在在側邊邊緣之區域中 之晶片前端側邊,和在邊緣之晶片背面側邊兩者塗覆。該 晶片背面側邊32在未塗覆區域中暴露。此可例如藉由使用 模型而達成,該模型留在晶片側邊32上僅在中央區域,使
得複合物31可以覆蓋在邊緣側邊之晶片區域中的晶 側邊32。 1後’應該指出有利地使用之複合物係為一種複合物 在酼後消除之後仍然稍微柔軟,例如以矽或聚胺基酸 為主之聚合複合物。 也解其他方法(例如,模板印刷或絲網印刷或分配方: 圖式簡述 -15- 569358
⑻ 本發明之進一步優點、特點和細節從在上面文字中扩述 之例示具體實施例和藉由使用圖式,而顯示,其中:田a 圖1-7顯示藉由根據本發明之一第一方法變化壓 性接觸元件之半導體晶片之產生, 、/、 圖8-H)顯示根據本發明之第二方法變化,同樣藉由壓縮 具彈性接觸元件之半導體晶片之產生,
圖11和12顯不根據本發明之第三方法變化之半導體晶片 之產生, 曰曰 顯示根據本發明在接觸元件之區域中半導體晶片之 狹大部分檢視圖,以及 二4顯示根據本發明之半導體晶片之進一步具體例。 圖式代表符號說明 1 . 前端晶圓 2、 13 、 20、 26 曰 κ 〇 日日月 3 、 14 、 21 、 97 27 接觸元件 4
5 交錯線層 載體 6 ^ 晶片排列 15、16、22、23 — 半模型 背側邊 複合物 複合物表面 晶圓 凹地 10 、 17 、 18 、 25 、 29 、 31 11 12、19 24 16- 569358 (12) 28 表面 30 半導體晶片 32 晶片背側邊
Claims (1)
- 569358 拾、申請專利範圍 一種裝U具有凸出在晶圓層級封骏之推 側邊上之接觸元件之半導體日日日片的^ /景内之—晶 片側邊提供具有形成保護層之 ’,其特徵為該 2. 3. 凡件’該突出接觸元件從該保護層突勿塗覆之接 如申所專利範圍第丨項之方法,其 片同時以複合物塗覆。 、·攻為該等複數個如申請專利範圍第2項之方法,1 :數個分開晶片或具有在其上形成‘複 4. 如申請專利範圍第3項之方法 或晶圓起始在依附之载體上, 步驟之後實施塗覆。 ,其特徵為該等分開晶片 特別地為膜,排列,在該 5. 如申請專利範圍第3項或第夕古土 ^ ^ ^ ^ ^ , 項方法,其特徵為除了負 複合物塗覆。 4卜u邊邊緣也以該6·如申請專利範圍第3或4項之方法,其特徵為在分開晶片 ,情況下,該晶片側邊,至少在一些區域,主要在邊緣 區域中,也額外地以複合物塗覆。 7·如申請專利範圍第3或4項之方*,其特徵為該等分開晶 片或附在晶圓中之晶片在模型中排列,該模型的一半模 尘轭加壓力於該等晶片至另一半模型,稍微地壓縮具彈 性之接觸元件,在該步驟之後複合物被引進至該模型中 且被消除。 5693588. 9. ^申請專利範圍第3或4項之方法,其特徵為該等分開曰 片或附在晶圓中之晶片在模型中排列,該模型的—半: 型具有凹地’其為突出接觸元件以晶片侧邊稍微鱼土: 模型間隔開之方式與其前面區域接合之地方,在該= 之後,在模型密合之後,複合物被引進且被消除。驟 =請專利範圍第5項之方法,其特徵為為了也讓侧邊土覆之目的,在載體上,特別地為膜,該耸 分開晶片被互相間隔排列。 10, 曰、i /、作用僅在晶片背面侧邊之點上,主要在 其中心,使得剩餘之空晶片背面侧邊可以複合物塗覆。 L如申请專利範圍第7項之方法,其特徵為在從模型消除 且移除之後’假如需要的話,在載體,特別地為膜,移 除之後’由分割該消除複合物或晶圓而分開。 12·如申请專利冑圍第w之方法,其特徵為在印刷方法中複口物施加至日日片别側邊’假如適當的話,在側邊邊緣 或至少部分在晶片背側邊。 13·如中請專利範圍第1項之方法,其特徵為在分配方法中 複合物施加至晶片前侧邊,假如適當的話,在側邊邊緣 或至少部分在晶片背側邊。 14.如申:專利範圍第1項之方法,其特徵為在被複合物塗 覆之刖或之後’ 4晶片背側邊,假如適當的話,其仍暴 露之地方,以進一步之複合物塗覆。 5·如申明專利範圍第14項之方法,其特徵為晶片背側邊之 -2- 569358塗覆可在印刷方法 型中實施。 分配方法、濺擊方法或是在注入成16· 一種根據如申請專利範圍第丨至15項中其中之—之方法 所特別地產生之具有在一晶片側邊突出之堅硬彈 性接觸元件之半導體晶片,其特徵為提供具有該等接觸 70件(3 ' 14、2卜27)之晶片侧邊以形成保護層之覆蓋複 合物(10、17、25、29)塗覆,該等突出接觸元件(3、ι4 、21、27)從該保護層突出。 17.如中請專利範圍第16項之半導體晶片,其特徵為接合具 有接觸元件(3、27)之晶片側邊的側邊邊緣也以複合物 (10、29、31)塗覆。 18·如中請專利範圍第16或17項之半導體晶片,其特徵為該 晶片背側邊(32),至少在一些區域,主要在邊緣區域中 ’也額外地以複合物(31)塗覆。 19.如申請專利範圍第16項之半導體晶片,其特徵為該晶片 背侧邊,假如適當的話,以進一步之複合物(1 8)塗覆至其仍暴露之範圍。 2〇·如申請專利範圍第16項之半導體晶片,其特徵該複合物 (10、17、2 5、2 9、3 1)以及假如適當的話,該進一步複 合物(18)係為非導電複合物,其以聚合物為主,特別地 為碎複合物或聚胺基甲酸酯。
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DE10156386A DE10156386B4 (de) | 2001-11-16 | 2001-11-16 | Verfahren zum Herstellen eines Halbleiterchips |
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TW200301943A (en) | 2003-07-16 |
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