US20080290478A1 - Lead-frame array package structure and method - Google Patents

Lead-frame array package structure and method Download PDF

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Publication number
US20080290478A1
US20080290478A1 US12/013,908 US1390808A US2008290478A1 US 20080290478 A1 US20080290478 A1 US 20080290478A1 US 1390808 A US1390808 A US 1390808A US 2008290478 A1 US2008290478 A1 US 2008290478A1
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Prior art keywords
leads
lead
frame
metal
shorter
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US12/013,908
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Yu-Ren Chen
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Chipmos Technologies Inc
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Individual
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Assigned to CHIPMOS TECHNOLOGIES INC. reassignment CHIPMOS TECHNOLOGIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, YU-REN
Publication of US20080290478A1 publication Critical patent/US20080290478A1/en
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    • H01L2924/191—Disposition
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    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present invention is a package structure, more particularly; it is a lead-frame array package structure.
  • the Computer/Communication/Consumer (3C) electronics are so popular in public.
  • the size of the 3C products are more attractive if the size of the electronics is smaller. Therefore, it is necessary to decrease the size of the semiconductor inside the 3C products.
  • the wafer level chip scale package (WL-CSP) is well known to use for the semiconductor in the second half package process in order to reduce the size of the semiconductor.
  • WL-CSP wafer level chip scale package
  • BGA ball grid array
  • the good-die test is able to execute after all the package processes were done and the wafer was cut, when the WL-CSP package process is used. If there is a fault happened in the package process, it would waste a lot of package cost.
  • the redistribution layer package process is a high cost and time consuming technique, and it is not good for economic remedies, especially for single-chip package.
  • the main object of the present invention is to provide a lead-frame array package structure disposed on the lead-frame by the array method to dispose a plurality of conductive elements.
  • Another object of the present invention is to provide a lead-frame array package structure to reduce the size of the package structure and the package process cost by the array method to dispose a plurality of conductive elements.
  • the package structure includes a lead-frame, which composed of a plurality of shorter leads and a plurality of longer leads.
  • the first surface and a second surface are composed of the plurality of shorter leads and the plurality of longer leads.
  • the chip is fixedly connected to the first surface of the lead-frame.
  • the plurality of metal pads is positioned on the one side of the active layer of the chip.
  • the plurality of metal pads is electrically connected to the plurality of leads of the lead-frame via the plurality of metal leads.
  • the chip, the plurality of metal leads, the first surface and the second surface of the lead-frame is encapsulated by encapsulated material to expose the portion of the plurality of leads.
  • the plurality of conductive elements is electrically connected to exposed leads so as to an array arrangement package structure is formed on the second surface of the lead-frame.
  • a lead-frame package method is also provided in the present invention.
  • the package method includes: forming a lead-frame in accordance with a plurality of shorter leads and a plurality of longer leads, and the shorter leads and the long leads are respectively and alternatively paralleled to form a first surface and a second surface, a geographic shape is formed at the end of each of the long leads, the end with the geographic shape is disposed at the same horizontal as the end of each of the shorter lead; fixedly connecting a chip to the first surface of the lead frame by a adhesive layer and the chip includes an active layer, one side of the active layer including a plurality of metal pads disposed thereon; executing a wire bonding process to electrically connect a plurality of metal leads to the metal pads on the chip and the plurality of leads on the lead-frame; executing an encapsulated process to cover the chip, the metal leads and the first surface and the second surface of the lead-frame by an encapsulant material; exposing a portion of the metal of the second leads of the lead-frame by
  • FIG. 1 is a top view of a lead-frame in accordance with an embodiment of the present invention.
  • FIG. 2 is a top view of a lead-frame with a plurality of leads with different length respectively and alternatively paralleled to each other.
  • FIG. 3A is a sectional view of a lead-frame package structure with 2 ⁇ n arrangement of the conductive elements.
  • FIG. 3B is a top view of the conductive elements with a plurality of longer leads and shorter leads disposed thereon.
  • FIG. 4A is a sectional view of a lead-frame package structure with 4 ⁇ n arrangement of the conductive elements.
  • FIG. 4B is a top view of the conductive elements with a plurality of longer leads and shorter leads disposed thereon.
  • FIG. 5A is a sectional view of a lead-frame package structure with 4 ⁇ n arrangement of the conductive elements by dual wire bonding process.
  • FIG. 5B is a top view of the conductive elements with a plurality of longer leads and shorter leads disposed thereon.
  • FIG. 6 is a flow chart of a lead-frame package method according to the present invention.
  • FIG. 7 is a view showing the wafer level chip scale package in prior art.
  • the lead-frame is made by forming a plurality of leads on a copper foil according to the stamp technique.
  • the pattern of the leads is designed by request. Because the stamp technique is a prior art, it is not a priority in the present invention. Therefore, the steps to form a plurality of lead-frames by the stamp technique are omitted herein.
  • the lead-frame 10 is formed in accordance with a plurality of first leads 101 and a plurality of second leads 102 .
  • the first leads 101 and the second leads are used to form a first surface and a second surface (not shown).
  • Each of the first leads 101 and each of the second leads 102 are respectively and alternatively paralleled to each other and there is an interval formed between each of the first leads 101 and each of the second leads 102 .
  • the end 104 of each of the second leads 102 forms a geographic shape, such as L shape or curved shape.
  • the ends 104 with geographic shape and the ends 103 of the first leads 101 are disposed at the same horizontal 11 .
  • FIG. 2 is a top view of another lead-frame structure in the present invention.
  • the lead-frame 20 is formed in accordance with a plurality of first leads 201 , a plurality of second leads 202 , a plurality of third leads 203 and a plurality of forth leads 204 .
  • the first leads 201 , the second leads 202 , the third leads 203 and the forth leads 204 are formed a first surface and a second surface.
  • Each of the first leads 201 , each of the second leads 202 , each of third leads 203 and each of forth leads 204 are respectively and alternatively paralleled to each other and formed with different lengths.
  • the rest of the longer leads includes the ends with geographic shape, such as L shape or curved shape.
  • the ends of the first leads 201 , the second leads 202 , the third leads 203 and the forth leads 203 are disposed at the same horizontal 11 .
  • FIGS. 3A-3B and FIGS. 4A-4B are sectional views and bottom views of the lead-frame package structure in accordance with the FIG. 1 and FIG. 2 .
  • FIG. 3A it is a sectional view of the package structure in the present invention.
  • a lead-frame 10 formed in accordance with a plurality of shorter leads 101 and a plurality of longer leads 102 .
  • the shorter leads 101 and the longer leads 102 are used to form a first surface 1011 and a second surface 1012 .
  • a chip 40 provided herein.
  • the chip 40 includes an active layer 402 and one side of the active layer 402 includes a plurality of metal pads 50 .
  • the reverse surface 401 of the chip 40 is connected to the shorter leads 101 and the longer leads 102 by an adhesive layer 30 on the first surface 1011 .
  • the material of the adhesive layer is polymer, such as a B-stage.
  • the adhesive layer 30 is able to stick on the reverse surface 401 of the chip 40 or the first surface of the lead-frame 10 , and it is not limited in the present invention.
  • a wire bonding process is used to electrically connect a plurality of metal pads 50 on the leads 101 , the leads 102 and the active layer of the chip 40 by a plurality of metal leads 60 .
  • an encapsulated process is used to cover the active layer 402 of the chip 40 , the metal leads 60 , the first surface 1011 and the second surface 1012 of the lead-frame 10 by an encapsulant material.
  • a removing process is used to remove the encapsulant material on the end 103 of the first lead 101 and the end 104 of the second lead 102 of the second surface 1012 of the lead-frame 10 and expose the metal on the end 103 and 104 (not shown).
  • a connecting process for the conductive element 80 is used to sequentially form a metal bump on each of the ends 103 and the ends 104 .
  • the conductive element 80 is also able to be a metal ball.
  • a dual rows package structure is formed, such as shown in FIG. 3B .
  • the conductive elements 80 are formed on the second surface 1012 of the lead-frame 10 by a 2 ⁇ n arrangement method.
  • the n can be any numbers depended on the requirement.
  • the conductive element 80 can be metal bump or solder ball.
  • the conductive element 80 is disposed on each of the leads (the shorter leads 101 and the longer leads 102 ) and the lengths of the conductive elements 80 are equal to each other.
  • FIG. 4A and FIG. 4B are sectional view and bottom view in accordance with another embodiment of the package structure in the present invention.
  • the lead-frame 20 in the present embodiment includes a plurality of first leads 201 , a plurality of second leads 202 , a plurality of third leads 203 and a plurality of forth leads 204 and those leads ( 201 , 202 , 203 and 204 ) are use to form a first surface and a second surface.
  • each of the first leads 201 , each of the second leads 202 , each of the third leads 203 and each of the forth leads 204 are respectively and alternatively paralleled to each other and formed with different length. Except for the shortest lead (such as the third lead 203 ), the ends of the longer leads are formed a geographic shape, such as L shape or curved shape. The ends of the first leads 201 , the second leads 202 , the third leads 203 and the forth leads 203 are disposed at the same horizontal 11 . Therefore, the plurality of conductive elements 80 are formed an array in accordance with the sticking process of the chip 40 , the wire bonding process, the molding process, the removing process and the reflow soldering process, as shown in FIG. 4A and FIG. 4B . It should be noted that the 4 ⁇ n array shown in figures are just one embodiment in the present invention. It should not be the limitation of the size of the array. The object with the lead-frame array package structure disclosed herein should be included in the embodiment of the present invention.
  • FIG. 5A and FIG. 5B are sectional view and bottom view in accordance with another embodiment of the present invention.
  • a stamp process is used to form a plurality of lead-frames 20 on the copper foil.
  • the lead-frame 20 is formed by a plurality of first leads 901 and a plurality of second leads 902 in the present embodiment.
  • the first leads 901 and the second leads 902 are respectively and alternatively paralleled to each other.
  • the first leads 901 include a plurality of shorter leads 9011 and a plurality of longer leads 9012 .
  • the second leads 902 include a plurality of short leads 9021 and a plurality of long leads 9022 .
  • the longer leads 9011 and 9021 in the first leads 901 and the second leads 902 and the shorter leads 9012 and 9022 in the first leads 901 and the second leads 902 are respectively and alternatively paralleled to each other.
  • the longer leads 9011 , 9021 include the ends with geographic shape, such as L shape or curved shape. The ends with geographic shape are disposed at the same horizontal 11 , as shown in FIG. 5B .
  • a portion of the reverse surface 401 of the chip 40 is stuck on the first leads 901 and the second leads 902 of the lead-frame 20 by an adhesive layer 30 .
  • the two sides of the active surface 402 of the chip 40 in the present embodiment dispose a plurality of metal pads.
  • the metal lead bonding technique is used to electrically connect the metal pads 50 on the two sides of the active surface 402 of the chip 40 and the first leads 901 and the second leads 902 of the lead-frame 20 by a plurality of metal leads 60 .
  • the encapsulant material 70 is used to cover the chips 40 , the metal leads 60 and the first leads 901 and the second leads 902 of the lead-frame 20 .
  • a removing process is used to remove the encapsulant material on the first leads 901 and the second leads 902 and expose the metal on the first leads 901 and the second leads 902 (not shown).
  • a connecting process for the conductive element 80 such as reflow soldering, is used to sequentially form a conductive element 80 on the ends of the first leads 901 and the second leads 902 .
  • the conductive element 80 is also able to be a metal ball.
  • an array package structure made by a plurality of conductive element 80 is formed, such as shown in FIG. 5B .
  • the encapsulated material 70 in the embodiment of FIGS. 3A-3B , FIGS. 4A-4B and FIGS. 5A-5B is to cover the chip 40 , the metal leads 60 , the first surface and the second surface of the lead-frame and saw the chip 40 in accordance with the sawing line 90 by a sawing process to isolate the chips.
  • the sawing process in the present invention is used to saw a portion of un-bumping leads to shorten the size of the package structure, the redistribution-layer (RDL) problem occurred in the prior art is not necessary to worry about.
  • the step to calculate the interval between the chips is not needed when sawing the package structure.
  • the sawing apparatus would not affect the package structure by the sawing process. It is not necessary to think about changing the sawing apparatus in the present invention. Therefore, according to the lead-frame array package disclosed in the present invention, it would reduce the cost and shorten the size of the package structure.
  • a lead-frame array package structure includes a lead-frame, which composed of a plurality of shorter leads and a plurality of longer leads.
  • the first surface and a second surface are composed of the plurality of shorter leads and the plurality of longer leads.
  • the chip is fixedly connected to the first surface of the lead-frame.
  • the plurality of metal pads is positioned on the one side of the active layer of the chip.
  • the plurality of metal pads is electrically connected to the plurality of leads of the lead-frame via the plurality of metal wires.
  • the chip, the plurality of metal wires, the first surface and the second surface of the lead-frame is encapsulated by encapsulant material to expose the portion of the metal of the plurality of leads.
  • the plurality of conductive elements is electrically connected to exposed leads so as to an array arrangement is formed on the second surface of the lead-frame.
  • a lead-frame array package method is also disclosed in the present invention.
  • the package method includes: forming a lead-frame in accordance with a plurality of shorter leads and a plurality of longer leads, and the shorter leads and the longer leads are respectively and alternatively paralleled to form a first surface and a second surface, a geographic shape is formed at the end of each of the longer leads, the end with the geographic shape is disposed at the same horizontal as the end of each of the shorter lead; fixedly connecting a chip to the first surface of the lead-frame by a adhesive layer and the chip includes an active layer, one side of the active layer including a plurality of metal pads disposed thereon; executing a wire bonding process to electrically connect a plurality of metal leads to the metal pads on the chip and the plurality of leads on the lead-frame; executing an encapsulated process to cover the chip, the metal leads and the first surface and the second surface of the lead-frame by an encapsulated material; exposing a portion of the

Abstract

The present invention provides a lead-frame array package structure. The package structure includes a lead-frame, which composed of a plurality of shorter leads and a plurality of longer leads. The first surface and a second surface are composed of the shorter leads and the longer leads. The chip is fixedly connected to the first surface of the lead-frame. The metal pads are positioned on the one side of the active layer of the chip. The metal pads are electrically connected to the leads of the lead-frame via the metal leads. The chip, the metal leads, the first surface and the second surface of the lead-frame is encapsulated by encapsulated material to expose the portion of the metal of the leads. The conductive elements are electrically connected to exposed leads so as to an array arrangement is formed on the second surface of the lead-frame.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention is a package structure, more particularly; it is a lead-frame array package structure.
  • 2. Description of the Prior Art
  • In recent years, the Computer/Communication/Consumer (3C) electronics are so popular in public. The size of the 3C products are more attractive if the size of the electronics is smaller. Therefore, it is necessary to decrease the size of the semiconductor inside the 3C products. For this reason, the wafer level chip scale package (WL-CSP) is well known to use for the semiconductor in the second half package process in order to reduce the size of the semiconductor. For example, there is a re-distribution layer used to form ball grid array (BGA) package structure in U.S. Pat. No. 7,129,581, as shown in FIG. 7. Obviously, the good-die test is able to execute after all the package processes were done and the wafer was cut, when the WL-CSP package process is used. If there is a fault happened in the package process, it would waste a lot of package cost. In the meantime, the redistribution layer package process is a high cost and time consuming technique, and it is not good for economic benefices, especially for single-chip package.
    • SUMMARY OF THE INVENTION
  • According to drawbacks and problems described above for the single-chip package method, the main object of the present invention is to provide a lead-frame array package structure disposed on the lead-frame by the array method to dispose a plurality of conductive elements.
  • Another object of the present invention is to provide a lead-frame array package structure to reduce the size of the package structure and the package process cost by the array method to dispose a plurality of conductive elements.
  • According to the objects described above, a lead-frame array package structure is provided in the present invention. The package structure includes a lead-frame, which composed of a plurality of shorter leads and a plurality of longer leads. The first surface and a second surface are composed of the plurality of shorter leads and the plurality of longer leads. The chip is fixedly connected to the first surface of the lead-frame. The plurality of metal pads is positioned on the one side of the active layer of the chip. The plurality of metal pads is electrically connected to the plurality of leads of the lead-frame via the plurality of metal leads. The chip, the plurality of metal leads, the first surface and the second surface of the lead-frame is encapsulated by encapsulated material to expose the portion of the plurality of leads. The plurality of conductive elements is electrically connected to exposed leads so as to an array arrangement package structure is formed on the second surface of the lead-frame.
  • A lead-frame package method is also provided in the present invention. The package method includes: forming a lead-frame in accordance with a plurality of shorter leads and a plurality of longer leads, and the shorter leads and the long leads are respectively and alternatively paralleled to form a first surface and a second surface, a geographic shape is formed at the end of each of the long leads, the end with the geographic shape is disposed at the same horizontal as the end of each of the shorter lead; fixedly connecting a chip to the first surface of the lead frame by a adhesive layer and the chip includes an active layer, one side of the active layer including a plurality of metal pads disposed thereon; executing a wire bonding process to electrically connect a plurality of metal leads to the metal pads on the chip and the plurality of leads on the lead-frame; executing an encapsulated process to cover the chip, the metal leads and the first surface and the second surface of the lead-frame by an encapsulant material; exposing a portion of the metal of the second leads of the lead-frame by removing the encapsulant material on each end of the leads in accordance with a removing process; and forming a plurality of conductive elements on the exposed metal leads and the conductive elements are used to electrically connected to the exposed metal leads.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
  • FIG. 1 is a top view of a lead-frame in accordance with an embodiment of the present invention.
  • FIG. 2 is a top view of a lead-frame with a plurality of leads with different length respectively and alternatively paralleled to each other.
  • FIG. 3A is a sectional view of a lead-frame package structure with 2×n arrangement of the conductive elements.
  • FIG. 3B is a top view of the conductive elements with a plurality of longer leads and shorter leads disposed thereon.
  • FIG. 4A is a sectional view of a lead-frame package structure with 4×n arrangement of the conductive elements.
  • FIG. 4B is a top view of the conductive elements with a plurality of longer leads and shorter leads disposed thereon.
  • FIG. 5A is a sectional view of a lead-frame package structure with 4×n arrangement of the conductive elements by dual wire bonding process.
  • FIG. 5B is a top view of the conductive elements with a plurality of longer leads and shorter leads disposed thereon.
  • FIG. 6 is a flow chart of a lead-frame package method according to the present invention.
  • FIG. 7 is a view showing the wafer level chip scale package in prior art.
    •  DESCRIPTION OF THE PREFERRED EMBODIMENT
  • The detailed description of the present invention will be discussed in the following embodiments, which are not intended to limit the scope of the present invention, but can be adapted for other applications. While drawings are illustrated in details, it is appreciated that the quantity of the disclosed components may be greater or less than that disclosed, except expressly restricting the amount of the components.
  • First of all, according to the embodiments disclosed in the present invention, the lead-frame is made by forming a plurality of leads on a copper foil according to the stamp technique. The pattern of the leads is designed by request. Because the stamp technique is a prior art, it is not a priority in the present invention. Therefore, the steps to form a plurality of lead-frames by the stamp technique are omitted herein.
  • Please referring to FIG. 1, it is a top view of the lead-frame structure in the present invention. As shown in FIG. 1, the lead-frame 10 is formed in accordance with a plurality of first leads 101 and a plurality of second leads 102. The first leads 101 and the second leads are used to form a first surface and a second surface (not shown). Each of the first leads 101 and each of the second leads 102 are respectively and alternatively paralleled to each other and there is an interval formed between each of the first leads 101 and each of the second leads 102. The end 104 of each of the second leads 102 forms a geographic shape, such as L shape or curved shape. The ends 104 with geographic shape and the ends 103 of the first leads 101 are disposed at the same horizontal 11.
  • FIG. 2 is a top view of another lead-frame structure in the present invention. The lead-frame 20 is formed in accordance with a plurality of first leads 201, a plurality of second leads 202, a plurality of third leads 203 and a plurality of forth leads 204. The first leads 201, the second leads 202, the third leads 203 and the forth leads 204 are formed a first surface and a second surface. Each of the first leads 201, each of the second leads 202, each of third leads 203 and each of forth leads 204 are respectively and alternatively paralleled to each other and formed with different lengths. Except for the shorter leads (such as the third leads 203), the rest of the longer leads (such as the first leads 201, the second leads 202 and the forth leads 204) includes the ends with geographic shape, such as L shape or curved shape. The ends of the first leads 201, the second leads 202, the third leads 203 and the forth leads 203 are disposed at the same horizontal 11.
  • FIGS. 3A-3B and FIGS. 4A-4B are sectional views and bottom views of the lead-frame package structure in accordance with the FIG. 1 and FIG. 2.
  • Please referring to FIG. 3A, it is a sectional view of the package structure in the present invention. As shown in FIG. 3A, there is a lead-frame 10 formed in accordance with a plurality of shorter leads 101 and a plurality of longer leads 102. The shorter leads 101 and the longer leads 102 are used to form a first surface 1011 and a second surface 1012. It should be noted that there are a plurality of lead-frame 10 formed on one sheet of copper foil in practical. But there is only one lead-frame shown in the present drawing, the rest of the lead-frame are packaged with same process procedure. Still refer to FIG. 3A, there is a chip 40 provided herein. The chip 40 includes an active layer 402 and one side of the active layer 402 includes a plurality of metal pads 50. The reverse surface 401 of the chip 40 is connected to the shorter leads 101 and the longer leads 102 by an adhesive layer 30 on the first surface 1011. It should be noted that the material of the adhesive layer is polymer, such as a B-stage. Besides, the adhesive layer 30 is able to stick on the reverse surface 401 of the chip 40 or the first surface of the lead-frame 10, and it is not limited in the present invention.
  • After the process described above, a wire bonding process is used to electrically connect a plurality of metal pads 50 on the leads 101, the leads 102 and the active layer of the chip 40 by a plurality of metal leads 60. After the wire bonding process, an encapsulated process is used to cover the active layer 402 of the chip 40, the metal leads 60, the first surface 1011 and the second surface 1012 of the lead-frame 10 by an encapsulant material. After the encapsulated process, a removing process is used to remove the encapsulant material on the end 103 of the first lead 101 and the end 104 of the second lead 102 of the second surface 1012 of the lead-frame 10 and expose the metal on the end 103 and 104 (not shown). After the removing process, a connecting process for the conductive element 80, such as a reflow soldering, is used to sequentially form a metal bump on each of the ends 103 and the ends 104. The conductive element 80 is also able to be a metal ball. Obviously, in the present embodiment, because of the structure of the lead-frame 10, a dual rows package structure is formed, such as shown in FIG. 3B.
  • Therefore, as the description above, the conductive elements 80 are formed on the second surface 1012 of the lead-frame 10 by a 2×n arrangement method. The n can be any numbers depended on the requirement. Besides, in the present embodiment, the conductive element 80 can be metal bump or solder ball. The conductive element 80 is disposed on each of the leads (the shorter leads 101 and the longer leads 102) and the lengths of the conductive elements 80 are equal to each other.
  • Please refer to FIG. 4A and FIG. 4B. Those are sectional view and bottom view in accordance with another embodiment of the package structure in the present invention. As shown in FIG. 4A and FIG. 4B, the different between FIGS. 3A-3B and FIGS. 4A-4B is the lead frame structure. The lead-frame 20 in the present embodiment includes a plurality of first leads 201, a plurality of second leads 202, a plurality of third leads 203 and a plurality of forth leads 204 and those leads (201, 202, 203 and 204) are use to form a first surface and a second surface. Each of the first leads 201, each of the second leads 202, each of the third leads 203 and each of the forth leads 204 are respectively and alternatively paralleled to each other and formed with different length. Except for the shortest lead (such as the third lead 203), the ends of the longer leads are formed a geographic shape, such as L shape or curved shape. The ends of the first leads 201, the second leads 202, the third leads 203 and the forth leads 203 are disposed at the same horizontal 11. Therefore, the plurality of conductive elements 80 are formed an array in accordance with the sticking process of the chip 40, the wire bonding process, the molding process, the removing process and the reflow soldering process, as shown in FIG. 4A and FIG. 4B. It should be noted that the 4×n array shown in figures are just one embodiment in the present invention. It should not be the limitation of the size of the array. The object with the lead-frame array package structure disclosed herein should be included in the embodiment of the present invention.
  • Please refer to FIG. 5A and FIG. 5B. Those are sectional view and bottom view in accordance with another embodiment of the present invention. In the present embodiment, a stamp process is used to form a plurality of lead-frames 20 on the copper foil. The lead-frame 20 is formed by a plurality of first leads 901 and a plurality of second leads 902 in the present embodiment. The first leads 901 and the second leads 902 are respectively and alternatively paralleled to each other. The first leads 901 include a plurality of shorter leads 9011 and a plurality of longer leads 9012. The second leads 902 include a plurality of short leads 9021 and a plurality of long leads 9022. In addition, the longer leads 9011 and 9021 in the first leads 901 and the second leads 902 and the shorter leads 9012 and 9022 in the first leads 901 and the second leads 902 are respectively and alternatively paralleled to each other. There is a fixed distance between the longer leads 9011, 9021 and the shorter leads 9012, 9022. The longer leads 9011, 9021 include the ends with geographic shape, such as L shape or curved shape. The ends with geographic shape are disposed at the same horizontal 11, as shown in FIG. 5B.
  • Now refer to FIG. 5, a portion of the reverse surface 401 of the chip 40 is stuck on the first leads 901 and the second leads 902 of the lead-frame 20 by an adhesive layer 30. The two sides of the active surface 402 of the chip 40 in the present embodiment dispose a plurality of metal pads. Then, the metal lead bonding technique is used to electrically connect the metal pads 50 on the two sides of the active surface 402 of the chip 40 and the first leads 901 and the second leads 902 of the lead-frame 20 by a plurality of metal leads 60. Subsequently, the encapsulant material 70 is used to cover the chips 40, the metal leads 60 and the first leads 901 and the second leads 902 of the lead-frame 20.
  • A removing process is used to remove the encapsulant material on the first leads 901 and the second leads 902 and expose the metal on the first leads 901 and the second leads 902 (not shown). After the removing process, a connecting process for the conductive element 80, such as reflow soldering, is used to sequentially form a conductive element 80 on the ends of the first leads 901 and the second leads 902. The conductive element 80 is also able to be a metal ball. Obviously, in the present embodiment, because of the structure of the lead-frame 20, an array package structure made by a plurality of conductive element 80 is formed, such as shown in FIG. 5B.
  • Besides, the encapsulated material 70 in the embodiment of FIGS. 3A-3B, FIGS. 4A-4B and FIGS. 5A-5B is to cover the chip 40, the metal leads 60, the first surface and the second surface of the lead-frame and saw the chip 40 in accordance with the sawing line 90 by a sawing process to isolate the chips. Because the sawing process in the present invention is used to saw a portion of un-bumping leads to shorten the size of the package structure, the redistribution-layer (RDL) problem occurred in the prior art is not necessary to worry about. The step to calculate the interval between the chips is not needed when sawing the package structure. The sawing apparatus would not affect the package structure by the sawing process. It is not necessary to think about changing the sawing apparatus in the present invention. Therefore, according to the lead-frame array package disclosed in the present invention, it would reduce the cost and shorten the size of the package structure.
  • According to the description above, a lead-frame array package structure is disclosed in the present invention. The package structure includes a lead-frame, which composed of a plurality of shorter leads and a plurality of longer leads. The first surface and a second surface are composed of the plurality of shorter leads and the plurality of longer leads. The chip is fixedly connected to the first surface of the lead-frame. The plurality of metal pads is positioned on the one side of the active layer of the chip. The plurality of metal pads is electrically connected to the plurality of leads of the lead-frame via the plurality of metal wires. The chip, the plurality of metal wires, the first surface and the second surface of the lead-frame is encapsulated by encapsulant material to expose the portion of the metal of the plurality of leads. The plurality of conductive elements is electrically connected to exposed leads so as to an array arrangement is formed on the second surface of the lead-frame.
  • Besides, please refer to FIG. 6, a lead-frame array package method is also disclosed in the present invention. The package method includes: forming a lead-frame in accordance with a plurality of shorter leads and a plurality of longer leads, and the shorter leads and the longer leads are respectively and alternatively paralleled to form a first surface and a second surface, a geographic shape is formed at the end of each of the longer leads, the end with the geographic shape is disposed at the same horizontal as the end of each of the shorter lead; fixedly connecting a chip to the first surface of the lead-frame by a adhesive layer and the chip includes an active layer, one side of the active layer including a plurality of metal pads disposed thereon; executing a wire bonding process to electrically connect a plurality of metal leads to the metal pads on the chip and the plurality of leads on the lead-frame; executing an encapsulated process to cover the chip, the metal leads and the first surface and the second surface of the lead-frame by an encapsulated material; exposing a portion of the metal of the second leads of the lead-frame by removing the encapsulant material on each end of the leads in accordance with a removing process; and forming a plurality of conductive elements on the exposed metal leads and the conductive elements are used to electrically connected to the exposed metal leads.
  • Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.

Claims (18)

1. A semiconductor package structure comprising:
a lead-frame formed by a plurality of shorter leads and a plurality of longer leads, and the shorter leads and the longer leads are respectively and alternatively paralleled to form a first surface and a second surface, a geographic shape is formed at the end of each of the longer leads, the ends with the geographic shape are disposed at the same horizontal as the end of each of the shorter leads;
a chip fixedly connected to the first surface of the lead-frame by an adhesive layer and including an active layer, one side of the active layer having a plurality of metal pads disposed thereon;
a plurality metal wires used to electrically connect the metal pads on the chip and the leads of the lead-frames;
an encapsulant material used to cover the chip, the metal leads and the first surface and the second surface of the lead-frame, and expose a portion of the metal of the leads; and
a plurality of conductive elements electrically connected to the exposed metal of the leads to form a dual row deploy on the second surface of the lead-frame.
2. The package structure of claim 1, wherein the material of the adhesive layer is B-stage.
3. The package structure of claim 1, wherein the conductive elements are conductive bump.
4. The package structure of claim 1, wherein the conductive elements are solder ball.
5. The package structure of claim 1, wherein the geographic shape is L-shape.
6. The package structure of claim 1, wherein the geographic shape is curved shape.
7. A semiconductor package structure comprising:
a lead-frame formed in accordance with a plurality of shorter leads and a plurality of longer leads, and the shorter leads and the longer leads are respectively and alternatively paralleled to form a first surface and a second surface, a geographic shape is formed at the end of each of the plurality of longer leads, the ends with the geographic shape are disposed at the same horizontal as the end of each of the shorter leads;
a chip fixedly connected to the first surface of the lead-frame by a adhesive layer and including an active layer, one side of the active layer having a plurality of metal pads disposed thereon;
a plurality metal leads used to electrically connect the metal pads on the chip and the leads on the lead-frame;
an encapsulant material used to cover the chip, the metal leads and the first surface and the second surface of the lead frame lead-frame, and expose a portion of the metal of the leads; and
a plurality of conductive elements electrically connected to the exposed metal of the leads and formed an array deploy on the second surface of the leads.
8. The package structure of claim 7, wherein the conductive elements are solder ball.
9. The package structure of claim 7, wherein the geographic shape is L-shape.
10. The package structure of claim 7, wherein the geographic shape is curved shape.
11. A semiconductor package structure comprising:
a lead-frame formed in accordance with a plurality of first leads and a plurality of second leads, and the first leads and the second leads are used to form a first surface and a second surface, the first leads and the second leads have a plurality of longer leads and a plurality of shorter leads, the longer leads and the shorter leads are respectively and alternatively paralleled, a geographic shape is formed at the end of each of the longer leads, the ends with the geographic shape are disposed at the same horizontal as the end of each of the shorter leads;
a chip fixedly connected to the first surface of the lead-frame by a adhesive layer and including an active layer, two corresponding side of the active layer having a plurality of metal pads disposed thereon;
a plurality metal leads used to electrically connect the metal pads on the chip and the leads on the lead-frame;
an encapsulant material used to cover the chip, the metal leads and the first surface and the second surface of the lead-frame, and expose a portion of the metal of the leads; and
a plurality of conductive elements electrically connected to the exposed metal of the leads and formed a dual row deploy on the second surface of the leads.
12. The package structure of claim 11, wherein the conductive elements are disposed on the second surface of the lead frame by the way of bi-parallel.
13. The package structure of claim 11, wherein the conductive elements are disposed on the second surface of the lead frame by the way of array.
14. A lead-frame package method comprising:
forming a lead-frame in accordance with a plurality of shorter leads and a plurality of longer leads, and the shorter leads and the longer leads are respectively and alternatively paralleled to form a first surface and a second surface, a geographic shape is formed at the end of each of the longer leads, the end with the geographic shape is disposed at the same horizontal as the end of each of the shorter leads;
fixedly connecting a chip to the first surface of the lead-frame by a adhesive layer and the chip has an active layer, one side of the active layer having a plurality of metal pads disposed thereon;
executing a wire bonding process to electrically connect a plurality of metal leads to the metal pads on the chip and the plurality of leads on the lead-frame;
executing an encapsulated process to cover the chip, the metal leads and the first surface and the second surface of the lead-frame by an encapsulant material;
exposing a portion of the metal of the second leads of the lead-frame by removing the encapsulant material on each end of the leads in accordance with a removing process; and
forming a plurality of conductive elements on the exposed metal leads and the conductive elements are used to electrically connected to the exposed metal leads.
15. The package structure of claim 14, wherein the longer leads are formed by a group of leads.
16. A lead-frame package structure formed in accordance with a plurality of shorter leads and a plurality of longer leads, and the shorter leads and the longer leads are respectively and alternatively paralleled to each other, characterized by:
a geographic shape formed at the end of each of the longer leads and the end with the geographic shape is disposed at the same horizontal as the end of each of the shorter leads.
17. A lead-frame package structure formed in accordance with a plurality of shorter leads and a plurality of leads, which is longer leads than the short leads, and the shorter leads and the longer leads are respectively and alternatively paralleled to each other, characterized by:
a geographic shape formed at the end of each of the longer leads and the end with the geographic shape is disposed at the same horizontal as the end of each of the shorter leads.
18. A lead frame package structure formed in accordance with a plurality of first leads and a plurality of second leads, the first leads includes a plurality of shorter leads and a plurality of longer leads, the second leads includes a plurality of shorter leads and a plurality of longer leads, and the first leads and the second leads are respectively and alternatively paralleled to each other, characterized by:
a geographic shape formed at the end of each of the longer leads and the end with the geographic shape is disposed at the same horizontal as the end of each of the short lead.
US12/013,908 2006-10-26 2008-01-14 Lead-frame array package structure and method Abandoned US20080290478A1 (en)

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US7816771B2 (en) 2010-10-19
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