TW479305B - A semiconductor package and a wafer level packaging method - Google Patents

Abstract

A semiconductor package and a wafer level packaging method for the same are disclosed. The semiconductor package having an upper surface, a bottom surface, and at least one lateral surface with contact pads. The package includes a chip with bonding pads on its upper surface, a plurality of inner connection lines formed on the upper surface of the chip for connection of bonding pads and contact pads, and an upper sealing layer formed on the upper surface of the chip for sealing the inner connection lines and the bonding pads. Thus, the semiconductor package has the benefits of wedging connection with PCB, tiny package size, and low manufacturing cost.

Description

479305 V. Description of the invention (1) _ " — ~-[Field of invention] The present invention relates to a semiconductor packaging structure and a wafer-level packaging method, and particularly relates to a semiconductor device with contact pads formed on side surfaces. structure. [Previous technology] The conventional semiconductor package is a wafer [disk-shaped silicon-based integrated circuit completed and cut into a plurality of dice [dice], and then the plastic and ceramic lead frame as a carrier With the advancement of technology, in order to reduce the cost and speed up the production of integrated circuit of die, some people have proposed the concept of wafer-level packaging. ^ Between the completion of the body circuit and the cutting, it will be a wafer type. A plurality of integrated circuits are encapsulated f: to achieve one-time packaging of a wafer ..., cutting; to properly packaged integrated circuits. No I) is disclosed in US Patent No. 5,892,273 "Semiconductor Wafer Package", which proposes a semiconductor device that can be formed by wafer-level encapsulation with an upper surface 62 and a lower surface fj ?, with π ± v 61 as the main body. On the upper surface 62, there is a 42th!:; Shi Xi substrate soil-proofing layer 65 and a plurality of known mats 64 exposed on the first = 65th layer. An internal connection line 71 is formed on the first-protection layer 65. Seal the internal connection lines with the first protective layer 72? 1. The same protective layer 72 has a plurality of openings 74 to expose the:-end of the internal connection line 71, and an end point 73 is formed at the opening 74. The end point 73 is a matrix row protective layer 72 and is electrically connected via the internal connection line. Connect the corresponding pads 64 to form a semiconductor device that can be packaged at the wafer level. However, the semiconductor device is

V. Description of the invention (2), i ca n’t be damaged in any way! ... The failure or the upgrade or replacement is almost bare crystal type Γ = ρ ;: the circuit board ㈣, and the semiconductor device Noritsu film 6 〇 protection Worse. Know how to use the buckle method 士士 人 # < J-shaped feet of small and small shape sealed on the printed circuit board semiconductor device is tsop) or j-shaped feet of the four; flat Thl; Sma 1 0ut; ine ㈣kage , Qfp] and other package types, = t Package, electrically connected to the cutting point, and the above structure must be carried by a lead frame and = the chip separated by cutting J Wucheng, and then placed in the mold. The semiconductor device has a large size and a high manufacturing cost. [Objective and Summary of the Invention] The purpose of the invention is to provide a semiconductor package structure. The side surface of the 4, ^ ^ half v-body packaging structure makes the half v-body packaging structure in the form of wafer rulers widely available for insertion. The adapter seated on the printed circuit board also has the functions of simple replacement and upgrade and small size: the circuit board is provided for a semiconductor packaging structure, which makes contact at the side surface at the same time when cutting Pad, the semiconductor package structure of the inch-inch package has the effect of the consistent packaging process, the manufacturing cost, and the small size of the rear-stage package. The second purpose of the invention is to provide a wafer-level package; =! Complete at least The primary material, the multiple internal serial, thousands, and nine blocks formed by it are all carried and sealed by the upper sealant layer. When grinding the crystal back, the internal circuit is not stained, and it is cut at the same time when cutting. Bumps to form contact pads on the sides to prepare a plurality of properly protected and low-molded cores

Page 6/9305 V. Description of the invention (3) Semiconductor package structure.及 ::: 导 f: 装 结构 'has-an upper surface,-and the following table is a combination of taxis, where the side surface is on the surface of the upper and lower surfaces, and 20% have several contact pads, which Contains: a chip with a top surface and a surface on the top surface forming an integrated circuit element and a plurality of soldering internal connection wires, which are located on the top surface of the chip and are electrically connected & The sealant layer is: the internal connection line of bismuth; the lower sealant layer is formed on the lower surface of the wafer; the contact pads on the side facets have the surface exposed on the sealant layer, which is located in the above [detailed description of the invention] As shown in FIGS. 3 and 4, it is a semiconductor package structure according to the first embodiment of the present invention}, which is a square plate shape, preferably a square plate shape, which has a The upper surface 2, the lower surface 3, and the left surface 4, the right surface 5, the front surface 6, and the rear surface 7 between the upper surface 2 and the lower surface 3. In this embodiment, in the semiconductor package structure A plurality of contact pads 23 are formed on the side surfaces 4, 5, 6, 7, and can be used as the half Electrically bonded surface of the conductive package structure 1 ° In this embodiment, as shown in FIGS. 3 and 4, the semiconductor package structure 1 includes a chip 10, an overseal layer 31, and a plurality of Internal connection wires 21 and a plurality of contacts 塾 2 3 formed on the side surfaces 4, 5, 6, 7; wherein the chip ο includes a silicon substrate 11 and a protective layer 16 (passivating layer), the protective layer Series 16 is made of materials such as Si〇2, phosphosilicate glass [ρ%] 5. Description of the invention (4) Siliconized silicon [Si3N4], etc., and the lower surface 13, where the protection; 16 and / or sheet 10 has an upper surface 12 and the upper surface 12 of the wafer 10 is formed with a body = on the upper surface 12 of the wafer, and a circuit element] [integrated [bonding pad] of the circuit circuit element is shown in the figure, and the bonding pad 14 connected to the solder pad is on the upper surface of the wafer 10 The middle position of 12 is described as copper or 1 Lu material and arranged close to 10 can be a microprocessor chip or a memory: not shown in Figure 5] 'outside the chip, the internal connecting line m is formed; the upper surface of this piece 10 is 12 The edge extends and connects "于 = 面 广 二 4,1; 晶 ί: Fang protective layer 16 [on the wafer 1〇 Face 12] is formed on-: sealant layer 31, which is preferably a sealing material with elasticity ^ forming the upper sealing layer 31, and a compound of fat is used as a t-contact. 23 has an exposed layer. : Connecting wire side surfaces 4, 5, 6, 7, preferably, connected: located above the two are vertical for side-insertion combination; the lower sealant layer 32 and the dUt lower surface 13 'can be connected to the upper sealant layer 31 It is the same or different. The sealant layer 32 and the upper sealant layer 31 are sealed semiconductor semiconductors [.utllne] approximately equal to or slightly smaller than the appearance of the structure 1 (not less than 0.8 times the seal structure), because

The Sc I I t body package structure 1 has a chip-size package structure [ChiP cale Package, CSP] and a function for inserting and integrating with a printed circuit board ', which is easy to replace and upgrade. As shown in Figure U, the semiconductor package structure! It can be inserted into a socket 40 (socket) on the printed circuit board 50, and the socket 40 has 479305 inside it. V. Description of the invention (5) Several elastic yellow pieces 41 to form the semiconductor package structure 丨The contact pad 23 is conductively connected to the printed circuit board 50, and has the functions of easy replacement and equipment upgrade. Unlike the conventional surface mounting method, the conventional semiconductor package structure is soldered to the printed circuit by solder balls. The board must not be easily removed. The conventional semiconductor package structure must be removed destructively if it is faulty. It does not have the effect of being easily removed and replaced for equipment upgrade. The above-mentioned semiconductor package structure can be prepared by wafer level packaging process, and the direct package steps are as follows: 〃 First, as shown in Figures 5 and 6, a wafer is provided, where the wafer The system integrally includes a plurality of wafers, each of which has an upper surface 12 and a lower surface 13, and the wafer is based on a silicon substrate [sUicon, substrate] as a base material, and Crystal silicon rods or polycrystalline silicon wafers are sliced, integrated circuit layout is performed on the upper surface 12 of the plurality of wafers 10, and a plurality of bonding pads 14 (bonding pads) and a protective layer 16 are defined. } 〇 Upper surface 丨 2 etching method to open a part of the surface of a plurality of pads 丨 4 with ^ electric = power and signal external termination points, preferably in the welding body circuit except the protective layer 16 of the cutting 〔[ Such as;, for-layer of gadolinium, phosphorite glass [PSG] or nitride stone layer and the solder pad 14 is an aluminum pad or a copper pad. Next, as shown in Figs. 7 and 8, a plurality of internal connection lines and 479305 are formed.

The bumps 22 are on the upper surface 12 of the wafer 10, and each internal connection line. It is electrically connected to the corresponding bonding pads 14 and extends in the direction of the scribe line 15 (the peripheral edge of the wafer 10). The formation of the internal connection lines 21 is performed by physical vapor deposition [Physical Vapor Deposition (PVD)], A chemical vapor deposition (CVD) or plasma-assisted chemical vapor deposition (PECVD) process is used to deposit aluminum A1, copper Cu, tungsten W, or an alloy thereof, for example, a physical vapor deposition method such as sputtering. A conductive bump 22 is formed at the scribe line 15 on the upper surface 12 to electrically connect the corresponding internal connection line 21, and the bulge 22 is a convex block that crosses the boundary between the wafer and the scribe line, such as Attach a more oxidation resistant metal or conductive adhesive by printing, thermal evaporating or piating, such as gold AU, silver Ag, nickel Ni, molybdenum, indium, tin, or tin Alloy, even conductive silver glue or polymer conductive glue and so on. After the mouth ', as shown in FIG. 9, an upper sealant layer 3 is formed on the upper surface 12 of all wafers 10, such as spin coating or print coating to form an insulating gel, and then Baking and curing, the top sealant layer 31 is preferably a thermosetting composite with insulation and elasticity containing epoxy resin, such as polyimide [p〇lyimi (; ie, PI], benzocyclobutene [Benezo Cyclobutene , BCB] etc. or other low dielectric constant materials 'are used to seal the plurality of internal connection lines 21, preferably, the upper sealant layer 3 1 more seals the plurality of bumps 2 2. Then,' as the first one. As shown in the figure, the photolithography technology is used to remove the part of the wafer 10 [the silicon substrate 1 i] in the scribe line 15 to form a concave groove. If necessary, firstly

479305 V. Description of the invention (7) The wafer is flipped and the lower surface 13 of all wafers 10 is ground to accurately control the thickness of the wafer 10. At this time, the bumps 2 2 originally carried by the wafer 1 1 have been sealed. The layer 31 is fixed. Since the upper sealant layer 31 is used to seal the bonding pad 14 and the internal connection line 2 1 ′, there will be no pollution problem during the grinding process. After that, as shown in FIG. 11, a lower sealant layer 32 is formed on the lower surface 13 of all the wafers 10. The method and material of the lower sealant layer 32 may be the same as the above, and it is preferable to use the same tool. An elastic encapsulation material is spin-coated on the entire lower surface 13 'last' to cut and cut along the cutting path 15 to be solid. The bumps on the cutting path 15 are cut to form bare sides, V · '>:.;; greater than or equal to μ = package, structure 1, obviously, the size of the semiconductor package structure 1 is slightly different: chip size package [ChiP Scale PackaM] type ^ corpse ^ Manufactured using wafer-level packaging method and not Requires a sealing mold, which can be used for a variety of purposes, low manufacturing costs, small package size, and combined with a circuit board buckle to facilitate replacement. "Choose = the scope of protection of the present invention shall be subject to the attached applicant. Anyone who is familiar with this technology" Any changes and modifications made within the scope of the present invention within the scope of the present invention are within the scope of the present invention.

479305 Schematic description [Schematic diagram 1: Picture 2: Picture 3 Picture 4 Picture 5 Picture 6: Picture 7: Picture 8: Picture 9: Picture 10: Picture 11: FIG. 12: [Figure No. 1 semi-lighting] US Pat. No. 5, 892, 2 73 bottom view; US Pat. No. 5, 8 92, 2 73 cross-sectional view, semiconductor package structure of the present invention semiconductor package of the present invention The structure of the semiconductor package junction according to the present invention "provide a wafer" manufacturing steps according to the wafer sectional view of Fig. 5; the semiconductor package junction according to the present invention "form internal connection lines and bumps" diagram; the wafer according to Fig. 7 Sectional view; manufacturing steps of "forming a sealant layer" for a semiconductor package junction according to the present invention "manufacturing a lower surface of a wafer" according to the semiconductor package junction of the present invention "manufacturing another sealant layer" according to the present invention Semiconductor package structure diagram. Ming] A perspective view of the body package structure "semiconductor wafer package", a semiconductor wafer package; a cross-sectional view structure, a top view of the wafer level package; a structure, a top structure of the wafer level package manufacturing steps, A cross-sectional view in a wafer-level package; a cross-sectional view in a step of constructing its wafer-level package; a cross-sectional view in a step of constructing its wafer-level package; and a schematic PS and... :

Page 12 479305

Brief description of the drawing 2 upper surface 3 lower surface 4 left surface 5 right surface 6 front side surface 7 back side surface 10 chip 11 silicon substrate 12 top surface 13 bottom surface 14 solder pad 15 cutting path 16 protective layer 21 internal connection line 22 bump 23 Contact pad 31 Upper sealant layer 32 Lower sealant layer 40 Adapter 41 Reed 50 Printed circuit board 60 Chip 61 Silicon substrate 62 Upper surface 63 Lower surface 64 Solder pad 65 First protective layer 71 Internal connection line 72 #- — Protective layer 73 End point 74 Open σ page 13

Claims (1)

+ — A semiconductor package structure with an upper surface and — = one side surface, wherein the side surface is on the upper surface and the lower surface:% Cheng has a plurality of contact pads, which include:, a wafer of Table 2 and an upper surface and The lower surface is on the upper circuit component and a plurality of solder pads; a plurality of internal connection lines are located on the upper surface of the wafer to the corresponding contact pads; and an electrical sealant layer is formed on the crystal line; Seal = A lower sealant layer formed on the lower surface of the wafer; and a plurality of contact pads exposed on the side surface. = Affirmation, the semiconductor package described in item 1 of the scope. The appearance of the semiconductor package is approximately equal to or slightly smaller than the semiconductor package junction, such as applying for the bare contact of the semiconductor package, applying for the semiconductor cover and backside table, applying for the dedicated wafer, and applying for the multiple access range. 1-way surface system and profit range. The first mounting structure is provided with a surface. A plurality of profit ranges. The first sealing layer and the lower interest range. The first contact pad is the half of the upper surface of the chip described in the guide. The semi-electrical bump cutting conductor package junction described in the semi-sealing adhesive layer described in the surface contact pad system is vertical. The conductor package junction and the right side surface are formed from the four-conductor package junction described above. The conductor package is formed. The surface and the surface teach the connection between the surface shape and the internal connection structure, where the structure is the structure, where the structure, where, the front side surface. Structure, where structure, where 479305 (1) A semiconductor package structure having an upper surface, a lower surface, and at least one side surface, wherein the side surface is between the upper surface and the lower surface and a plurality of contact pads are formed, which includes a wafer and has a The upper surface and the lower surface form integrated circuit components and a plurality of 'soldering pads' on the upper surface; and a plurality of internal connection lines, which are located on the upper surface of the chip, and electrically connect the soldering pads to the corresponding contact pads; Layer, formed on the upper surface of the wafer, which seals the internal connection lines; and a plurality of contact pads, which are exposed on the above side surface. 8. The semiconductor package structure described in item 7 of the scope of patent application, wherein the appearance of the wafer is approximately specialized in Or slightly less than the appearance of the semiconductor package structure. 9. The semiconductor package structure described in item 7 of the scope of the patent application, wherein the exposed surface of / contact is perpendicular to the upper surface of the wafer. K 1 0 The semiconductor package structure according to item 7, wherein the semiconductor package structure has a left side surface, a right side surface, a front side surface, and a rear side surface. The contact pads are formed on the four sides of the above surface. 11. The semiconductor package structure as described in item 7 of the scope of patent application, wherein the semiconductor package structure further includes a lower sealant layer formed on the lower surface of the wafer. 1 2. If applied The semiconductor package structure described in item i 丨 of the patent scope, wherein the chip is sealed by an upper sealant layer and a lower sealant layer. 479305 VI. Scope of patent application 13, such as the application of the lower sealant layer 14 in the application for the patent, such as a plurality of 15 in the application for a patent, a kind of wafer-level knowledge and supply * wafer wafers and a plurality of surfaces and a plurality of lower surfaces to form a plurality of The connecting lines are electrically extended to the scribe line to form a plurality of connecting lines; the connecting lines; and the semiconductor package structure described in the item 11 of the scope, which is the same material as the upper sealing layer. For the semiconductor package structure described in the seventh item, 1 contact is formed by cutting a conductive bump. Packaging method: wherein the wafer is integrally formed to include a plurality of defined scribe lines, each wafer has a table above, in which a plurality of bonding pads are formed on the upper surface; internal connection lines are on the upper surface of the wafer, each The internal pads corresponding to the internal connection are formed in which the internal connection lines are directed toward the bumps on the dicing path, and an electrical sealant layer is formed on the upper surface of all the wafers to electrically seal the internal cutting of the wafer along the dicing path. And separated into a plurality of semiconductor packaging structures. 16. The wafer-level packaging method described in item 5 of the patent application scope, wherein the method of forming the internal connection lines is selected from physical vapor deposition (PVD), chemical vapor deposition (CVD), or plasma-assisted chemical deposition [PECVD]. 17. The wafer-level packaging method described in item 5 of the patent application scope, further comprising: forming / underlaying an adhesive layer on the lower surface of all wafers before cutting. flesh Page 16 479305 VI. Patent application scope 1 8. The wafer-level packaging method described in item 15 of the patent application scope, wherein after the step of forming an upper sealant layer, the lower surface of all the wafers is ground 0 1 9 2. The wafer-level packaging method described in item 18 of the scope of patent application, wherein in the grinding of the entire lower surface of the wafer, the portion of the wafer in the scribe line is removed. 20. The wafer-level packaging method as described in item 15 of the scope of patent application, wherein in the step of forming an upper sealant layer, the internal connection lines and bumps are sealed. Page 17