TW546820B - Single transistor ferroelectric transistor structure with high-k insulator and method of fabricating same - Google Patents

Single transistor ferroelectric transistor structure with high-k insulator and method of fabricating same Download PDF

Info

Publication number
TW546820B
TW546820B TW091105734A TW91105734A TW546820B TW 546820 B TW546820 B TW 546820B TW 091105734 A TW091105734 A TW 091105734A TW 91105734 A TW91105734 A TW 91105734A TW 546820 B TW546820 B TW 546820B
Authority
TW
Taiwan
Prior art keywords
ferroelectric
gate
item
crystal structure
patent application
Prior art date
Application number
TW091105734A
Other languages
English (en)
Inventor
Sheng-Teng Hsu
Fengyan Zhang
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Application granted granted Critical
Publication of TW546820B publication Critical patent/TW546820B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Formation Of Insulating Films (AREA)

Description

546820 A7 B7 五、發明説明0 ) 發明背景
本發明係關於一般的半導體技術及更特別的係關於金屬 -鐵電-絕緣體半導體（MFIS)電晶體結構，及製造方法。MFIS 電晶體與MF0S電晶體相似，但是並不受限於使用氧化物當 作絕緣體材料的結構。 先則，單一電晶體鐵電記憶體電晶體使用的係鐵電電極 層疊（stack) ’包括一具有一頂端電極的鐵電閘極。該裝置 可以藉由沉積一鐵電材料，再沉積一覆蓋金屬層以形成。 接著會對該層進行電漿蝕刻（plasma etched)。電漿蝕刻會 降低該鐵電閘極的鐵電特性，從而降低該記憶電晶體的可 Λ f生該鐵電材料亦需要進行鈍化（passivated)以防止氫 污染。鈍化亦可用以降低該鐵電材料與下方氧化物之間有 害的反應。 發明概要 本發明提供一鐵電電晶體結構，包括一覆蓋半導體基板 的鐵電閘極。該鐵電閘極具有一被高—k材料包圍的底部及 側邊，及一被頂端電極覆蓋的頂端。該頂端電極及該高一k 材料係用以將該鐵電電極圍住，從而降低，或消除，因為 氧氣，氫氣，或是其它污染物所造成的污染。該鐵電閘極 底部的高-k材料亦作為一閘極介電質。 亦提供一種形成本發明之鐵電閘極結構的方法。在基板 上方形成一消耗性閘極結構，然後移除該結構以產生一開 口閘極區。在該基板上會沉積一高_k絕緣體，包括該開口 閘極區。在該高-k絕緣體上沉積一鐵電材料，然後利用CMp I,_ - 4 - ^紙張尺度適财S g家標準(CNS)威格㈣χ撕公爱) 546820
進行研磨。接著在其餘的鐵電材料上形成_頂端電極。該 頂端電極及該高-k絕緣體結合之後可用以圍住並且保護該 鐵電材料。 該高-k絕緣體以Zr02、矽酸錘、卜〇、 铪、Hf-A1-0、La-A卜0、氧化鑭、Ta2〇5，或是其它 材料為佳。
Hf02、矽酸 適當的 該鐵電材料以 PGO、PZT、SBT、SB0、SBT〇、SBTN、ST〇 、BT0、BLT、⑽、YMnG3’或是其它適當的材料為佳。 該頂端電極以銥、鉑、釕、氧化銥、氧化鉑、氧化釕，或 是其它適當的材料為佳。 圖式簡單說明 圖1所示者係準備進一步處理之半導體基板的剖面圖。 圖2所示者係具有一覆蓋該介電層之消耗性層之半導體 基板的剖面圖。 圖3所不者係具有一覆蓋該介電層之消耗性閘極結構之 半導體基板的剖面圖。 ，圖4所示者係具有一被氧化物包圍之消耗性閘極結構之 半導體基板的剖面圖。 圖5所示者係將該消耗性閘極移除之後之半導體基板的 剖面圖。 圖6所不者係在沉積一高—k絕緣層之後之半導體基板的 剖面圖。 圖7所不者係在沉積一鐵電材料層之後之半導體基板的 剖面圖。
裝 訂
線 -5- 546820 A7 ____ _Β7_ 五、發明説明（3 ) 圖8所示者係在對該鐵電材料層進行化學-機械研磨之後 之半導體基板的剖面圖。 圖9所示者係在沉積一頂端電極層之後之半導體基板的 剖面圖。 圖10所示者係顯示出蝕刻之後的頂端電極之半導體基板 的剖面圖。 圖11所示者係顯示出一鈍化層及一接觸該裝置結構的金 屬之半導體基板的剖面圖。 發明詳細說明 圖1所示的係利用技藝處理狀態所製備的半導體結構10 。利用到淺溝渠絕緣（STI )以產生絕緣區12，及一位於基板 16中的主動裝置區14。雖然圖中顯示的係STI結構，但是亦 可使用LOCOS絕緣取代STI。該半導體基板最好係矽或是絕 緣體上碎（SOI)。在該基板16上會成長或是沉積一厚度介於 2 nm與20 nm之間的消耗性氧化物18。 圖2所示的係具有一沉積覆蓋該消耗性氧化物18的消耗 性層20。該消耗性層所沉積的厚度介於2〇〇 nm與400 nm之 間。該消耗性層最好係氮化矽或是多晶矽。該消耗性層最 好係可以選擇性蝕刻便可以輕易地移除而不會影響到下方 或是鄰近的材料。 圖3所示的係利用一上方光阻層（未顯示）對該消耗性層 進行成形處理，並且電漿蝕刻該消耗性層所形成的消耗性 閘極結構22。源極區24及汲極區26係形成於該消耗性閘極 結構22的附近。該源極區24及該汲極區26可以利用任何技 • 6- 本紙張尺度適财S S家標準(CNS) A4規格(210X297公爱)" -- 裝 訂
546820 A7 B7 五、發明説明（4 藝處理狀態以形成，但是最好係利用離子植入。離子植入 可以經由該消耗性氧化物完成。 圖4所示的係沉積及研磨氧化物層30之後之該半導體基 板10。該氧化物層30係沉積在該消耗性閘極結構22上方及 周圍區域。該氧化物層30的沉積厚度為該氧化物的最低部 份至少與該消耗性閘極結構22—樣高。該厚度最好係該基 板16上之該消耗性閘極結構22的高度的1至2倍。在該氧化 物層30沉積之後，便會利用化學—機械研磨（CMp)進行研磨 以曝露該消耗性閘極結構22。最好的係，該CMP處理會停止 於該消耗性閘極結構22的頂端而不會移除大量的該消耗性 閘極結構22部份。 圖5所示的係將該消耗性閘極結構22及該下方消耗性氧 化物移除之後之該半導體結構10。移除該消耗性閘極結構 22及該下方消耗性氧化物之後便會留下一開口閘極區犯。 該肩耗性閘極結構2 2及該消耗性氧化物最好係利用濕式姓 刻處理進行移除。亦可以使用其它適當的蝕刻處理。 圖6所示的係在沉積一高—k絕緣體34之後之該半導體結 構1 0。該南-k絕緣體34的厚度最妤介於2 nm與1〇〇 nm之間 。該高_k絕緣體34最好係從可以降低，或消除，氧氣或氫 氣擴散的材料中選擇。該高-k絕緣體34最好係可以作為適 當閘極介電質的材料。該高絕緣體34最好係Zr02。雖然 最好使用Zr〇2，但是亦可以使用其它適當的材料，包括石夕酸锆、Zi-Al-Si-〇、Hf02、矽酸銓、Hf-Al-0、La-A1 -〇、 氧化鑭及Ta205。
裝 訂
線 五、發明説明（5 可以使用各種方法沉積該高—k絕緣體34。可用的沉積方 、：=氣相沉積，包括脈衝CVD、喷濺，或是蒸發。 舉例來说’可以利用原子層沉積方式沉積Zr02,亦稱之 ::脈衝CVD”。原子層沉積方式係用以在該基板上沉積一非 以的材料層。原子層沉積方式係運用一種所熟知的化學 吸收仙的化學現象。在化學吸收作用中’氣相材料會被 吸收至使其飽和的表面中，形成一單層大部 伤慣用的沉積技術都會運用自然的吸收作用方法，其會產 生一具有一純粹統計上的表面覆蓋的多層沉積區。利用化 學吸收作用的優·點，薄膜的成長在厚度及成分中都會非常 的均勻。舉例來說，利用此方法可以利用氯化形 成該第一單層，清洗該ZrCl4系統，然後將該表面曝露於水 蒸氣（H2〇)中便可以在矽上成長Zr〇2薄膜。用以產生氧化锆 層的其它母體包括丙氧化鍅（Zr(i0pr)4)及四甲基庚二酸 锆（Zr(tmhd)4)。對特定的氣體—固體組合而言，化學吸收 作用/、會發生在非吊限定的溫度及壓力範圍中。舉例來說 ，在攝氏300度利用ZrCL及可於矽基板上沉積氧化鍅。 因為該處理會產生一單層，所以藉由添加額外的單層可以 產生較厚的氧化锆層^雖然實驗沉積證明該原子層沉積係 可行的，但是在半導體基板上製備這類特別薄，原子層沉 積的有效工具目前尚未出現。 在較慣用的CVD處理中，亦可以利用上述的母體，以及其 它的母體，沉積Zr02。 ’、 利用慣用系統的一種替代沉積技術係以喷賤目標物以放 -8 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 546820 A7 B7 五 、發明説明（e
置一薄的高_k材料層。所使用的係高純度金屬的喷濺目標 物。會製備一晶圓並且放入一沉積反應室中。接著會將該 晶圓加熱至室溫與攝氏500度之間。接著會將氬（Ar)及氧 (02)之混合物導入該沉積反應室中。在該反應室中會產生 具有大約500W與5kW之間的喷濺功率的電漿。會打開該锆遮 板（shutter)在該晶圓上沉積锆，然後再關閉。該反應室中 的氧氣會促使該目標材料形成Zr02&且同時在該晶圓上形 成沉積。 在本發明沉積方法的另一具體實施例中，可以利用目標 物的蒸發以沉積該薄層。基本的處理約略與上述喷濺相關 的說明實質上相同，但是並不會將該目標物曝露於電漿中 ，而是會將該目標物加熱至約攝氏1，〇〇〇與2,000度之間。 如上所述，可以利用遮板控制沉積的時間長度。 圖7所示的係在沉積一鐵電材料38之後之該半導體結構 10。該鐵電材料會填塞該開口閘極區。較好的係，該鐵電 材料38的沉積厚度會大於該開口閘極區的深度。可以利用 金屬-有機化學氣相沉積（MOCVD)或是化學-溶液沉積（CSD) 處理沉積該鐵電材料38。該鐵電材料最好係從PGO、PZT、 SBT、SBO、SBTO、SBTN ' STO、BTO、BLT、LNO、ΥΜη03 中所 選取出來的。 舉例來說，PGO材料，其亦稱之為Pb5Ge3〇H，可以利用下 面較佳的方法進行沉積。可以利用金屬有機化學氣相沉積 (MOCVD)或是 RTP(快速高溫處理（Rapid Thermal Process) 退火技術沉積該PGO材料。該PGO材料可以在450°C與550°C -9 - 本纸張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
裝 訂
線 546820 A7 _ B7 五、發明説明（7 溫度之間進行沉積。
可以利用具有液體輸送系統之EMC0RE氧化物M0CVD反應 器進行該PG0材料的成長。該pG0材斜的母體如砉1所别。 母體 化學式 蒸氣壓 (mm Hg) 分解溫度（°C ) Pb(TMHD)2 Pb(CuH1902)2 180°C /0. 05 325t Ge(ET0)4 Ge(C2H50)4 b. p. 18 5. 5 °C 表1 PG0薄膜的母體特性 液態母體，例如烷氧基鍺、齒化鍺、烷基鉛，及_化鉛 ’會利用控制溫度的氣泡機（bubb ler)產生母體蒸氣。固態 母體’例如沒-二嗣酸斜，會溶解於溶劑中並且利用具有快 速蒸餾器（flash vaporizer)的液體輸送系統產生母體氣 體。表2所示的係可使用於本發明部份觀點的pG〇母體列表。 母體 化學式室溫下濕氣 蒸氣壓分解溫度 的外觀 穩定度 （mm Hg)(。(：）
GeH4
Ge2H6
Ge3H8
Ge(ET0)4 Ge(0C2H5)4 無色液體敏感 i8yc
GeCl4 (C2H5)2Ge
Cl2 本紙張尺度適用中國國家標準(CNS) A4規格(210 x 297公釐） -10- 546820 A7 B7
Pb Pb(C6H5)4白色粉末 四苯 PbCTMHDhPbCCuiyU 白色粉末 230〇C 325〇C /〇· 05 180°C 325〇C /0. 05
Pb(C2H5)4
溶劑 化學式 沸點溫度（ 四氫夫喃（THF) c4h80 65 - 67〇C 異丙醇 c3h7oh 97〇C 四甘醇二甲醚 Ci〇H2205 275〇C 二曱苯 c6h4(ch3)2 137-144〇C 曱笨 c6h5ch3 111°C 丁醚 [CH3(CH2)3]20 142 - 143〇C 醋酸丁酯 CH3C02(CH2)3CH3 124-126〇C 2-乙基-1~己烧 CH3(CH2)3CH(C2H6)CH2 183-186〇C OH 裝 訂 線 表3 PGO薄膜的溶劑特性 莫耳比5:3的[Pb(thd)2]及[Ge(ET0)4]可以溶解於莫耳比 8:2:1的四氫夫喃，異丙醇及四甘醇二甲醚的混合溶劑中。 該母體溶液中的Pb5Ge30u濃度為0. 1至〇. 3M/L。該溶液會由 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 546820 A7 B7 五、發明説明（g 一泵以〇· 1亳升/分鐘的速率注入至蒸餾器（15(rc )中以形 成母體氣體。該母體氣體會利用一預熱至l5〇 —17(rc的氬氣 流流入該反應器中。該沉積溫度及壓力分別為5〇(rc&5 — 1〇 Torr。該含氧（1000 —2000 SCCffl)的罩幕流（Ar 4〇〇〇 sccffl) 導入該反應器中。沉積之後，該PG0材料會在氧氣中冷卻至 室溫。利用RTP對該PG0材料進行退火。 另外，可以利用CSD處理取代M0CVD沉積該鐵電材料。其 中一種CSD處理的形式係旋塗式（Spin 〇n)方法。舉例來說 ，可以利用該旋塗式方法沉積PG0薄膜。該母體係乙烯乙二 醇乙醚溶液中的醋酸鉛及鍺、丙氧化碘。該母體會在該基 板及任何形成薄膜的覆蓋結構上旋轉。該薄膜會在攝氏5〇 至350度烘烤1至1〇分鐘並且在每次旋塗之後於攝氏4〇〇至 500度進行預退火（preannea ied)烘烤1至15分鐘以便蒸發 該溶劑並且消除該有機成分。每個旋塗層的厚度都介於 10 nm與1〇〇 nm之間。重複幾次之後，該PG〇薄膜便可以產 生所需要的厚度。該PG0薄膜會在氧氣中於攝氏500至6〇〇 度進行結晶（crystal lized)5分鐘至3小時。不需要太多的 實驗’便可以達到所需要之薄膜厚度的處理的最佳化。 圖8所示的係在對該鐵電材料進行CMP產生鐵電閘極4〇之 後之該半導體結構1〇。較理想，該CMP處理會停止於該氧化 層30的頂端。 圖9所示的係在沉積一電極層42之後之該半導體結構1〇 。該電極層42包括銥，鉑，釕，或是其它的氧化物。如圖 10所示，會對該電極層42進行成形處理及蝕刻以形成一該 -12-
546820 A7 ------—_B7 五、發明説明（1() ) ~ '—- 頂端電極44。該電極層42可以利用光阻或是硬遮罩材料， 例如，TiN、Ti〇2、TiA1〇3、Si〇2、SiN，或是其它適當的材 料，進打成形處理。該電極層可以利用電漿蝕刻或是或是 其它適當的蝕刻處理進行姓刻。 在替代的具體實施例中，可以利用鑲嵌（inlaid或 damascene)的方式形成該頂端電極44。會利用與用於形成 該鐵電閘極相同的方法形成一溝渠，其詳細說明如上所述 。接著會在該溝渠上沉積一金屬，例如銀、麵、釕，或是 其它的氧化物，並且利用CMP進行研磨以形成該頂端電極 44 〇 圖10所不的係具有一鐵電閘極結構46的該半導體結構1〇 。該鐵電閘極結構46包括一沿著底部及侧邊受到該高_k絕 緣體34保護的鐵電閘極40，其中該高—k絕緣體會形成側牆 48，及上面的頂端電極44。這可以降低，或是消除，該鐵 電閘極40中從氧或是氫擴散至該鐵電閘極4〇的污染物。在 部份的具體實施例中，使用該高一k絕緣體34便可以不需要 將該鐵電材料鈍化。 圖11所示的係利用技藝方法狀態鈍化及金屬化之後之該 半導體結構10。與該源極區24，該汲極區26，及該頂端電 極44相連的連接50會延伸穿過鈍化層52。圖中所示的該連 接50係簡化的結構。可以利用任何目前技藝的金屬化技術 ，包括銅金屬化。該金屬化包括位障層及其它與各種金屬 化技術相關的層。 雖然上述中利用沉積進行金屬化之後便會進行钱刻，但 -13- ^紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)~' 546820 A7 B7 五、發明説明Cm ) 是亦可以利用鑲嵌金屬化處理取代與上面該頂端電極44相 關的處理。舉例來說，對銅金屬化而言利用鑲嵌金屬化處 理係較好的方式。 -14- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐)

Claims (1)

1 · 一種鐵電電晶體結構，包括： a) —覆蓋一半導體基板的鐵電閘極；及 b) —插入於該鐵電閘極及該半導體基板之間的高噠 材料。 2·如申請專利範圍第1項之鐵電電晶體結構，其中該半導 體基板係矽或SOI。 3·如申請專利範圍第1項之鐵電電晶體結構，其中該鐵電 閘極係 PG0、PZT、SBT、SB0、SBT0、SBTN、ST0、BT0、 BLT 、 LN0或ΥΜη03 。 4·如申請專利範圍第1項之鐵電電晶體結構，其中該高一k 材料係Zr02、矽酸锆、Zr-A卜Si-0、Hf02、矽酸铪、η卜A1—〇 、La-Al-0、氧化鑭或 Ta205。 5·如申請專利範圍第1項之鐵電電晶體結構，其中該鐵電 閘極係利用化學溶液沉積（CSD)方法進行沉積。 6·如申請專利範圍第1項之鐵電電晶體結構，進一步包括 相鄰於該鐵電閘極的高_k侧牆。 7·如申請專利範圍第6項之鐵電電晶體結構，其中該高一k 侧牆包括Zr02、矽酸錘、Zr-A卜Si-0、Hf02、矽、 Hf-A1-0、La-A卜0、氧化鑭或 Ta205。 8·如申請專利範圍第6項之鐵電電晶體結構，其中該高一k 側牆包括與該高-k材料相同的材料。 9·如申請專利範圍第1項之鐵電電晶體結構，進—步包括 一覆蓋該鐵電閘極的頂端電極。 10·如申請專利範圍第9項之鐵電電晶體結 π τ 1¾頂端 546820 申請專利範圍 11 電極包括銥、鉑、釕、氧化銥、氧化鉑、或是氧化釕。 一種鐵電電晶體結構，包括一具有一底部，侧邊及一覆 蓋一半導體基板之頂端的鐵電閘極，其中該鐵電閘極係 被該底部及該側邊上的高-k材料及該頂端上的頂端電 極的結合所包圍。 12 其中該半導 其中該鐵電 ST0 、 ΒΤ0 、 如申請專利範圍第11項之鐵電電晶體結構 體基板係矽或SOI。 13·如申請專利範圍第11項之鐵電電晶體結構 閘極係 PG0、PZT、SBT、SB0、SBT0、SBTN BLT、LN0或 ΥΜη03。 14·如申請專利範圍第u項之鐵電電晶體結構，其中該高一^ 材料係zr〇2、碎酸結、Zr-A卜Si_〇、Hf〇2、碎酸給、Η=ι〇 、La-A卜0、氧化鑭或Ta2〇5。 15. 如申請專利範圍第u項之鐵電電晶體結構，其中該鐵電 閉極係利用化學溶液沉積（CSD)方法進行沉積。 16. 如申請專利範圍第u項之鐵電電晶趙結構，其。中該頂端 電極包括銥、鉑、釕、氧化銥、氧化鉑或氧化釕。 17. :種在基板上形成鐵電電晶體結構的方法，包括的步驟 a) 形成一覆蓋該基板的消耗性閘極結構； b) 移除該消耗性閘極結構； c) 在該基板上沉積一高—k材料；及 d) 在該高—k材料上沉積一鐵電材料。 18·如申請專利範圍第17項之方法，其 # r形成該消耗性閘極 -16 本纸張尺度g家鮮(CNS)鑛格(21()><297公爱） 546820 申請專利範圍 A BCD 19· 20. 21· 22, 23. 24· 25. 26. 的進行步驟包括：. a) >儿積一消耗性閘極材料層並且進行圖案形成處理 ’以便形成一消耗性閘極； b) 形成一覆蓋該消耗性閘極的氧化物； c) 及研磨該氧化物以曝露該消耗性閘極。 如申明專利範圍第18項之方法，其中形成該消耗性閘極 材料層係氮化石夕或多晶石夕。 如申％專利範圍第18項之方法，其中該研磨步驟係使用 化學-機械研磨（CMP)的方式進行。如申請專利範圍第17項之方法，#中沉積該高—k材料的 步驟係藉由化學氣相沉積（CVD)、脈衝CVD、喷濺或是 蒸發的方式進行。 如申请專利範圍第Π項之方法，其中沉積該高料的 步驟係沉積ζΓ〇2、矽酸鍩、Zr_A1_Si_〇、Hf〇2、矽酸姶 、Hf-A1-0、La-A1-0、氧化鑭或^此。 如申凊專利範圍第17項之方法，其中沉積該鐵電材料的 步驟係藉由使用金屬-有機化學氣相沉積（M〇CVD”或是 化學溶液沉積（CSD)的方式進行。如申請專利範圍第17項之方法，其中沉積該鐵電材料的 步驟係積 PGO、PZT、SBT ' SBO、SBTO、SBTN、STO、 BTO 、 BLT 、 LN0或YMh03 。如申請專利範圍第17項之方法，進_步包括形成—頂端 電極的步驟。如申請專利範圍第25項之方法，其中該頂端電極係銀、
-17- 546820 A B c D 六、申請專利範圍 始、氧化錶或氧化始。 27·如申請專利範圍第25項之方法，其中形成該頂端電極的 步驟係藉由沉積並進行圖案形成處理一頂端電極層的 方式進行。 28.如申請專利範圍第25項之方法，其中形成該頂端電極的 步驟係藉由使用一鑲嵌處理的方式進行。 -18- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）
TW091105734A 2001-03-28 2002-03-25 Single transistor ferroelectric transistor structure with high-k insulator and method of fabricating same TW546820B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/820,023 US6602720B2 (en) 2001-03-28 2001-03-28 Single transistor ferroelectric transistor structure with high-K insulator and method of fabricating same

Publications (1)

Publication Number Publication Date
TW546820B true TW546820B (en) 2003-08-11

Family

ID=25229687

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091105734A TW546820B (en) 2001-03-28 2002-03-25 Single transistor ferroelectric transistor structure with high-k insulator and method of fabricating same

Country Status (4)

Country Link
US (2) US6602720B2 (zh)
JP (1) JP2002329847A (zh)
KR (1) KR100472258B1 (zh)
TW (1) TW546820B (zh)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7554829B2 (en) 1999-07-30 2009-06-30 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
US6852167B2 (en) * 2001-03-01 2005-02-08 Micron Technology, Inc. Methods, systems, and apparatus for uniform chemical-vapor depositions
US7037862B2 (en) * 2001-06-13 2006-05-02 Micron Technology, Inc. Dielectric layer forming method and devices formed therewith
DE10228768A1 (de) * 2001-06-28 2003-01-16 Samsung Electronics Co Ltd Nicht-flüchtige Floating-Trap-Halbleiterspeichervorrichtungen, die Sperrisolationsschichten mit hohen Dielektrizitätskonstanten enthaltend, und Verfahren
US7253467B2 (en) * 2001-06-28 2007-08-07 Samsung Electronics Co., Ltd. Non-volatile semiconductor memory devices
US8253183B2 (en) 2001-06-28 2012-08-28 Samsung Electronics Co., Ltd. Charge trapping nonvolatile memory devices with a high-K blocking insulation layer
US20060180851A1 (en) * 2001-06-28 2006-08-17 Samsung Electronics Co., Ltd. Non-volatile memory devices and methods of operating the same
US7473959B2 (en) * 2001-06-28 2009-01-06 Samsung Electronics Co., Ltd. Non-volatile semiconductor memory devices and methods of fabricating the same
TW512463B (en) * 2001-09-28 2002-12-01 Macronix Int Co Ltd Method for epitaxial growth of lead zirconate titanate film
US6664116B2 (en) * 2001-12-12 2003-12-16 Sharp Laboratories Of America, Inc. Seed layer processes for MOCVD of ferroelectric thin films on high-k gate oxides
US6893984B2 (en) * 2002-02-20 2005-05-17 Micron Technology Inc. Evaporated LaA1O3 films for gate dielectrics
US7045430B2 (en) * 2002-05-02 2006-05-16 Micron Technology Inc. Atomic layer-deposited LaAlO3 films for gate dielectrics
US7160577B2 (en) * 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US7589029B2 (en) * 2002-05-02 2009-09-15 Micron Technology, Inc. Atomic layer deposition and conversion
US6531325B1 (en) * 2002-06-04 2003-03-11 Sharp Laboratories Of America, Inc. Memory transistor and method of fabricating same
US7135421B2 (en) * 2002-06-05 2006-11-14 Micron Technology, Inc. Atomic layer-deposited hafnium aluminum oxide
US6664156B1 (en) * 2002-07-31 2003-12-16 Chartered Semiconductor Manufacturing, Ltd Method for forming L-shaped spacers with precise width control
US6884739B2 (en) * 2002-08-15 2005-04-26 Micron Technology Inc. Lanthanide doped TiOx dielectric films by plasma oxidation
JP4887481B2 (ja) * 2002-08-20 2012-02-29 独立行政法人産業技術総合研究所 半導体強誘電体記憶デバイス
JP5019297B2 (ja) * 2002-08-20 2012-09-05 独立行政法人産業技術総合研究所 半導体強誘電体記憶デバイスの製造方法
US7199023B2 (en) * 2002-08-28 2007-04-03 Micron Technology, Inc. Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed
US7084078B2 (en) * 2002-08-29 2006-08-01 Micron Technology, Inc. Atomic layer deposited lanthanide doped TiOx dielectric films
US7101813B2 (en) * 2002-12-04 2006-09-05 Micron Technology Inc. Atomic layer deposited Zr-Sn-Ti-O films
US6958302B2 (en) * 2002-12-04 2005-10-25 Micron Technology, Inc. Atomic layer deposited Zr-Sn-Ti-O films using TiI4
KR100947562B1 (ko) * 2002-12-26 2010-03-15 매그나칩 반도체 유한회사 강유전체막을 이용한 반도체 메모리소자의 제조 방법 및그의 셀 트랜지스터
DE10308970A1 (de) * 2003-02-28 2004-09-09 Infineon Technologies Ag Halbleiterspeicherzelle und Verfahren zu deren Herstellung
US7135369B2 (en) * 2003-03-31 2006-11-14 Micron Technology, Inc. Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9
KR100741983B1 (ko) 2004-07-05 2007-07-23 삼성전자주식회사 고유전율의 게이트 절연막을 갖는 반도체 장치 및 그 제조방법
US7601649B2 (en) * 2004-08-02 2009-10-13 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7973348B1 (en) * 2004-08-06 2011-07-05 Dalton David I Single transistor charge transfer random access memory
US7267996B2 (en) * 2004-08-20 2007-09-11 Sharp Laboratories Of America, Inc. Iridium etching for FeRAM applications
US7081421B2 (en) 2004-08-26 2006-07-25 Micron Technology, Inc. Lanthanide oxide dielectric layer
US7588988B2 (en) 2004-08-31 2009-09-15 Micron Technology, Inc. Method of forming apparatus having oxide films formed using atomic layer deposition
US7494939B2 (en) * 2004-08-31 2009-02-24 Micron Technology, Inc. Methods for forming a lanthanum-metal oxide dielectric layer
JP4785180B2 (ja) * 2004-09-10 2011-10-05 富士通セミコンダクター株式会社 強誘電体メモリ、多値データ記録方法、および多値データ読出し方法
US7235501B2 (en) * 2004-12-13 2007-06-26 Micron Technology, Inc. Lanthanum hafnium oxide dielectrics
US7560395B2 (en) * 2005-01-05 2009-07-14 Micron Technology, Inc. Atomic layer deposited hafnium tantalum oxide dielectrics
US7687409B2 (en) * 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7390756B2 (en) * 2005-04-28 2008-06-24 Micron Technology, Inc. Atomic layer deposited zirconium silicon oxide films
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US7410910B2 (en) * 2005-08-31 2008-08-12 Micron Technology, Inc. Lanthanum aluminum oxynitride dielectric films
US7335562B2 (en) * 2005-10-24 2008-02-26 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US7709402B2 (en) * 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US7605030B2 (en) 2006-08-31 2009-10-20 Micron Technology, Inc. Hafnium tantalum oxynitride high-k dielectric and metal gates
US7759237B2 (en) * 2007-06-28 2010-07-20 Micron Technology, Inc. Method of forming lutetium and lanthanum dielectric structures
KR101338158B1 (ko) * 2007-07-16 2013-12-06 삼성전자주식회사 비휘발성 기억 소자 및 그 형성 방법
US7800166B2 (en) 2008-05-30 2010-09-21 Intel Corporation Recessed channel array transistor (RCAT) structures and method of formation
WO2011043794A2 (en) * 2009-09-29 2011-04-14 Yale University Ferroelectric devices including a layer having two or more stable configurations
US20130237046A1 (en) * 2012-03-09 2013-09-12 Chien-Ting Lin Semiconductor process
FR3051973B1 (fr) 2016-05-24 2018-10-19 X-Fab France Procede de formation de transistors pdsoi et fdsoi sur un meme substrat
KR20180111303A (ko) 2017-03-31 2018-10-11 에스케이하이닉스 주식회사 강유전성 메모리 장치 및 그 제조 방법
KR20190001455A (ko) 2017-06-27 2019-01-04 에스케이하이닉스 주식회사 강유전성 메모리 장치
US11101365B2 (en) * 2019-01-31 2021-08-24 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device and semiconductor device fabricated by the same
KR102709128B1 (ko) * 2019-01-31 2024-09-23 삼성전자주식회사 반도체 장치의 제조 방법 및 이를 이용하여 제조한 반도체 장치
JP2021044510A (ja) 2019-09-13 2021-03-18 キオクシア株式会社 半導体記憶装置
KR20210041858A (ko) 2019-10-08 2021-04-16 김경선 접속기 일체형 조명등
US11706928B2 (en) * 2020-10-30 2023-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device and method for fabricating the same
US20240120420A1 (en) * 2022-10-05 2024-04-11 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Ferroelectric field-effect transistors with a hybrid well

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5070026A (en) * 1989-06-26 1991-12-03 Spire Corporation Process of making a ferroelectric electronic component and product
JP2834603B2 (ja) * 1991-08-16 1998-12-09 ローム株式会社 強誘電体デバイス
US5384729A (en) * 1991-10-28 1995-01-24 Rohm Co., Ltd. Semiconductor storage device having ferroelectric film
US5274249A (en) * 1991-12-20 1993-12-28 University Of Maryland Superconducting field effect devices with thin channel layer
US5858543A (en) * 1993-09-20 1999-01-12 Dow Corning Corporation Silane coated flavor/aroma barrier film
KR0141160B1 (ko) * 1995-03-22 1998-06-01 김광호 강유전체 메모리 장치 및 그 제조방법
JP3027942B2 (ja) * 1996-05-15 2000-04-04 日本電気株式会社 半導体装置及びその製造方法，並びに半導体集積回路装置
US5858843A (en) * 1996-09-27 1999-01-12 Intel Corporation Low temperature method of forming gate electrode and gate dielectric
KR100238210B1 (ko) * 1996-10-28 2000-01-15 윤종용 산화티탄마그네슘 박막을 이용한 fram 및 ffram 소자
US6048738A (en) * 1997-03-07 2000-04-11 Sharp Laboratories Of America, Inc. Method of making ferroelectric memory cell for VLSI RAM array
JP3055494B2 (ja) * 1997-06-10 2000-06-26 日本電気株式会社 強誘電体メモリ及びその製造方法
US6054355A (en) * 1997-06-30 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device which includes forming a dummy gate
US6020024A (en) * 1997-08-04 2000-02-01 Motorola, Inc. Method for forming high dielectric constant metal oxides
US6352913B1 (en) * 1998-04-28 2002-03-05 Compaq Computer Corporation Damascene process for MOSFET fabrication
US6339238B1 (en) * 1998-10-13 2002-01-15 Symetrix Corporation Ferroelectric field effect transistor, memory utilizing same, and method of operating same
US6048740A (en) 1998-11-05 2000-04-11 Sharp Laboratories Of America, Inc. Ferroelectric nonvolatile transistor and method of making same
US6197668B1 (en) * 1998-11-06 2001-03-06 Advanced Micro Devices, Inc. Ferroelectric-enhanced tantalum pentoxide for dielectric material applications in CMOS devices
JP2000243922A (ja) * 1999-02-23 2000-09-08 Fuji Electric Co Ltd 強誘電体ゲート電界効果トランジスタの製造方法
JP2000252372A (ja) * 1999-02-26 2000-09-14 Sharp Corp 半導体メモリ装置及びその製造方法
JP2001118942A (ja) * 1999-10-21 2001-04-27 Matsushita Electronics Industry Corp トンネルチャネルトランジスタおよびその駆動方法
TW502255B (en) * 2000-02-14 2002-09-11 Infineon Technologies Ag Method for reading and storing a state from or in a ferroelectric transistor in a memory cell, and a memory matrix

Also Published As

Publication number Publication date
US6906366B2 (en) 2005-06-14
US20030027360A1 (en) 2003-02-06
US20030205742A1 (en) 2003-11-06
JP2002329847A (ja) 2002-11-15
KR100472258B1 (ko) 2005-03-08
KR20020077181A (ko) 2002-10-11
US6602720B2 (en) 2003-08-05

Similar Documents

Publication Publication Date Title
TW546820B (en) Single transistor ferroelectric transistor structure with high-k insulator and method of fabricating same
TW535288B (en) MFOS memory transistor and method of fabricating same
JP4700181B2 (ja) 原子層蒸着法を用いた薄膜形成方法
TWI446522B (zh) 半導體裝置及其製造方法
KR100519800B1 (ko) 란타늄 산화막의 제조방법 및 이를 이용한 모스 전계효과트랜지스터 및 캐패시터의 제조방법
US6383873B1 (en) Process for forming a structure
JP4160638B2 (ja) 半導体装置
CN100468638C (zh) 半导体元件的制造方法
WO1999032685A1 (en) Method for selectively depositing bismuth based ferroelectric films
TWI312543B (en) Process for fabricating a mim capacitor
US20150140838A1 (en) Two Step Deposition of High-k Gate Dielectric Materials
TW201205782A (en) Semiconductor device with metal gates and method for fabricating the same
US6417042B2 (en) Method of manufacturing a capacitor in a semiconductor device
JP3419665B2 (ja) 半導体装置の製造方法
JP4486735B2 (ja) 半導体メモリ素子のキャパシタの製造方法
US7371670B2 (en) Method for forming a (TaO)1-x(TiO)xN dielectric layer in a semiconductor device
TWI354711B (zh)
JP4109304B2 (ja) 半導体装置およびその製造方法
JP4812164B2 (ja) 半導体素子のキャパシタ製造方法
KR100882090B1 (ko) 반도체소자의 캐패시터 제조방법
JP2002184978A (ja) 半導体装置及びその製造方法
KR20060070010A (ko) 박막 제조 방법 및 이를 이용한 게이트 구조물,커패시터와 플래시 메모리 장치의 제조 방법
JP2004247324A (ja) 強誘電体キャパシタの製造方法
KR100600261B1 (ko) 반도체 소자의 캐패시터 형성방법
US20050014296A1 (en) Mocvd of tio2 thin film for use as feram h2 passivation layer

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees