TW540162B - Electronic devices comprising thin-film transistors, and their manufacture - Google Patents

Electronic devices comprising thin-film transistors, and their manufacture Download PDF

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TW540162B
TW540162B TW091105468A TW91105468A TW540162B TW 540162 B TW540162 B TW 540162B TW 091105468 A TW091105468 A TW 091105468A TW 91105468 A TW91105468 A TW 91105468A TW 540162 B TW540162 B TW 540162B
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mask layer
layer
gate
holes
gate electrode
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TW091105468A
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Frank Wilhelm Rohlfing
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Koninkl Philips Electronics Nv
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0331—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers for lift-off processes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78627—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD

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Description

540162 A7 _B7_._ 五、發明説明（1 ) 本發明與包含薄膜電晶體（此後稱之為TFT)之電子裝置有 關；該TFT係建構於譬如，玻璃或絕緣聚合物基板之上； 該裝置則可以是譬如，主動矩陣式之液晶顯示器或其他的 全平面顯示器，或其他任何以TFT為驅動電路之矩陣型電 子裝置，像是薄膜資料儲存器或是影像感測器。本發明亦 與製造此種電子裝置之方法有關。 多年來，業界投注相當多的關注在如何於玻璃及/或其 他價格低廉之絕緣基板上，發展可應用在多項電子領域之 TFT薄膜電路。此種以非晶或多晶半導體膜所製造出來之 TFT可譬如，如美國專利US-A-5，130,829(我們的參考字號： PHB 33646)中所述的，作為全平面顯示器中單元矩陣的開 關元件。較新的發展重點則是在如何將TFT(通常採用的是 多晶矽）製造整合成為譬如，此種單元矩陣的驅動電路。所 以，已公佈的歐洲專利申請案ΕΡ-Α-0 629 003(我們的參考字 號：PHB 33845)中即描述了此種電子裝置，包括基板上之 薄膜開關電晶體開關矩陣，以及位於該矩陣外之週邊驅動 電路，另包括與該矩陣之開關電晶體相連之薄膜電路電晶 體。本文在此將US-A-5,130,829及ΕΡ-Α-0 629 003之全文併入 以作參考。 不幸地是，此種TFT的電晶體會有令人不快的場致效應 特性，特別是那些以低溫程序所形成，以多晶矽為本之 TFT尤然。有幾種不穩定的機制會產生，譬如，導通電流 的耗損，多晶矽中之偏壓致態，以及熱載子致態及熱載子 陷擾。另外會產生的效應則是汲極場致的漏電流增加。電 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 540162 A7 ________B7 五、發明説明（Γ7 ^-- 晶體一些特性（譬如，關閉狀態下之漏電流，臨界電壓以及 導通電流）的退化，嚴重地限制了此種電晶體在本文所提及 電路中的可用性。 降低TFT中此種效應的方法之一是，產生一個摻雜濃度 較汲極區為低之場緩區。TFT具有一個絕緣閘，毗鄰於結 晶半導體膜，係用以控制該半導體膜中，源極與汲極間之 導電通道。該場緩區即位在TFT汲極區與該導電通道之間 。可置於閘極側，也可全部或部份地與閘極重疊。 傳統場緩架構的問題在於，它們另需執行一個低劑量佈 植步驟。高劑量的佈植是用來形成源極與汲極，而低劑量 的佈植則是產生場緩區時所需要的。雖然，加入場緩區可 相當私度地改良TFT的效能，但多加一個佈植的步驟卻會 使TFT的製程變得較為複雜。吾人需要一種能同時製出源 極、汲極以及場緩區的佈植步驟，以簡化TFT的製程，如 此一來，將可降低製造成本、改善產能及良率。曰本專利 說明書第9148266號即針對此問題提出一種製造TFT之法， 此法將閘電極的邊緣予以氧化，形成多孔膜。該等多孔膜 係面罩之作用，目的在使植入主動區中之雜質離子的量減 少，藉以在源極與汲極的旁邊，形成一場缓區。 本發明之目的在於，提供出一種改良法，可在單一佈植 步驟中定義出場緩區。 本發明所提供之方法，可製造出含有薄膜電晶體之電子 裝置’該法包含下列之步驟： · (a)於一絕緣基板之上，形成一半導體膜； -5-
540162 A7 B7 五、發明説明（3 ) (b)於該半導體膜之上，沈積一第一面罩層，並將其部份 移除以形成多個穿透於其之孔洞，該等孔洞實質垂直地從 該面罩層之上表面延伸至該面罩層之下表面； (C)將該第一面罩層圖案化為一第一圖案； (d) 於該第一面罩層圖之上，沈積一第二面罩層； (e) 圖案化該第二面罩層，於該第一圖案區域範圍内，定 義出一第二圖案；以及 ⑴至少以該第一面罩層為佈植面罩，對該半導體膜進行 佈植，5亥至少界定了一些孔洞之第一面罩層的一部份，部 伤地了面罩該佈植，如此，該佈植定義出源極與汲極區， 一介於該源極與汲極區間之未摻雜導電通道，以及一摻雜 〉辰度較該汲極區為低之場緩區，其係位於該導電通道及該 沒極區之間。 疋故，利用疋義場緩區用之面罩層或型板，可將源極， 汲極與場緩區的佈植一併完成，此係以一種可控制的方式 相對於;又有型板下的源極與汲極區，使用較少的佈植劑 量。 β亥第面罩層疋義了大置的垂直孔洞，這些孔洞直達下 層，摻質將通過它們佈植至下層。該型板為孔洞所覆之小 部伤區域，決定了型板所定義之區域中其雜質的有效濃度 。孔洞的數量愈多，尺寸愈小，冑能製造出摻雜分佈為準 均質之場緩區。後續可利用雷射，一併完成摻雜物的活化 與擴散，使摻雜物在半導體材料中側向擴散，以增加場緩 區的摻雜均勻度。因此，摻雜劑量及分佈可用一種可护制 -6 -
裝 訂
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540162 A7 B7 五、發明説明（4 ) 的方式，即以選擇適當的孔洞密度及孔洞尺寸的方式，予 以指定。以下將討論行此觀念之技術。 若使用前提及之日本專利說明書第9148266號中所揭示之 方法，則只需改變該氧化層的厚度，就可調整該場緩區中 摻質濃度與源極與沒極區中摻質濃度的相對關係。 可使用譬如，微影法或·*奈米技術”，於型板中製備出孔 洞，至少該使用何種方法，則端賴孔洞的數目及尺寸而定 ，該奈米技術則係一種定義奈米級形狀（而非微米級）之技 術。 步驟（b)，係於該半導體膜、之上形成一具有多孔洞穿透其 間之第一面罩層，此步驟包含：於該半導體膜上提供出一 陣列其間有間隔之隆起外型，於其上沈積該第一面罩層， 以及將該隆起外型，連同該第一面罩層材質覆蓋於該外型 上之部份，一併移除。另外一作法則是，步驟⑻包含：於 該半導體膜之上，沈積一第一面罩層；於該第一面罩層之 上，定義一蝕刻面罩；以及蝕刻出多個穿逸該第一面罩層 材質之孔洞。 將該第一面罩層圖案化為一第一圖案之步驟⑷，可在該 於第一面罩層中蝕刻孔洞的步驟之前執行。 在本方法之較佳具體實施例中，於該第一面罩層中形 成孔洞之步驟，係在步驟⑷之後執#，如此使該等孔 洞穿透形成於該第一面罩層之曝露區。 有幾種方法可完成第一及第二面罩層的圖案化。在一較 佳製程中，步驟（d)於步驟（c)前執行，以及該方法於步驟 -7- ^張尺度適用中國國家標準(Cliinii：格(21GX 297公釐)-〜--^_ 540162
2)_之則’步驟⑷之後，另包含下列步驟（h):圖案化該 第二面罩層以在該第一面罩層中形《步驟（c)中圖案化該 第1罩層時所需之面罩。更特定地，其中步驟（h)包含 ’於'亥第二面罩層中定義第二圖案，之後於該第二面罩層 之鄰接處，形成側壁邊襯以定義該第一圖案。 曰 …圖案化該第二層之步驟(e)包含：於該第二面罩層上之· 面罩層中’疋義該第二圖案，氧化該第二面罩層之曝 路口P份，以及之後將該第二面罩層之氧化部份去除，藉以 於該第二面罩層中定義出該第二圖案。 使用此氧化技術或邊襯可、製造出相對較窄的場緩區，使 相關的寄生電容及串聯電阻效應得以較低。 最好是，該第-面罩層形成一閘電極層，且該方法在步 驟U)之後，步驟（b)之前，包含沈積一閘絕緣層之步驟。 、言樣可开個王自我對齊，閘極重疊之輕摻雜汲極（ΜΑ GOLDD)裝置結構。 或者是，該第一面罩層形成一閘絕緣層，而該第二面罩 層則形成一閘電極層。 根據另一面向，本發明提出一種包含薄膜電晶體之電子 裝置，該薄膜電晶體包含一於絕緣基板上之已圖案化半導 體膜，-於該半導體膜上之閘絕緣層，以及一於問絕緣層 上之閘電極；該半導體膜包含源極與汲極區，一介於該源 極與汲極區間之未摻雜導電通道，以及一摻雜濃度較該汲· 極區為低之場緩區，其係位於該導電通道及該汲極區之間 ，·其中部份的閘電極係與場緩區重疊，並具多個定義的孔 -8 _ 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公釐) '' -—-- A7
A7 B7 五、發明説明（7 ) 閘極重疊， 汲極區的邊緣實質地對齊。
且乂些TFT及/或其他電路TFT之閘極其邊緣與 一具體實施步驟； 二具體實施步驟；以及 說明在材料層中形成 圖1 A至c是本發明製造TFT之第一 圖2A及B是本發明製造τρ丁之第二· 圖3A至C以及4A至C是二個例子，
應注意，這些圖式僅為圖例，並未按比例繪製。為了明 晰及方便起見， 縮小。 這些圖式某些部份的尺寸有按比例放大或 圖1所示之過程，適於製造具場緩之自我對齊（sa)tft架 構，其中佈植場緩區之面罩層在定義閘極之前即已形成。 圖1A中所示結構之形成如下。首先，於基板4之上沈積 一半V體薄膜2。譬如，可先沈積非晶矽後再以帶能量的 輻射光束像疋雷射光，予以晶格化。此膜層的厚度大約 是40奈米。接著沈積出閘絕緣層6 (譬如，二氧化矽），及絕 緣層8，此一層組成第一面罩層。此材質層中具多個孔洞 ，其形成方式容後說明。第一面罩層形成之後，再沈積並 圖案化出一材質通常為鋁鈦合金之閘電極層1〇(形成第二面 罩層），並沿著它的兩邊，形成一由譬如，氧化石夕或氮所構 成的邊襯12，14。 之後，如圖1B所繪，以該已圖案化之閘電極層1〇及邊襯 12，14作為面罩，蝕刻絕緣層8。 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 540162
然後，移去邊襯並對曝露在該多孔絕緣層8(是為第一面 罩σ卩伤地）之外及該閘層ιο(是為第二面罩）之外的半導體 ㈣2進行佈值。佈植後即可在該半導體膜2中，定義出源 極16，汲極18，場緩區20、22，以及導電通道24。 圖2所不為製造具有場緩區的自我對齊TFT之法，此法中 ，孔洞的引入該絕緣層8中乃在定義出閘極之後。圖2B可 看出，這些孔洞會侷限在絕緣層8的曝露部份26及28。一種 有引於圖2的處理流程則是’在定義出問極層⑺之後，即 仃將孔洞引入絕緣層8之中，接著才執行邊襯Η，Μ的製作 、巴緣層8的姓刻、該等邊襯的移除以及離子的佈植。 上述關於圖1及2之製造過程，將產生出-完全自我對赢 ^摻雜汲極（FSALDD)裝置。絕緣層⑷共同形成閑介 ，層。應了解’實例中的絕緣層6可以省略，而由絕緣W 早獨：形成該絕緣介電層。或者是，將圖…中之層8(代 緣：二、面罩層)改為導電材質，作為閘極，而層1 〇為絕 、’貝形成第二面罩層）或另種合適的面罩用材質。可 (出FSA^將提供出全自我對齊，閘極重叠之輕摻雜沒極 曰OLDD)裝置。此法可單獨地以層8來作為佈植面 ⑺。如此1可在執行佈植摻雜步驟之前，先移除層 ::，無淪如冑’若是由層8來作閘極層，則最終裝 置中疋沒有層1〇的。 、 ^極2與&極區16及18中#典型推雜等級是’譬如， 1〇⑽ < 更多。場緩區2G及22的#雜·等級則是在1()13cm.2。 本紙張尺度 裝 訂 -11 - 540162
不論是閘補償型的TFT或是閘重疊型的丁 FT，其場緩區2〇 及22的最佳長度，均取決於一些因素，這其中包括··通道 區24的長度、閘極與最大汲極的操作電壓以及通過丁ρ丁的電 流位準。場緩區20及22的一般標準長度是，若τρτ的通道長 度24在5微米至1〇微米，則在約！微米至3微米的範圍。若 使用的是本發明之全自我對齊式具體實施例，則可擁有相 對較窄之LDD區，長度可在1微米以下。 應了解，以上之法可有多種的修改版，均可產生出具場 緩區之FSA裝置。譬如，取消以邊襯來定義_或g〇lde^ 的方式，而改採以陽極氧化或過度蝕刻閘電極層1〇的方式 來定義，隨後再將孔洞引人絕緣層8中，1進行摻雜物的 佈植。SALDD及SAG0LDD同樣地可用該方法形成，但定義 層8及10時需用不同的光罩。 半導體膜2中換雜物的均勻度，取決於絕緣層8中孔洞的 尺寸及數量。孔洞的數量愈多，〖寸愈小，愈能製造出摻 ，分：為準均質之場緩區1有必要，可利用能量光束（像 疋，田射），一併完成摻雜物的活化與擴散，使摻雜物在半 導體材料中側向擴散，以增加摻雜物的均勾度。 =吏GOLDD裝置具有良好的穩^度，g〇ldd區中的佈植 劑量最好應低於源極與汲極區的佈植劑量不止一個數量級 。因此’層8中被孔洞所佔據的區域應小於腦。GOLDD具 體實施例乃以層8作A + k A + 一 乍為閘電極。相較於層中沒有任何孔洞 所能產生的電場而t , 士 士 ，， ° 中有孔洞的閘·電極，其閘電場是較 -12-
540162 A7 _____ B7_ 五、發明説明（^~^ ~ 、 低的。不過，若孔洞所涵蓋的面積低於1〇%，則電場的降 低程度是可忽略的。 現要說明形成孔洞的技術。此處理過程包括：於該半導 體膜上提供出一陣列其間有間隔之隆起外型，於其上沈積 孩第一面罩層，以及將該隆起外型，連同該第一面罩層材 貝覆蓋於该外型上之部份，一併移除。此種技術牽涉到於 閘介電質的頂端，發展自組性的奈米島陣列。s. Tsuchiya， Μ· Green及R.R.A· Syms於電化學及固態信函期刊3, 44_46 ’ (2000)中所共同發表的論文：”於氟碳烷活性離子蝕刻電漿 中，以氯化鉋島陣列為光阻之結構製作”以及M· Green及丁丄
Tsuchiya於Vac. Sci· and Tech. B17, 2074-2083 (1999)中共同發表 的論文：”以介觀之半球陣列作為結構製作中之光阻•，中說 月了半球之氣化絶島陣列的使用。該種製程圖解於圖3。 圖3A中之島30乃是先利用熱蒸鍍法，在氧化矽層6上沈積 一氯化鉋薄膜，接著再將該氣化鉋膜曝需在水蒸氣中而形 成。水蒸氣會使薄膜斷裂形成島狀，這是因為其必須使表、 面自由能處在最低的狀態。接著再於該自組結構上沈積一 閘金屬層32,如圖3B所示。藉由譬如，超音波震動，可將 k佈在4等光阻島上之金屬膜去除，產生含有孔洞的閘電 極8 (圖3C)。 亦可將矽島作為奈米結構之光阻面罩。此法描述於由B.
Legrannd，v. Agache，J p都，v Sen^D 如㈣·报應用物 理信函期刊，76(22)，3271(2000)中所共同發表之論文：”以 熱回火’於絕緣基板上之石夕上，形成石夕島”中。此技術牽 涉到對氧化石夕上的石夕薄膜加熱至攝氏5〇〇至簡度。石夕島的 __ -13- 本纸張尺度適用巾g @家‘準(CNS) A4規格(21GX297公复广^ ---—— 540162
五、發明説明（11 ) 形成咸仏疋該矽/二氧化矽系 ,^ 尔兄义目由靶取小化的結果。鈥 後，再於該等矽島上兮锆兮&抵 … ,w , 沈積该閘極層。施以超音波或蝕刻， 將遠寺矽島連同該閘極層覆蓋於矽島上的部份 ，留下該閘極層中的孔洞。 ’于、 c. Haginoya，M. Ishibashi及K K〇ike於應用物理信函期刊， 71(20)，2934(1999)中所共同發矣之”以p 4 ^尸;表之以尺寸可控制自然微影 法所製之奈米結構"論文明了如何形成六角聚苯乙烯 球之陣列，此聚笨乙稀球的直徑在控制之下，以活性離子 ㈣^縮減。金屬膜沈積在陣列的之上，接著將覆著金屬 的聚苯乙烯球予以剝離，形成具有孔洞陣列之金屬膜。 近年來，於大面積上製作奈米矽柱的技術有突飛猛進的 進步，這是因為其可廣泛地應用在光電，單電子學方面並 可作為場射極。已可做出的矽柱，其直徑在5奈米至幾微 米的犯圍，高度則在丨微米。奈米矽柱亦可應用在圖丨所示 的TFT製程中，其可使該製程所製出之金屬膜具有有序的 奈米孔洞陣列。此涉及在閘介電層上沈積矽膜，並將矽膜 轉換成奈米矽柱陣列之技術。然後再沈積閘金屬，隨後以 乾或濕式蝕刻法，將該等奈米柱去除。這樣，形成在閘金 屬中之孔洞陣列其孔洞的直徑將相當於該等奈米柱的直徑 此種技術揭示於譬如’由M. Green，M. Garcia-Parajo，F.
Khaleque以及R· Murray於應用物理信函期刊63, 264-266(1993) 中所共同發表之”使用”自然”微影法於所製之n+砷化鎵上製 作量子柱結構”論文中。 -14- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 540162
〃或者是，孔洞的形成步驟包含，於該半導體膜上沈積一 第一面罩層’然後形成多個穿透該第一面罩層之孔洞。譬. 如可以下法形成孔洞··先在該第一面罩層之上，定義一 蝕刻面罩，然後蝕刻出穿透該第一面罩層之孔洞。 譬如，由 J.p· spatz，τ· Herzog，s· MyB職，p Zieniann以及 Μ· M0ller於尖端材料i i⑺，149(1999)中所共同發表之論文·· ，一種奈求微影之工具-微胞無機聚合體混合系統，，中即述 及了冑方法’品要使用摻雜的半導體材料來做間極。使 用雙團鏈塊狀共聚物之單微胞膜之自組式面罩，可以在砷 化鎵（或其他的半導體）中引入直徑為1〇奈米，排列間隔為‘· 80奈求之孔洞’藉以將合適的過渡性金屬鹽載上該等微胞 。雙團鏈塊狀共聚物面罩元件間蝕刻率的高度反差，使得 孔洞得以形《。此過程圖解於圖4中。如圖4A所示，問極 層8之上沈積了一層微胞層，該微胞層含有奈米粒子％， 其以規律性的方式配置在雙團鏈塊狀共聚物膜36中。該等 奈米粒子的材質可以是譬如，亦可是聚苯乙烯雙團鏈 塊狀共聚物。接著，使用譬如，氬束作濺擊蝕刻，在閘極 層中形成凹洞38，最終形成孔洞4〇(如圖4B和4C所示）。 · 或者是，在摻雜的半導體層上沈積均勻的六角形乳膠粒 子陣列，使用乳膠球作為活性離子阻劑，以於半導體中形 成六角形的孔洞陣列。此種技術揭示於應用物理信函期刊 ，55(14)，1433(1989)中，由 H· Fang，R· ZelledP· j 如以所共 同發表的”於砷化鎵/坤化鋁鎵異質結·構中，製作準零維度 之次微米點陣列及電容光譜儀π中。 -15- ί紙張尺度適财g S家標準(CNS) Α4規格(210 X 297公釐) -^---- 540162 A7 B7 五 發明説明（13 ) 另一種在閘電極中形成本半3丨^ u 风不木孔的技術則揭示於由Κ.
Seeger及R.E. Palmer於應用物理信函期刊，％⑴），ΐ627(·) 中所共同發表的"使用粗金屬膜作為電㈣刻罩的石夕錐及 石夕柱之製作”。當使用濺鍍法沈積銀f膜時，該薄膜的乃 長成三度空間式的銀質叢（橫向大約是2〇_4〇伽），而非一層 層的沈積。濺鏟出銀叢膜後，緊接著即加以姓刻，形成: 奈米孔洞之銀質膜，可用作為閘極材料。 以上所參考論文的全部内容在此併入以作參照。 装 習於此藝人士於閱讀本揭示後’可做出其他變體及修改 。其中可牽涉到等同物及其他設計、製造中已知之特性， 使用的電子裝置包括薄膜電路、+導體裝置及裝置中的部 件以及可用來取代此處已述之特性或另加特性之裝置。 訂 :然本申請案已針對特殊特性之組合，明確地陳述於專 利乾圍中’但應了冑’本發明之揭示範圍還包含此處所揭 不之任何新穎特性或特性的組合，無論其為顯明或隱含或 :般化’ i無論其所相關的發明是否與任一專利範圍中所 聲月的电明相同，以及無論其所解決的技術問題是否與本 發明㈣。本文中不同具體實施例中所描述的特性可同時 存在於單一具體實施例中。相對地，描述於本文中之單— 具體貫施例中的各種特性，亦可分別地提供或存在於任何 合適的次組合中。申請人藉此宣告，在本申請案或其他由 此竹生之申請案的申請期間’有可能以新的專利，明確地 陳述此種特性及/或此種特性的組合。 -16 -

Claims (1)

  1. 裝 540162
    η
    4 ·如申請專利範圍第3項 ® ΐ ^ Φ ^ ^1 ή ^ ^乃沄，其中步驟（c)在該於第一 曲罩層中蝕刻孔洞的步驟之前執行。 5 _如申請專利範圍第3 3t 4 中姓刻孔洞之步驟，在=法：其中於該第-面軍層 ，π — V驟（e)之後執行，如此使該等孔 而穿透形成於該第—面罩層之曝露區。 6 .如申請專利範圍第1、？.,, .Z、3或4項之方法，其中步驟（d) 於步驟（c)前執行，以及 . 3方法於步驟（c)之前，步驟⑷之 卜另包含下列步驟(h):圖案化該第二面罩層，以在該 第一面罩層中形成步驟（c)中圖案化該第一面罩層時所需之 裝 面罩。 7 ·如申請專利範圍第6項之古本 ., A ^ 只之方法，其中步驟（h)包含，於該 第二面罩層中定義第二圖案，之後於該第二面罩層之鄰 接處，形成側壁邊襯以定義該第一圖案。 # 8.如申請專利範圍第i、2、3或4項之方法，其中步驟⑷ 包含，於該第二面罩層上之第三面罩層中，定義該第二 圖案’氧化該第二面罩層之曝露部份，以及之後將該第 二面罩層之氧化部份去除，藉以於該第二面罩層中定義 出該第二圖案。 9 ·如申請專利範圍第1、2、3或4項之方法，其中該第一 面罩層形成一閘絕緣層，以及該第二面罩層形成一閘電 極層。 10.如申請專利範圍第第1、2、3或4項之方法，其中該第 一面罩層形成一閘電極層，以及該方法在步驟⑷之後， 步驟（b)之前，包含以下之步驟：沈積一閘絕緣層。 -2 - 本紙張尺度適用中國國家標準(CNS) A4规格(21〇 X 297公釐) u.一種包含薄膜電晶體之電子裝置，言亥薄膜電晶體包含一 於絕緣基板上之已圖案化半導體膜、_於該半導體膜上 之閘絕緣層、以及-於問絕緣層上之問電極；該半導體 膜包含源極與汲極區'一介於該源極與汲極區間之未摻 雜導電通道、以及-摻雜濃度較該汲極區為低之場緩 區，其係位於該導電通道及該汲極區之間，其中部份的 閘電極係與場缓區重疊，並具多個定義的孔洞，實質垂 直地從該閘電極之上表面延伸至該閘電極之下表面。 12.—種包含薄膜電晶體之電子裝置，該薄膜電晶體包含一 於絕緣基板上之已圖案化半導體膜、一於該半導體膜上 之閘絕緣層、以及一於閘絕緣層上之閘電極；該半導體 膜包含源極與汲極區、一介於該源極與汲極區間之未摻 雜導電通道、以及一摻雜濃度較該汲極區為低之場緩 區，其係位於該導電通道及該汲極區之間，其中部份的 閘絕緣層係與場緩區重疊，並具多個定義的孔洞，實質 垂直地從該閘電極之上表面延伸至該閘電極之下表面， 以及該閘電極係自我對齊至該導電通道。 13·如申請專利範圍第丨丨或^項之電子裝置，其中該場緩區 之長度小於1微米。 14.如申請專利範圍第u*12項之電子裝置，其中該第一面 罩層中之孔洞，將其下層曝露出約1〇/〇至10%。 15·如申請專利範圍第n*12項之電子裝置，其中孔洞的平 均值徑小於100奈米。 -3-
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