TW538660B - Method for making an electric circuit device - Google Patents

Method for making an electric circuit device Download PDF

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Publication number
TW538660B
TW538660B TW091111649A TW91111649A TW538660B TW 538660 B TW538660 B TW 538660B TW 091111649 A TW091111649 A TW 091111649A TW 91111649 A TW91111649 A TW 91111649A TW 538660 B TW538660 B TW 538660B
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TW
Taiwan
Prior art keywords
conductive
circuit device
conductive foil
manufacturing
mentioned
Prior art date
Application number
TW091111649A
Other languages
English (en)
Inventor
Yoshiyuki Kobayashi
Noriaki Sakamoto
Kouji Takahashi
Original Assignee
Sanyo Electric Co
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Publication date
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Publication of TW538660B publication Critical patent/TW538660B/zh

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • H01L21/4832Etching a temporary substrate after encapsulation process to form leads
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Description

m〇6〇 五、發明言兒明(1) 【發9月所屬 本發明 要支持基板 【習知之技 以^往, 電話、可攜 量化之·需求 例如: 一般的半導 (transfer 裝置,如第 該封裝 周圍,並由 技術領域】 路裴置之製造方法,尤其係關於 之薄型電路t置的製造方法。 術】 子機器的電路裝置由於要應用在攜帶 工电甸小型機器,故有小型化、薄型化、輕 0 二2 2電,裝置之半導體裝置為例來說明,就 ^ 而β ,具有以習知一般移送塑模 l〇i g)密封之封裝型半導體裝置。該半導體 圖所不,係安裝於印刷基板ps。 型半導體裝置係以樹脂層3覆蓋半導體晶片2的 該樹脂層3的側部導出外部連接用的引導端子 线而,該封裝型半導體裝置丨之引導端子4係由樹脂層 3向外拉出,整體尺寸很大,因而無法達成足小型化、薄 型化反輕量化。 因此’各公司為了謀求小型化、薄型化及輕量化因而 競相野發各種構造’最近開發出稱為Μ p (晶片尺寸封裝 體Ch i p Size Package )之構造,係指與晶片尺寸相同的 晶圓t寸(wafer scale) CSP或者是晶片尺寸稍大之 CSP ° 第1 9圖係採用作為支持基板的玻璃纖維環氧基板5, 表示樹大於晶片尺寸的CSP6,於此,說明安裝電晶體晶片
313712.ptd 第6頁 538660 五、發明言兒明(2) T於玻璃^•氧基板5。 在該玻璃環氧基板5上,形成第1電極?、 晶片鋒塾9,並儿在背面形成第lf面電極1()/ 面電 ㈣。而5,,,Φ貫穿孔TH,將上述 極、
電極1〇,第2電極8與第2背面電極丨丨電性連接:此弟外^在 晶片萍塾9上固揍上述一對電晶體曰H #命绝;# K 7尨人丄人^/日片T,電晶體的射極電 =:二 線12連接’電晶體的底部電極 !Γ:,由金屬細線12連接。再者,以覆蓋電晶 體曰曰片Τ之方式,在玻璃基板5上設置樹脂層13。 上述CSP6係採用玻璃環氧基板5,然而盥晶圓尺寸 (wafer SCale) CSP不同,由晶片了至外部連接用背面電 極10、 11的延伸構造很簡單,具有可廉價製造之優點。 上述CSP6如第18圖所示,係安裝於印刷基板ps。在印 刷基板PS上,設置構成電性電路之電極、配線,並且電性 連接固接CSP6、封裝型半導體裝置丨、晶片電阻cr 電容器CC等。 而且’該印刷基板構成的電路係安裝於各種器具 (set)中。 八 法 繼之,參照第2 0圖及第2 1圖,說明該c s p之製造方 貧先’準備玻璃環氧基板5作為基板(支持基板), 並在其兩面介由絕緣性連接劑壓接Cu箔2〇、2 1。(以上, 參照第20 ( A )圖) 在第1電極7、第2電極8、晶片銲墊9、第1背面電極1〇
313712.ptd 第7頁 538660 五、發明言兒明⑶ 及第2嘴面電極11對應之Cufl 20、21上,覆蓋耐抗蝕性之 抗蝕齊^ 22,於Cu諂2 〇、2 1製作圖案。尚且,圖案亦可分別 在表面與背面製作。(以上,參照第20 ( B )圖) 到用鑽頭(cin Π )或雷射,將作為貫穿孔th的孔形 成於上述玻璃環氧基板上,並於該孔上施以電鍍以形成貫 穿孔Τ Η。耩由該貝牙孔Τ Η,電性連接第1電極7與第1背面 電極1 〇、第2電極8與第2月面電極1 〇。(以上,|昭第2 〇 (c )圖)。 …. 睢然圖面未顯示,在成為銲接柱(b〇nding p〇st)之 第i電糨7、第2電極8上實施Au電鍍,同時在成為晶片銲接 柱之晶片銲塾9上實施A u電鍍’並且晶片銲接電晶體晶片 T ° 最後,介由金屬細線12連接電晶體晶片τ的射極電極 與第1電極’電晶體晶片T的底部電極及與第2電極8,並以 樹脂廢13覆蓋。(以上,參照第20 ( D )圖) 遂過以上之製造方法,完成採用支持基板5之csp型的 電性元件。該製造方法亦與採用撓性基板作為支持基板相 同。 【發明所欲解決之問題】 第1 8圖中,電晶體晶片τ、連接機構7至丨2及樹脂層j 3 與外部電丨生連接,且在電晶體的保護上係為必要的構成要 素’然而僅僅如此的構成要素在提供實現小型化、薄型 化、輕量化之電路元件是有困難的。 而且’成為支持基板之玻璃環氧基板5如上所述原本 Ι|^Η:ϋϋ 1H1 313712.ptd 第8頁 538660 五、發明彭^明⑷ ' ίI ^要。然而,因為在製造方法上需要黏接電極,所以 木二支持基板時,無法缺少該玻璃環氧基板5。 彳木用該玻璃環氧基板5時,成本增加且玻璃環氧基變 =丄故電路元件變厚,因此在小型化、薄型化、輕量化上 產生限^制。 ♦ * t破璃環氧基板或陶瓷基板中,必須連接兩面電極之 1i =成步驟係不可缺少的步驟,如此製造步驟會變長, 於I產時亦會出現問題。 叫议ΐ鐘於以上的問題’本發明人於特許2 0 0 0 — 2 6 6 73 6中 …之步=it電路裝置。然而’在覆蓋背面抗 在各答载部上進行ί銲劑電極用的開口部’需分別 認識時會有費時:口 :之位置認識,所以在實行位置 【解決:問題之方案】 本發明係繁於Ρ、+、 備:率備導電箱,在對4各問題而開發者’其特徵在具 及形成預定位置對準浐於去除形成預定導電圖案之區域 上述筝電為的厚度淺的疋=電 >自上,形成比 電圖案之上述各搭載 離溝之乂騄,在所希望之上述導 接上逃各搭载部的電,固接電路元件之步驟;電性連 之步驟;-併覆蓋各牛電極與所希望的上述導電圖幸 上述分離溝之方式以絕^ ^述電路元件,並以充填於 認識用確認孔上充填上^ ^樹脂共同塑模’同時亦在上述 電猪的背面區域至上二^緣性樹脂之步驟;去除上述導 〜性樹脂露出之步驟;並且;: 313712.ptd 第9頁 538660 五、發明說明(5) 上述電動箔的去除並經由出現於背面之上述位置對準標 記,來進行位置認識。 本發明中,形成導電圖案之導電箔係為起始 (start)的材料,至塑模絕緣性樹脂前,導電箔具有支 持功姖,而進行塑模之後絕緣性樹脂具有支持功能,據此 不需支持基板,即可解決習知之問題。於此,位置對準標 記係露出於絕緣性樹脂背面之導電箔的一部份。 各發明係鑒於上述各問題而開發者,其特徵在具備: 準備導^電猪’在對應於去除形成預定導電圖案之區域及形 成預定位置對準摞記之區域的上述導電箔上,形成比上述 導電箔的厚度淺的分離溝之步驟;在所希望之上述導電圖 案之上述各搭載部上,固接電路元件之步驟;電性連接上 述各答載部的電路元件電極與所希望的上述導電圖案之步 驟;一併覆蓋各搭載部的上述電路元件,並以充填於上述 分離蓉之方式以絕緣性樹脂共同塑模,同時亦在上述認識 用確認孔上充填上述絕緣性樹脂之步驟;去除上述導電箔 的背面區域至上述絕緣性樹脂露出之步驟;並且藉由上述 電動箔的去除並經由出現於背面之上述位置對準標記,來 進行位置認識。 各發明電路裝置之製造方法,其特徵在於:藉由上述 位置對準標誌間接認識背面之上述導電圖案的位置,在上 述導電圖案上保留用以形成預定背面電極之開口部並以抗 蚀劑層覆蓋。 再者,本發明電路裝置之製造方法,其特徵在於:在
313712.ptd 第10頁 538660 五、發明言兒明(6) 上述抗^蝕劑層的開口部附著導電機構以形成背面電極。 ;^發明電路裝置之製造方法,其特徵在於:藉由上述 位置針準標誌間接認識背面之上述導電圖案的位置並進行 切割(a i c i n g) ο ;^發明電路裝置之製造方法,其特徵在於:藉由上述 位置對準標誌間接認識背面電極的位置並測定上述電路元 件的待性。 ;^發明電路裝置之製造方法,其特徵在於:上述導電 箔係以銅、鋁或鐵鎳之任一樣為主材料而構成者。 本發明電路裝置之製造方法,其特徵在於:至少以導 電皮膜部分的覆蓋上述導電箔表面。 ;^發明電路裝置之製造方法,其特徵在於··上述導電 被膜像以鎳、金、銀或鐘把形成者。 ;^發明電路裝置之製造方法,其特徵在於:選擇的形 成於上^述導電箔之上述分離溝係以化學或物理的方式去 除。 本^發明電路裝置之製造方法,其特徵在於:上述電路 元件傣固接裸晶片、晶片電路零件之任一或者兩者皆固 接。 木發明電路裝置之製造方法,其特徵在於:上述絕緣 性樹脂係以移送塑模共同塑模於上述各方塊上。 衣發明電路裝置之製造方法,其特徵在於:將至少於 上述導電箔上形成多數個電路元件搭載部之導電圖案,排 列為矩陣狀之方塊排列多數個。
313712.ptd 第11頁 538660 五、發明說明(7) 本發明電路裝置之製造方法,其特徵在於:上述絕緣 性樹脂係將上述導電1¾的上述方塊全部同時進4于移送塑才吴 而形成者。 本發明電路裝置之製造方法,其特徵在於:上述位置 對應標記位於上述導電箔之上述方塊外部,係為露出於上 述導電猪背面之上述絕緣性樹脂。 木發明電路裝置之製造方法,其特徵在於:上述位置 對應標記設置於上述導電箔的周邊。 木發明電路裝置之製造方法,其特徵在於:上述位置 對應標記位於上述導電箔之上述方塊内部,係為露出於上 述導電箔背面之上述導電箔。 衣發明電路裝置之製造方法,其特徵在於:上述位置 對應標記位於上述導電箔方塊的内部係為露出於上述導電 箔的内侧之上述絕緣性樹脂,而上述絕緣性樹脂露出於上 述絕緣樹脂背面。 各發明電路裝置之製造方法,其特徵在於:露出於上 述各方塊之上述絕緣性樹脂背面的上述導電圖案位置認 識,係藉由上述位置對準標記來進行。 衣發明電路裝置之製造方法,其特徵在於··露出於上 述導電箔整體的上述絕緣性樹脂背面之上述導電圖案的位 置認識,係藉由上述位置對準標記來進行。 【發明之實施型態】 貧先,參照第1圖說明本發明電路裝置之製造方法。 衣發明具備下列步驟··準備導電箔,在對應於去除形
313712.ptd 第12頁 538660 五、發明說明(8) 成預定導電圖案的區域及形成預定位置 上述導電箱上,形成比上述導電落厚度還淺二分2域的 驟;在所希望的上述導電圖案之上述各搭 刀離溝之步 路元侏之步驟;連線銲接上述各搭载部;電路侏=接電 與所希望的上述導電圖案之步驟;件的電極 路元件之電極’以充填於上述分離溝之方;電 脂共同塑模’同時亦在上述認識用的確認孔上 緣性紂脂之步驟;去除上述導電簿的背面全 it,絕 性樹脂露出之步驟;藉由上述位置對準標記,間 形成預定之背面電極的開口部並以抗兹劑層覆蓋 於上逖湖層的開口部附著銲劑(solder r :電 方塊之各搭載部的上述電子元件特性之步驟;在』 述黏接片的狀態下,將上述方塊絕各 載部分割之步驟。 細ί尤各搭 於第1圖所不之流程圖中,首先進行準備Cu箔之步 私、A g電鍍之步騾與半蝕刻等三項流程以形成導電圖案。 晶片揍合及連線銲接2個步驟係指:使電路元件固接於各 搭載邨及連接電路元件的電極與導電圖案。移送塑模步驟 係^ ·以絕緣性樹脂的共同塑模。該共同塑模係指:將設 ^複婁^搭載部的方塊使用i個鑄模窩穴(c a v丨t y )來進行塑 板、。背面Cu辖去除步驟係指:蝕刻上述導電箔的背面直至 上述絕緣樹脂露出為止。背面抗蝕劑的步驟係指:於露出 313712.ptd 第13頁 五、發明說明(9) 於絕緣性樹脂背面的、酋命 極形成的步驟係指:¥二圖案上,形成抗蝕劑層。背面電 電圖案的背面電杨。^著貧狀的銲劑並且加融化以形成導 數方魄。測定步驛係^接片步驟係指:於黏接片上貼合複 元件的良品判斷或特' 日:進行裝置於各電路襞置部之電路 方式使各個電路袁曹11等級區分。切割步驟係指:以切割 以下,參照第2图由絕緣性樹脂分離。 各發明第1步驟二至,17圖,說明本發明各步驟。 6 0,至少於與去除多糸如第2圖至第4圖所示,準備導電箔 51的區域及位置對數开v成電路元件52搭載部之導電圖案 比導電猪60的厚度ΐ標記相對應之區域導電箱60上,形成 圖案51。 枣火的分離溝61,並形成各方塊的導電 本步驟中,首先 ^ 箔60。選擇該導電&,第2 ( A )圖所示,準備板狀的導電 性、電鍍性,就材=〇 =應考慮到銲劑的附著性、接合 镇、以A1為主材料的。;=用以Cu為主材料的導電 箔等。 電,自或FeNl專合金所構成的導電 至3。0因/二=的钕刻’故該導電猪的厚度係以1… 亦可 _ 、在此係採用125#πι的銅箔。然而,基本上 電笔6 0 Μ /二2上1 〇 " m以下。如後詳述,亦可形成比導 電v自6 0的厗度逛淺的分離溝6 i。 尚且’片狀的導電箔60捲曲為預定的寬度,例如: 45mm的捲狀,此亦可於後述各步驟中進行搬送,又,準備 切成預定的大小之長矩形狀的導電箔6〇,於後述之各步驟 538660 五、發明說明(ίο) 搬送亦可。 具體而言,如第2(B)圖所示,於長矩形狀的導電箔 6 0上並列有4至5個相分離且形成多數搭載部的方塊6 2。在 各方魄62之間設有間隙6 3。該間隙具有吸收塑模步驟等加 熱處理時所產生之導電箔6 0的應力之作用。此外,於導電 箔60的上下端上以預定間隔設有標記(index )孔64,使 用於各步驟的位置決定。 繼之,具有形成各方塊的導電圖案51之步驟。 貧先,如第3圖所示,於 C U箔6 0上形成光阻劑(耐抗 蝕遮罩)PR,並以露出成為導電圖案51區域的導電箔60之 方式,將光阻劑PR作成圖案。而且,如第4(A)圖所示, 介由光阻劑PR選擇的蝕刻導電箔60。 以#刻所形成之分離溝6 1的深度係如5 0 /z m,而且該 側面為了成為粗面可提升與絕緣性樹脂5 0的黏接性。 又,該分離溝6 1的側壁係以直線(s t r a i g h t )模式的 圖示,而經由去除方式而成為不同的構造。該去除步驟可 採用濕蝕刻、乾蝕刻、藉由雷射之蒸發、切割。進行濕蝕 刻時,主要係採用氯化第二鐵或氯化第二銅作為蝕刻劑, 上述導電箔係在該該蝕刻劑中浸潰,或者以該錄刻劑進行 喷淋。於此,濕蝕刻一般係為非異向性蝕刻,所以側面成 為彎曲構造。 尚且,第3圖中,亦可選擇性的覆蓋對蝕刻液具抗蝕 性之導電被膜(無圖示)來替代光阻劑。若在成為導電路 的部分選擇性的覆著,則該導電被膜會成為蝕刻保護膜,
313712.ptd 第15頁 538660 五、發明說明(11) 該導電被膜的材料 些抗钱性的導電被 徵。 黏接。因此,若在 的Ag被膜上可熱壓 片。又,在Ag導電 焊接。因此,具有 塾之優點。 5 1。本圖係對應於 『、的1個部分係表示 方塊6 2上排列有5 各搭载部6 5上設置 置框狀的圖案6 6, 對準標記6 7。使用 為與上鑄模的抵接 不須採用抗蝕劑即可蝕刻分離溝。 係有Ag、Ni、Au、Pt或Pd等。而且,、言 膜具有可活用作為晶片銲墊、銲墊的^ 例如:Ag被膜與Au黏接,亦與銲劑 晶片背面覆蓋Au被膜,則在該導電路51 接晶片,並且介由銲劑等銲劑可固接晶 被膜上黏接Au細鎳,所以亦可進行連線 可將這些導電被骐活用為晶片銲墊、銲 ,4(B)圖孫表示具體的導電圖案 放大第2 ( B )圖所示之1個方塊6 2。塗, 1個搭载部65’構成導電圖案η,於1個 列1 〇行之矩陣狀的多數搭載部6 5,並在 相同的導電圖案51。在各方塊的周邊設 並在稱微分離的内側設置切割時的位置 框狀的圖案6 6作為塑模鑄模,尤其是作 部分而使用。 又,如第4 C β )圖所示,在標記孔6 4附近設有於背面 抗餘齊J覆蓋時使用之位置認識的確認孔1 〇 〇。 第4(C)圖係為第4(B) A-Α線之剖視圖,確認孔i 〇〇 於形成分離溝6 1之同時設置,具有大致相等的深度,而且 於背面抗蝕劑覆蓋步驟中,間接使用於背面導電圖 置認識。 ”的位 私發明第2步驟係如第5圖所示,在所希望之導電 5 1的各搭載部6 5上固接電路元件52,並形成電性連接:二 538660 五、發明說明(12) 載部65之電路元件52的電極與所希望之導電圖案5 4* 八丄的連 機構 接 就電路元件5 2而言,具有電晶體 極體 ic晶片辇 半導體元件、晶片電容器、晶片電阻等被動元件。又,寻 可安裝面朝下(facedown )的半導體元件、與進行CSp亦 BGA等封裝處理的半導體元件。 ' 於此,將裸電晶體晶片52A係晶片銲接於導電圖案 上,紂極電極與導電圖案5 1 B、底部電極與導電圖案f 5 U 介由以球接合或超音波所產生之楔形接合等固接的金屬名' 線5 5A連接。又,52B係為晶片電容器或被動元林, 細 劑等銲劑或導電膨55B固接。 泰步驟係於各方塊6 2上積體多數的導電圖案5 1,所γ 具有可非常高效率的進行電路元件5 2的固接及連線焊接Χ 優點。 之 衣發明之第3步驟,係如第6圖所示,一併覆蓋各搭、 部63的電路元件52,並以可充填於分離溝61之方式以^ $ 性樹脂50共同塑膜。 % % 衣步驟如第6 ( A )圖所示,絕緣性樹脂5 0完全覆蓋 路元件52A、52B及複數導電圖案51A、51B、51C,並與"於 導電圖案5 1之間的分離溝6 1充填有絕緣性樹脂5 〇之導電圖 案5 1 A、51 B、5 1 C的側片彎曲構造嵌合且強固結合。且/ 藉由絕緣性樹脂5 0支持導電圖案51。 此外,本步驟可藉由移送塑模、射出塑膜或浸潰來實 現。就樹脂材料而言,環氧樹脂等的熱硬化性樹脂可利用 ΪΗΙ 313712.ptd $ 17頁 538660 五、發明說明(13) 移送塑膜來實現,而且聚醯 樹脂可利用射出塑骐來實現 各步驟中進行移送^膜 所示,1個塑膜鑄模的槽中 脂5 0進行共同塑骐。因9此, 塑模,並且以利用樞架圖案 案’形成禮封區域。因此, 各搭载部之方法相比較,樹 多樹脂量。 各步驟中,塑模鑄模不 塑模方塊’所以與作成電路 同使用塑模鑄模。 亞胺樹脂、聚笨硫等熱可塑性 〇 或射出塑膜時,如第6圖(B) 在各個方塊上以1個絕緣性樹 各方塊6 2係以1個鑄模進行1次 6抵接之上轉模的槽與導電圖 1如習知移送塑模等分別塑模 月曰流道的數量較少且可減少許 僅塑模各個搭載部,而且共同 元件的種類或大小無關,可共 覆蓋於導電謂60表面之絕緣性樹脂5〇的厚度,係以由 電路元件52的金屬細線55A的最頂部覆蓋1〇〇// m左右之方 式來調整。可考慮強度而將厚度變厚或變薄。 衣步驟的特徵係:至覆蓋絕緣性樹脂5 〇的步驟中,成 為導電圖案51之導電箱60係為支持基板。以往如第19圖所 示,係採用原本沒有必須之支持基板5形成導電路7至1 1, 然而,本發明中,作為支持基板的導電箔60就電極材料而 言,係為必須材料。因此,具有可大幅節省構成材料來進 行作業之優點且亦可降低成本。 因為分離溝61比導電箔的厚度還淺,所以導電箔6 〇不 會各自分離為導電圖案。因此,可一體處理板狀的導電箔 6 0,並且在進行絕緣性樹脂5 0之塑模時,具有非常容易進
313712.ptd 第18頁 538660 五、發明說明(14) 行鑄模的搬送、安裝作業之特徵。 各步驟中的另一重點係一併進行複數電路元件之塑 模,所以不會發生將電路元件時個別塑模所發生之樹脂毛 邊的問題。 此外,第6 ( C )圖係第6 ( B )圖之A-A線的剖視圖, 本步驟中確認孔1 0 0亦進行塑模,可充填絕緣性樹脂5 0。 各發明之第4步驟,如第7(A) 、 (B)圖所示,去除 導電箔6 0背面全部區域至露出絕緣述樹脂為止。 衣步驟係化學的/物理的去除導電箔6 0的背面全域, 並分離為導電圖案5 1。該步驟可藉由研磨、研削、蝕刻、 雷射的金屬蒸發等來施行。 實驗中,全面濕蝕刻導電箔60,且由分離溝6 1露出絕 緣性樹脂5 0。結果,成為約4 0 // m厚度的導電圖案而分 離。 如第7 ( B )圖所示,本步驟中充填於確認孔1 0 0的絕 緣性樹脂5 0亦為露出於背面之構造,並於背面抗蝕劑覆蓋 步驟中,為了間接進行背面導電圖案5 1的位置認識,而使 用為位置對準標記1 0 1。 各發明第5步驟係如第8圖至第11圖所示,在露出導電 箔6 0的絕緣性樹脂5 0的背面之導電圖案5 1上覆蓋抗蝕劑層 9 0,並以露出預定背面電極5 6之方式形成開口部9 2。 第8 ( A )圖孫為了表示背面抗蝕劑的開口部9 2與導電 圖案5 1的關係,塗黑的部分表示導電圖案5 1,去白的圓印 表示背面抗蝕劑的開口部9 2。然而,實際上背面抗蝕劑的
313712.ptd 第19頁 538660
五、發明言兒明(15) 開口部9 2以外的方塊6 2为面’係以抗姓劑層g 〇覆蓋。 各步驟中’如第8 ( A )圖所示,藉由二置對^標記 101’間接進行露出於背面之導電圖案51的位置認識,並 在導電圖案51上保留形成預定背面電極56的開口部92,並 以抗缺劍層9 0覆蓋。 於此’就認識露出於背面之導電圖案的標記而言,亦 可考慮採用引導孔64。然而,在背面Cu去除步驟中蝕刻導 電箱6 0的背面整面,所以亦會蚀刻引導孔64的内壁,並在 =外從或位置產生誤差。因此,引導孔64在露出於背面之 ^電V白的位置認識使用。據此,本發明採用露出於導電箔 背面周邊部之絕緣性樹脂1 0 1,來作為位置確認用標記。/ 一 因為位置對準標記1 〇 1係於與搭載部6 5的分離溝6 1相 同之方^法所形成之確認孔1 〇 〇中充填絕緣性樹脂而形成 =,所以在背面Cufl去除步驟中,如第8 ( B )圖所示,係 露出^於背面。本步驟中,位置對準標記1 〇丨形成圓形,然 而若為位置認識用照相機可認識的形狀時,亦可以是圓形 以外的形狀。 、 疼體而言,最初係在導電箔60各方塊62的背面整體施 以網板印刷,並施行輥式塗鍍設備(rol 1 coat er )或靜 $塗市來進行抗蝕劑層9 0的覆蓋。據此,藉由導電圖案5 1 或抗飯劑層9 0完全覆蓋,且因為抗蝕劑層9 0並#透明,所 X欲复接進行導電圖案的位置認識是有困難的。 斤 一 Μ之’進行導電圖案51的位置認識。如第8(A)这 不,位置對準標記丄〇丨係露出於沒有形成導電圖案5 1之
538660 五、發明說明(16) 電猪6 0周邊殘餘 進行根據抗餘劑 絕緣性樹脂與導 大,所以可明白 又,比較導電箔 此,經由正確認 各方塊或各導電 繼之,如第 5 6之開口部9 2上 藉由光抗蝕劑1〇 開口邨92。該抗 染,同時亦決定 抗蝕劑層9 0 102 ° 據1此,本步 塊或备導電箔背 之背面抗鍅劑。 部的背面,所以如第8 ( B )圖所示,沒 層9 0之覆蓋。位置對準標記丨〇 i的材料& 電箔60的材料cu,其光的反射率差異很 的進行位置對準標記1 〇丨輪廓之區別、。、 6〇與陶瓷基板等,尺寸精確度較高。因 識位置對準標記101的位置,可間接認識 箱之導電圖案5 1的位置。 9/( A )圖所示,在保留形成預定背面電極 形成光抗蝕劑1 〇 2。如第9 ( B )圖所示, 2選擇性的蝕刻覆蓋之抗蝕劑層9〇以形成 襁劑層90保護導電圖案51免於氧化或污 所形成之背面電極5 6的大小。 的材料為感光性材料時,不需要光抗蝕劑 騾:可利用一次的位置認識連續進行各方 面抗蝕劑之覆蓋,所以可形成將時間短縮 上Ϊί步驟的說明中,使用露出於導電猪方塊的外側 背面之:邑緣性樹脂101作為位置對準標記,以進行露出於
背面之導電圖案的位置認識。铁 么给彳η卸α ^ 添而,如第1 0圖所示,亦有 使用於方塊内部沒有設置導雷园安> Μ 丄 L當+ ΛΜ 夏^ ^圖案之絕緣性樹脂背面所露 出的V電、治1 1 0作為位置對準標記之方法。 如1第11圖所示,亦有传用^ αλ. , , 0 ^ 3便用於導電箔1 11内部所露出之 導電箔Π 2作為位置對準桿泞$古1 ^ 知°己之方法,而該導電箔1 1 1係露
538660 五、發明說明(17) 出於方塊内部沒有設置導電圖案之絕緣性樹脂背面。 尚且,本發明為了形成銲劑電極用的開口部,藉由位 置對準摞記進行淤背面露出之導電圖案的位置認識。然 而,當位置對準檑記設置於方塊内部時,使用該位置對準 標記並在後續的步驟中進行導電箔或銲劑電極之間接的位 置認識。例如:渕定步驟中,可在藉由位置對準標記進行 方塊6 2内全部背面電極的位置認識之後再實施側定。此 外,在切割步驟中,藉由位置對準標記進行方塊6 2内全部 背面電極5 6的位置認識之後再實施切割。 本發明第6步驟,係如第1 2 ( A ) ( B )圖所示,將膏 狀的焊劑9 1藉由網板印刷相同大小地附著於包含開口部9 2 之其周邊的抗蝕劑層9 0上。 木步驟中,就膏狀的銲劑9 1而言,可使用以有機溶劑 混合焊劑粒子的銲劑膏。如第1 2 ( A )圖所示,因為膏狀 的銲劑9 1係由開口部9 2大大地附著,所以可作業性良好地 附著於各方塊62之全部的搭載部65的開口部92上。 泰步驟中,如第1 2 ( B )圖所示,使各方塊6 2通過流 通氮氣的加熱爐,並且加熱熔化膏狀的銲劑9 1以形成背面 電極5 6。因為背面電極5 6預先附著相同大小的開口部9 2與 相同大小的膏狀銲劑9 1,所以全部形成均一的大小。 因此,進行後述之切割步驟後,可獲致第1 4圖所示之 最終構造。本發明電路裝置5 3係如第1 8圖所示之習知背面 電極1 0、11沒有設置段差,所以晶圓固定時具有因銲劑等 的表面張力可向水平方向移動而可施行自動對準之特徵。
313712.ptd 第22頁 538660 五、發明言兒明(18) 本步驟中,如第13圖所示,藉由具有開口部之位置確 認用坑蝕劑1 2 1 A、1 2 1 B,間接進行背面抗蝕劑開口部的位 置確認。 具體而言,最初,背面覆蓋步驟中,在導電箔背面的 方塊外部,設置具有開口部1 1 2A、1 1 2B之位置確認用的抗 餘劑 121A、121B。 繼之,以位置確認用照相機,來認識位置確認用抗蝕 劑1 2 1 A、1 2 1 B的開口部1 1 2 A、1 1 2B,以固定導電箔6 0。 最後,於與抗蝕劑開口部1 1 2A、1 1 2B相同位置上,使 用具有開口部之半導體印刷金屬網板(無圖示)進行銲劑 印刷。 從進行位置確認之2個抗蝕劑1 2 1 A、1 2 1 B至導電箔6 0 中心線1 3 0的距離之d 1、d 2係為不同。因此,上述步驟 中,將外框相反固定時,在與所希望的位置大幅分離之處 進行網板印刷,可容易進行本步驟之不良判定。 尚且,本步驟的說明中,位置確認用的抗钱劑係設置 於導電箔6 0長度方向的兩端部附近,然而位置確認用的抗 蝕劑亦可設置於寬度方向的端部附近。 根據上述步驟,進行使用位置確認用抗蝕劑之銲劑印 刷。 衣發明第7步驟,如第1 5圖所示,係將複數個方塊6 2 的絕緣性樹脂貼合於黏接片8 0。 進行導電箔60的背面蝕刻之後,將各方塊6 2從導電箔 6 0切離。因為該方塊6 2係以絕緣性樹脂5 0與導電箔6 0的殘
313712.ptd 第23頁 538660 五、發明說明(19) 餘部連結,所以無須使用切斷鑄模即 殘餘部分離。 衣步驟中,將黏接片80的周邊貼 屬框81 ’並且在泰接片8〇的中央部分 62時刀片不會觸碰之間隔,使絕緣性 雖可便用UV板作為黏接片8〇,惟因為 脂而具有機械強度,所以亦可使用便 表發明第8步驟,如第16圖所示 的狀態下,以絕緣性樹脂50 —併進行 搭載部65的電路元件52之測定。 此各方塊62的背面,如第16圖所示 二=電極56,亚且各搭载部65與導電 二ηίΓ車狀。將探針68抵接由該 2主 背面電極56, *別測定 Π性參數以進行不良判定,並且 油墨#打標印。 第16圖中為ύ矣— 塗里的邻八I 表不背面電極56與 示導電圖案51,去白的 5 6 ’然而,實際上導 9 0覆蓋。 圖案5 1開口部 可達成從導電萡6〇的 合於不銹製的環狀金 ’區隔切割4個方塊 樹脂5 0抵接而點貼。 各方塊6 2以絕緣性樹 宜的切割片。 ,在貼合於黏接片8 0 已塑模之各方塊62各 ’路出導電圖案51的 圖案51形成時完全同 導電圖案5 1的絕緣性 各搭載部65電路元件 在不良品上進行磁性 導電圖案5 1的關係, 圓印表示背面電極 92以外係以抗蝕劑層 置5 3係以絕緣性樹脂 地分離。因此,可將 著於测試器 應搭載部65尺寸之程 本^步驟中,久# 5〇 —體支持於方^载。Μ5的電路裝 貼合於勒技μ、方塊62,所以不會散亂 (teSter)二80的複數方塊62真空吸 的載置台。在各方塊上對
538660 五、發明言兒明(20) 度,間距傳送於箭頭所示 ^ 快速且*大量進行方塊62各搭、截=^ 方向,藉此,可極 亦即,因為不需習知必要^邛、電路裝置53之测定。 極位I的認識等,更可同二路裝置表面背面的判別、電 縮短测定時間。 ]4處理複數方塊62,所以可大巾^ 睢然本步驟在進行切 性的測定,然而本發明“ρς =路j置前先進行特 合於基板的狀態,所以切姓電路震置亦為貼 各發明第9步驟,係乂 ]第,;灸圖再所實施特/的測定亦可。 8 0的狀態下,藉由切宝j將 回 不在貼合於黏接片 搭載部65。 j將方塊62的絕緣性樹脂50分離至片各 衣步驟中,將貼人 於切割裝置的載置台,並以七=80的稷數^塊6 2真空吸著 的切割線,切割分離溝6 = σ,刀片6 9沿著各搭载部6 5間 裝置53。 刀離溝61的絕緣性樹脂5〇並分離至各電路 =步驟中,切割刀片69完全切斷絕 割至黏接片表面的切削 深注W月曰5 0,並切 至各塔载部65。遠= 樹脂5 00完全分離 設置之各方塊周邊框狀^ ^ ^識上述第1步驟中 以此為基準來進行切割。眾所❹ 己67, 完全的切割後,再使載f A M Qn # 係於縱方向進行 割。 更載置台疑轉90度以進行橫方向的切 再者,本步騾中,切割線7〇上存 絕緣'!·生樹脂50與抗钱㈣9Q,所之 乃的耗才貝 313712.ptd 第25頁 538660 五、發明說明(21) 少,且不易發生金屬毛邊而可切割為極正確的外形之特 徵。 即使在本步驟實施後,進行切割之後由於黏接片8 0的 功能所以不會散亂分離至各電路裝置,亦可高效率地進行 之後的浸潰作業。亦即,一體支持於黏接片8 0的電路裝置 僅認識良品,並可利用吸著吸具收納在傳送帶的收納孔上 使其不會從黏接片8 0脫離。因此,即使是微小的電路裝 置,至浸潰步驟為止之前散亂分離的情形一次也不會發 【發明之效果】 本發明中,使成為導電圖案材料之導電箔本身發揮為 支持基板之功能,且形成分離溝時或者電路元件的安裝、 絕緣性樹脂的覆蓋時,係以導電箔支持整體,此外,將導 電箔分離為各導電圖案時,使絕緣性樹脂發揮支持基板之 功能。因此,可利用所需最小限度之電路元件、導電箔、 絕緣性樹脂來製造。如習知例之說明,在構成原本電路裝 置上,不需支持基板亦可降低成本。此外,藉由不需要支 持基板,導電圖案埋入於絕緣性樹脂,並且可調整絕緣性 樹脂與導電薄的厚度,具有得以形成非常薄的電路裝置之 優點。 此外,於本發明之背面Cu箔去除步驟中蝕刻引導孔, 所以弓I導孔的尺寸或位置的精確度較低,於背面抗蝕劑覆 蓋步驟中使用引導孔作為位置對準標記是很難的。於此, 本發明係於半蝕刻步驟中形成確認孔,並於塑模步驟中將
313712.ptd 第26頁 538660 五、發明說明(22) 絕緣彳生樹脂封入 露出於Cu箔背面 可將位置對準標 才象此,於本 認識上述之位置 行露出於背面之 位置言忍識,可在 成預定背面電極 現縮短時間之製 此*外,就位 出於絕緣性樹脂 言己而言,亦有使 性樹脂之方法, 面。亦可藉由這 確認孔, 之絕緣性 記以預定 發明之背 對準標記 導電圖案 各方塊或 之開口部 造方法。 置對準標 背面的導 用方塊内 且上述導 2種方法, 且,背面Cu箔去除步驟中係採用 樹脂作為位置對準標記。因此, 尺寸形成於預定的位置。 面抗蝕劑覆蓋步驟中,藉由位置 ,可間接於各方塊或各導電箔進 的位置認識。此外,藉由1次的 各導電箔之導電圖案上,保留形 ,以形成抗#劑層。因此,可實 記而言,亦有使用方塊内部中露 電箔之方法。又,就位置對準標 部中露出於導電箔的内部的絕緣 電箔内部係露出於絕緣性樹脂背 獲致與上述效果相同之效果。
313712.ptd 第27頁 538660 圖式簡單說明 【圖面之簡單說明】 第1圖係說明本發明之製造流程圖。 第2圖係說明本發明電路裝置之製造方法的圖< 第3圖係說明本發明電路裝置之製造方法的圖< 第4圖係說明本發明電路裝置之製造方法的圖< 第5圖係說明本發明電路裝置之製造方法的圖< 第6圖係說明本發明電路裝置之製造方法的圖< 第7圖係說明本發明電路裝置之製造方法的圖< 第8圖係說明本發明電路裝置之製造方法的圖< 第9圖係說明本發明電路裝置之製造方法的圖< 第1 0圖係說明本發明電路裝置之製造方法的圖 第11圖係說明本發明電路裝置之製造方法的圖 第1 2圖係說明本發明電路裝置之製造方法的圖 第1 3圖係說明本發明電路裝置之製造方法的圖 第1 4圖係說明本發明電路裝置之製造方法的圖 第1 5圖係說明本發明電路裝置之製造方法的圖 第1 6圖係說明本發明電路裝置之製造方法的圖 第1 7圖係說明本發明電路裝置之製造方法的圖 第1 8圖係說明習知電路裝置之安裝構造的圖。 第1 9圖係說明習知電路裝置之圖。 第20圖係說明習知電路裝置之製造方法的圖。 第2 1圖係說明習知電路裝置之製造流程的圖。 【元件符號說明】 50 絕緣性樹脂
313712.ptd 第28頁 538660 圖式簡單說明 51 導電圖案 5 2 電路元件 53 電路裝置 6 1 分離溝 6 2 方塊 8 0 黏接片 9 0 抗ϋ劑層 101 位置對準標記
313712.ptd 第29頁

Claims (1)

  1. 538660 六、申請專利範圍 1· 一種電路裝置之製造方法,具備下列之步驟:準備導 電箔,在對應於去除形成預定導電圖案之區域及形成 預定位置對準標記之區域的上述導電箔上,形成比上 述導電箔的厚度淺的分離溝之步驟; 在所希望之上述導電圖案之上述各搭載部上,固 接電路元件之步驟; 電性連接上述各搭載部的電路元件電極與所希望 的上述導電圖案之步驟; 一併覆蓋各搭載部的上述電路元件,並以充填於 上述分離溝之方式以絕緣性樹脂共同塑模,同時亦在 上述認識用確認孔上充填上述絕緣性樹脂之步驟; 去除上述導電箔的背面區域至上述絕緣性樹脂露 出之步驟;並且 藉由上述導電箔的去除並經由出現於背面之上述 位置對準標記,來進行位置認識。 2· —種電路裝置之製造方法,具備下列之步驟:準備導 電箔,在對應於去除形成 預定導電圖案之區域及形成預定位置對準標記之 區域的上述導電箔上,形成比上述導電箔的厚度淺的 分離溝之步驟; 在所希望之上述導電圖案之上述各搭載部上,固 接電路元件之步驟; 電性連接上述各搭載部的電路元件電極與所希望 的上述導電圖案之步驟;
    313712.ptd 第30頁 538660 六、申請專利範圍 一併覆蓋各搭載部的上述電路元件,並以充填於 上述分離溝之方式以絕緣性樹脂共同塑模,同時亦在 上述認識用確認孔上充填上述絕緣性樹脂之步驟; 去除上述導電箔的背面區域至上述絕緣性樹脂露 出之步驟;並且 藉由上述導電箔的去除並經由出現於背面之上述 位置對準標記,來進行位置認識。 3·如申請專利範圍第1或2項之電路裝置的製造方法,其 中,藉由上述位置對準標誌間接認識背面之上述導電 圖案的位置,在上述導電圖案上保留用以形成預定背 面電極之開口部並以抗蝕劑層覆蓋。 4·如申請專利範圍第1或2項之電路裝置的製造方法,其 中,在上述抗蝕劑層的開口部附著導電機構以形成背 面電極。 5·如申請專利範圍第1或2項之電路裝置的製造方法,其 中,藉由上述位置對準標誌間接認識背面之上述導電 圖案的位置並進行切割。 6·如申請專利範圍第1或2項之電路裝置的製造方法,其 中,藉由上述位置對準標誌間接認識背面電極的位置 並測定上述電路元件的特性。 7.如申請專利範圍第1或2項之電路裝置的製造方法,其 中,上述導電箔係以銅、鋁或鐵鎳之任一樣為主材料 而才冓成者。 8·如申請專利範圍第1或2項之電路裝置的製造方法,其
    313712.ptd 第31頁 538660 六、申請專利範圍 中,至少 9 ·如申請專 中,上述 1 0 ·如申請申 ,其中, 化學或物 1 1.如中請專 中 任 上述 樣或 1 2 ·如申請專 中,上述 方土兔上。 1 3 ·如申請專 中,複數 上述之導 電路元件 1 4.如申請專 ,上述絕 時進行移 1 5 .如中請專 上述位置 係為露出 1 6.如中請專 上述位置 以導電皮膜部分的覆蓋上述導電箔表面。 利範圍第1或2項之電路裝置的製造方法,其 導電被膜係以鎳、金、銀或鍍鈀形成者。 請專利範圍第1或2項之電路裝置的製造方法 選擇的形成於上述導電箔之上述分離溝係以 理的方式去除。 利範圍第1或2項之電路裝置的製造方法,其 電路元件係固接一對晶片、晶片電路零件之 者兩者皆固接。 利範圍第1或2項之電路裝置的製造方法,其 絕緣性樹脂係以移送塑模共同塑模於上述各 利範圍第1或2項之電路裝置的製造方法,其 並列有使導電圖案排列為矩陣狀之方塊,而 電圖案係為至少於上述導電箔上形成多數之 搭載部之導電圖案。 利範圍第13項之電路裝置的製造方法,其中 緣性樹脂係將上述導電箔的上述方塊全部同 送塑模而形成者。 利範圍第1項之電路裝置的製造方法,其中, 對應標記位於上述導電箔之上述方塊外部, 於上述導電箔背面之上述絕緣性樹脂。 利範圍第1項之電路裝置的製造方法,其中, 對應標記設置於上述導電箔的周邊。
    313712.ptd 第32頁 538660 六、申請專利範圍 1 7 .如申請專 上述位置 係為露出 1 8 ·如申請專 上述位置 出方t上述 緣个生樹脂 1 9 .如申請專 中,露出 導電圖案 〇 2 0 .如專利範 露出於上 導電圖案 行〇 %: 利範圍第1項之電路裝置的製造方法5 對應標記位於上述導電箔之上述方塊 於上述導電箔背面之上述導電箔。 利範圍第1項之電路裝置的製造方法, 對應標記位於上述導電箔方塊的内部 導電箔的内側之上述絕緣性樹脂,而 露出於上述^絕緣樹脂背面。 利範圍第if2項之電路裝置的製造方 於上述各尤棒之上述絕緣性樹脂背面 位置認識,係藉由上述位置對準標記 圍第·_項之電路裝置的製造方法, 述導着爹整體的上述絕緣性樹脂背面 的位置蠢識,係藉由上述位置對準標 其中, 内部, 其中, 係為露 上述絕 法,其 的上述 來進行 其中, 之上述 記來進
    313712.ptd 第33頁
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