TW521356B - Method of manufacturing IC device packages - Google Patents

Method of manufacturing IC device packages Download PDF

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Publication number
TW521356B
TW521356B TW089121960A TW89121960A TW521356B TW 521356 B TW521356 B TW 521356B TW 089121960 A TW089121960 A TW 089121960A TW 89121960 A TW89121960 A TW 89121960A TW 521356 B TW521356 B TW 521356B
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Taiwan
Prior art keywords
wafer
substrate
thinning
chip
thickness
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TW089121960A
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English (en)
Inventor
Yinon Degani
Thomas D Dudderar
King L Tai
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Lucent Technologies Inc
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Publication of TW521356B publication Critical patent/TW521356B/zh

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Description

A7
本發明係關於具有降低高度的積體電路封裝件，尤其係 關=覆晶封裝件，於該封裝件中—個或多個Ic組件之厚度 係藉由背側減薄的方式減低。 由於裝置-致的達到未曾有過之縮小尺切及更高程度 的裝置密集度，造成更高相互連接的密度，使得微電子工 業已廣泛的發展m持續的相互連結的進步以及策略 已發展至封裝產業，以符合這些高相互連結密度的需求。 幾乎所有皆針對一個目標-減小尺寸。除了少數的例外，減 少尺寸亦代表降低成本。因此於該封裝之技藝中，雙線封 裝件（duaNiiMine packages)a大量的為表面固定封裝件所 取代，且新的發展，珠如晶片對晶片（chip_〇n_chip ; c〇c) 以及多晶片模組（multichip m〇dules ; MCM)係可符合高密 度相互連結的需要。這些或類似的發展係針對減少該封裝 的面積即該封裝χ-y方向上的尺寸。封裝厚度的關鍵已 界定在將切割為晶片之晶圓減薄之技術。於一完全加工之 晶圓上，孩減薄操作的完成係藉由將該晶圓加工側面向下 ，定於一暫時的載具上，諸如一膠帶，以及研磨該晶圓之 身面。現已有多種的研磨技術被提出及使用，範圍從簡單 的機械研磨，例如使用一研磨劑的研磨輪，到化學蝕刻以 及拋光技術，或前述技術的結合，例如，化學機械拋光 (CMP)。於一典型之晶圓減薄製程中，完整1C之200 111111直 徑的晶圓可由26至30密耳（mils)的最初厚度，於其再固定與 -4- 521356 A7 ____ B7 五、發明説明（2 ) 切割為晶粒之前，可減低之至僅有12 mils的最終厚度。該 個別的晶片，或晶粒，然後封裝，其將包括總成而形成MC Μ或COC的晶塊。用於本文中之該項目晶塊係指至少兩構件 之一次總成、一基質以及至少一主動晶片覆晶的連結於該 基質上。該晶塊之基質可為會非為一主動晶片，於一教的 配置中’該晶塊包括兩個或多個的組件、一基質、以及一 或多個的晶片，可為單獨的、並排的、或晶片堆叠的為該 基質所承載。又，該基質可為主動或被動的。該晶片堆疊 可包括兩堆疊的晶片，或兩個或多個的晶片堆疊在一個， 通常是較大的’晶片上。該項目基質於此上下文中係指一 支撐元件，可為主動或者是被動的，且該項目晶片通常係 指一完整加工的，亦即完成的，半導體晶片導體Ic裝置。 於較佳之情況下，於該晶塊中所有之該元件係為半導體晶 片導體，通常係為矽。該基質亦可為陶瓷。 於$亥組裝操作中’该單一之晶粒係透過一晶粒固定以及 連接工具所處置，且當需要時可進行額外的連結。為能承 受此種額外的加工而不致折斷，1 〇 m i 1 s或更大的厚度大致 上係足夠的。然而，少於8 mils的晶粒厚度，於許多的應 用中反而係較理想的，但於減薄之後由於會暴露於處置下 而被限制。 該晶粒厚度上的限制亦應用至一支撐晶圓或基質上。此 限制，10 mils或更高，於該產業中如同一標準般通常會被 接受’而便無法達成小於20 mils的晶塊。如此的限制便於 許多重要的應用中排除堆疊晶片的使用，諸如所謂的智慧 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂
線 521356 五、發明説明（ 卡’亦即嵌入晶片之信用卡。 用以減少I c封裝晶塊之高度的技術，在該晶片封裝的技 嚷rf域中’係為一相當大的進步。 泰Θ概述 人已發展出一種製造過程，用以製造ic封裝晶塊^且 性的減少厚度。於此製程中該關键的元件係將該減薄 步驟’應用至已經將覆晶連結至該基質晶圓上之一完成之 1C晶片。因為對未固定之晶片沒有額外的處置係必須的， 居曰g片可減薄而相當的低於1 〇 m i 1 s，例如2 - 8 m i 1 s ^該被 固足之曰日片之厚度的減低，在某些情況下可以減少該封裝 之整體高度一半導體晶片，因此可於一特定之封裝區域以 及高度中產生兩倍的裝置功能性。 附圖之概略說明 圖1為一典型之1C封裝晶塊之示意圖； 圖2為一晶圓佈局之视圖，顯示固定三個元件晶塊，用於 根據本發明之該晶片減薄操作； ζ 圖3係圖2中之該晶圓之部分的等高視圖； 圖4係於該晶片減薄步驟之後，圖3中該晶圓之 高視圖；以及 3刀的♦ 的兩個實施 例 元件符號說明 11 矽基質 12 裝置 圖5及6顯示根據本發明所加工之⑴封裝晶塊 本紙張尺度適財關家料 •6- 521356 A7
521356 A7 B7 五、發明説明（5 ) 18以及銲錫突出接點19，加裝於該基質u上。 由-晶圓製造者所製得之—半導體晶圓之—般的厚度係 25-35 mils。於封裝技術之狀態中，該晶圓可減薄至12_ 20 mils ’以減少該封裝之尺寸。於減薄之後該晶圓會被 切割為個別的晶粒，且該晶粒係連結於一基質上，用於最 終之總成。因此，參考圖丨，具有基質U及晶片15之一典型 的晶塊將具兩倍12-20 mils之一結合的z維度（高度），外加 通常為2-5 mils的分離。故於此所述之技術中，該整體晶塊 的南度將在範圍26-45 mils中。 與圖1中所示之該裝置相似之裝置，其製造係藉由突出， 將個別的晶片連結至矽基質晶圓。一典型之晶圓係顯示於 圖2。該矽晶圓21具有大數量的晶片連結位址22，每個位址 於切割為晶粒之後，將形成一基質，諸如圖1中之丨丨❶碎晶 片2 3係覆晶的連結至該基質晶圓之該晶片連結位址上。圖2 顯示兩個晶片加裝至每一位址上。該數量可以更大，或者 ，如圖1所示，每一位址可以使用一單一的晶片。在某些情 況中，某些該位址可係不完全的，且因此保留空缺。如前 所述，該基質晶圓可唯一裸露之矽晶圓，或包含圖1所示之 被動或主動之裝置。 · 圖2中該晶圓之部分的等高視圖係顯示於圖3中。所示之 晶圓21之切裁部分，具有兩晶片連結位址22。標示為23之 該晶片，利用銲錫突出3 1突出連結至該基質。該晶粒切割 鋸道係顯示為32。該晶片23可具有原始晶片的厚度。或者 ，該晶片可以在晶片級減薄，亦即減薄該整個加工的晶圓
本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 乂將居印片厚度減少至l2_2〇 mUs。於加工之此一階段， 邊基貝晶圓可已減薄至一相當的厚度。於該晶片固定且銲 锡再流動操作之後，但於切割該晶圓之前，該晶圓之前側 ，於其上暴露出該晶片之背側，係被減薄的。此一步驟為 圖4所代表’其中所示之該晶片的高度係相當程度的被域低 的。利用本發明之方法，該晶片可以減薄至10 mils以下， 亦P 2 8 miis。如此可減少整體封裝的高度，於前述之例子 中，減少4-18 mils ,或與先前技術之最佳的薄形封裝相比 達到10-40%的減低率。 於該減薄操作之前使用一保護填料係較合意的，且在某 二清況係較佳的。此係起因於一適當的填料能夠提供保護 T抵抗磨損及切割碎片，以及亦能夠於機械減薄以及切割 操作過程中增加該組件之實體強度的雙重功能。於1996年5 月14日頒予Degani等人之美國專利第5,5 16,728號中，已說 明且申請專利範圍保護適當填料的材料，該專利為此内容 編入本又中以為參考。一般而言，該填料材料基本上係不 溶於水的材料，其可為極性之有機溶劑，諸如甲醇、乙醇 、或丙醇等溶劑去除。較佳的填料材料係為松脂、或含有 松脂。松脂材料通常含有一種或多種的樹脂酸或衍生化樹 脂酸，諸如苯甲酸酐、2-十六烷酸、以及2,2，•聯石炭酸。該 松脂材料可應用為一包覆層，覆蓋該晶圓，且於一溫度， 例如大於120。。的溫度下，融化而充填該空缺的空間。 圖5及6代表概略的視圖，代表另一晶塊的配置，其可用 以促進本發明。圖5所代表之該實施例中，一單一水^之晶 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公爱) 521356 A7 ________B7 五、發明説明（7 ) 片係覆晶的連結至該晶圓。該晶圓51可為被動的，亦即裸 露的裝置，或包含主動的半導體裝置，及/或諸如電阻器、 電容器等等的裝置。該基質5丨可為裸露的陶瓷，或可為具 有電阻器、電容器等之陶瓷。由晶片52所代表之該單一= 平之晶片係利用銲錫突出53，直接覆晶的固定於基質51上。 請參考圖6 ,顯示一晶塊，其係根據本發明減薄兩次，藉 此在整體的晶塊厚度上造成一種戲劇化的降低。基質6 ^支 撐1C晶片62，係藉由前述之技術減薄。於該晶片減薄之後 ，m總成再固定於該載具帶上，而該晶圓之晶片側面位於 該戴上，且該基質61之背側係被減薄的。一額外的步驟部 分的切割該基質晶圓，藉由刻線或鋸該基質晶圓之主動側 ，以形成一深度大約等於最終晶圓的厚度，將係較佳的。 於此方式下，該晶塊可於該同一操作中減薄與切割。因此 藉由使用兩重複的圖2及3所代表的加工過程，便可製造此 種極薄的晶塊。使用本發明之加工過程，所製造之此種封 裝其高度相當低於20 mils，甚至低於1〇 mils。如果該組件 減薄至2 rmls ,相互間分離2 mils，該整體晶塊的厚度係為 6 mils。此種低剖面之晶塊係適用於編入信用卡之^ ,或 其他要求細長剖面的應用中。 本發明之該減薄步驟可藉由任冑已知的多種技術加以完 成，諸如機械研磨或雷射鎔蝕。用於矽晶圓減薄之裝置已 廣泛的使用，且可於商業上購得。舉例而言，用以固定晶 圓之一適當的切片器/層化器可為Nitt0 Denso出品之nel= 統。Okamoto出品型號〇Νχ·2〇〇 Grind x之研磨器可用= 本紙張尺度適用中國國豕標準(CNS) A4規格(210X297公爱) 521356 五、發明説明（8 進行本文所述之減薄操作 請瞭解本發明之|點在於該主動晶片之該晶圓可完全的 加工而不需要任何的減薄。如此於處置期間將該晶圓保持 在強固的狀悲，且減低斷裂的可能性。再纟，可使用兩個 減薄步驟，-個在晶圓級於晶片固定之前，以及該固实晶 片上之一最終減薄。於該第一減薄步騾中，該晶圓可由2弘 35 mils的製造厚度舉例而言減低25_67%。如此將使該晶圓 以及由晶圓上切割足該晶片，能夠具有適合於處置的厚度 。孩晶圓係切割為晶片，且該晶片係覆晶的固定在該晶圓 基質上。然後完成該第二減薄步驟，其中該晶片之厚度將 進一步減低至少25%。 顯示於圖中該銲錫突出之配置具有陣列的連結位置環繞 該晶片之周邊或邊緣。其他的配置同樣的亦適用於本發明 。舉例而言，茲技藝之晶片的狀態通常係利用面積陣列相 互連結，琢面積陣列定義為由該邊緣去除該晶片的面積上 ，具有相互連結之位址，亦即任何邊緣之相互連結位址之 至少一個特定的長度區間内。本發明可應用至任何結構之 可覆晶連結的晶片上。 於本發明之該總成中之該晶片係完全加工的晶片.，其係 覆晶固定，如此於加工之最後階段會現出該晶片之背側， 以便用於該基本的減薄操作。覆晶固定的本質係完全加工 的半導體的附件。 1C基質”上下顛倒的”位於該相互連結的基質上，亦即一 矽晶圓或陶瓷基質上^該加裝之裝置通常係為銲錫，形成 -11- 本紙張尺度適肖中S國家標準(CNS) A4規格(210X297公爱)~ '"""" ---—__
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球、襯塾、或突出之類的型式（於本文中通稱為突幻。鮮锡 突出可應用至該半導體晶片i，或該相互連結之基質上， 或至兩者上。於該連結操作時，該晶片係放置與該基質相 接觸’且孩銲錫會被加熱以將該銲錫再流動，以及將該晶 片加裝至4基免上。為能夠成功的連結，該銲錫所連镇之 位置，必須對該銲錫係可濕潤的。 通系用於積體電路以及覆晶基質上之該金屬相互連結的 圖樣係為鋁。同時用於直接焊接至鋁的技術已經試用，且 廣為人知並可接受的是鋁對於銲錫並非一種合宜的材料。 所以於業界實際係將一可銲錫的金屬塗覆於該鋁的接觸墊 上，而再將該銲錫突出或襯墊應用於該塗層上。該金屬塗 層通常稱為下突出的金屬化（Under Bump MetalHzation; UBM) ο 用於UBM技術中之該種金屬或多種金屬必須相當良好的 黏著至鋁，為可一般的錫製銲錫成品濕潤，且具高度導電 性。符合此種需求之一金屬化係為鉻及銅的混合物。先將 鉻沈積，以黏著至該鋁上，再將銅塗覆於該鉻上用以提供 一錦錫可濕潤之表面。已知鉻可以良好的黏著至不同種類 的材料、有機物以及無機物。然而，銲錫合金會溶解銅， 且會對路係去濕的。因此’直接在絡上之一薄層的銅將溶 入該熔融的銲錫中，然後該銲錫會自該鉻層上去濕。為確 保該銲錫及該UBM間介面的整體性，鉻及銅的混合物或共 沈積層通常係用於該鉻與銅層之間。 如同本文中之用途，該項目連結位址係意指1C晶片係以 -12- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) A7
球或大出連結至該基質之處的位址。該連結位址一般具有 下欠出的金屬化丨丨_些位址準備於該基質晶圓以及固定於 該基質晶圓上之辞魯> 上。 本又所述义琢I_p晶塊，典型的係組裝於一印刷線路 板上，通常具有β，其他的晶塊以及其的組件。該項且印 刷線路板係指標準的環氧樹脂板，例如FR4、球柵陣列相互 連結之基質、以及任何其他相互連結之基質。該晶塊可為 銲錫哭出或球連結、或者導線連結至該板上，或者替換連 結至一中間的矽相互連結基質上。 用於根據本發明之該基質之該晶片的材料以及最佳材料 係為半導體。更佳典型的其係為矽。使用矽基質以支撐矽 晶片的-㈣點在於該基質肖晶片纟熱機械力#性的配合 。另-個優點在於，用以於該基質上，形成流道之細微圖 樣之該金屬化的技術係廣為人知的，且本身係用於製造該 1C晶片。然而，本發明亦可應用至其他的半導體材料，著 名的m ·ν半導體材料諸如用於光波裝置中之GaAs以及In卜 精於本技藝者將可對本發明進行許多另外的修正。根據 本說明書所指出的精義中，所有的變動，其基本上基於該 原理及其等似物，且藉以使本技藝得以進步者，將理所當 然的视為落入說明書及申請專利範圍所界定之本發明之範 圍之中。 -13 · 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) -------

Claims (1)

  1. 521356 A8 B8 C8 D8 六、申請專利範圍 a. 減薄一完全加工之半導體晶圓， b. 將該完全加工之半導體晶圓切割為晶粒，以製造多 個半導體晶片， c·於一半導體晶圓基質上提供多個的晶片連結位址， d ·將該等半導體晶片覆晶連結至該等晶片連結位址上 rve丨將該等半導體晶片減薄，以及 將該半導體晶圓切割為晶粒，以製造多個晶塊。 Eg (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 15- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）
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Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999032304A1 (en) * 1997-12-22 1999-07-01 Hitachi, Ltd. Semiconductor device
JP2000091273A (ja) * 1998-09-11 2000-03-31 Sony Corp 半導体パッケージの製造方法およびその構造
EP1264520A4 (en) * 2000-03-10 2007-02-28 Chippac Inc PACKAGING STRUCTURE AND METHOD
US6639321B1 (en) * 2000-10-06 2003-10-28 Lsi Logic Corporation Balanced coefficient of thermal expansion for flip chip ball grid array
US6672947B2 (en) * 2001-03-13 2004-01-06 Nptest, Llc Method for global die thinning and polishing of flip-chip packaged integrated circuits
JP3788268B2 (ja) 2001-05-14 2006-06-21 ソニー株式会社 半導体装置の製造方法
FR2829291B1 (fr) * 2001-08-31 2005-02-04 Atmel Grenoble Sa Procede de fabrication de capteur d'image couleur avec ouvertures de contact creusees avant amincissement
FR2829292B1 (fr) * 2001-08-31 2004-09-10 Atmel Grenoble Sa Procede de fabrication de capteur d'image couleur avec substrat de support soude plot sur plot
DE10147877B4 (de) * 2001-09-28 2011-08-11 Epcos Ag, 81669 Verfahren zur Herstellung eines Bauelementträgers geringer Bauhöhe
US6867501B2 (en) 2001-11-01 2005-03-15 Rohm Co., Ltd. Semiconductor device and method for manufacturing same
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
US7018268B2 (en) * 2002-04-09 2006-03-28 Strasbaugh Protection of work piece during surface processing
US6713366B2 (en) 2002-06-12 2004-03-30 Intel Corporation Method of thinning a wafer utilizing a laminated reinforcing layer over the device side
JP3910493B2 (ja) 2002-06-14 2007-04-25 新光電気工業株式会社 半導体装置及びその製造方法
KR100442699B1 (ko) * 2002-07-19 2004-08-02 삼성전자주식회사 인접 수동소자 칩이 전기적으로 연결된 웨이퍼, 수동소자및 이를 이용한 반도체 패키지
US7250330B2 (en) * 2002-10-29 2007-07-31 International Business Machines Corporation Method of making an electronic package
JP4056854B2 (ja) 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
US7190082B2 (en) * 2003-03-24 2007-03-13 Lsi Logic Corporation Low stress flip-chip package for low-K silicon technology
US7244663B2 (en) * 2004-08-31 2007-07-17 Micron Technology, Inc. Wafer reinforcement structure and methods of fabrication
US20060141666A1 (en) * 2004-12-29 2006-06-29 Infineon Technologies Ag Method for producing a module including an integrated circuit on a substrate and an integrated module manufactured thereby
DE102005022017B3 (de) 2005-05-12 2006-10-26 Infineon Technologies Ag Verfahren zur Herstellung von Chip-Stapeln sowie zugehörige Chip-Stapel
KR100817078B1 (ko) * 2006-12-05 2008-03-26 삼성전자주식회사 시스템-인 패키지 및 시스템-인 패키지의 제작 방법
US7932180B2 (en) 2008-07-07 2011-04-26 Infineon Technologies Ag Manufacturing a semiconductor device via etching a semiconductor chip to a first layer
KR101601793B1 (ko) * 2009-10-08 2016-03-09 삼성전자주식회사 멀티칩 모듈들을 위한 개선된 전기적 연결들
US8114707B2 (en) * 2010-03-25 2012-02-14 International Business Machines Corporation Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip
KR100987116B1 (ko) * 2010-04-15 2010-10-11 (주)유일엔지니어링종합건축사사무소 입체적 외벽 및 그 시공방법
US9768128B2 (en) * 2014-01-29 2017-09-19 Infineon Technologies Ag Chip and method for detecting an attack on a chip
CN112582285B (zh) * 2020-12-15 2023-07-25 青岛歌尔微电子研究院有限公司 封装结构的减薄方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0231437A (ja) * 1988-07-21 1990-02-01 Oki Electric Ind Co Ltd 半導体チップの実装方法
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5516728A (en) * 1994-03-31 1996-05-14 At&T Corp. Process for fabircating an integrated circuit
US5952247A (en) * 1994-11-23 1999-09-14 Intel Corporation Method of accessing the circuitry on a semiconductor substrate from the bottom of the semiconductor substrate
KR100443484B1 (ko) * 1996-02-19 2004-09-18 마츠시타 덴끼 산교 가부시키가이샤 반도체장치및그제조방법
US5698474A (en) * 1996-02-26 1997-12-16 Hypervision, Inc. High speed diamond-based machining of silicon semiconductor die in wafer and packaged form for backside emission microscope detection
DE19707887C2 (de) * 1997-02-27 2002-07-11 Micronas Semiconductor Holding Verfahren zum Herstellen und Trennen von elektronischen Elementen mit leitfähigen Kontaktanschlüssen
JPH10335383A (ja) * 1997-05-28 1998-12-18 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH1167979A (ja) * 1997-08-13 1999-03-09 Citizen Watch Co Ltd フリップチップ半導体パッケージの実装構造及びその製造方法
US5963781A (en) * 1997-09-30 1999-10-05 Intel Corporation Technique for determining semiconductor substrate thickness
US6069366A (en) * 1998-03-30 2000-05-30 Advanced Micro Devices, Inc. Endpoint detection for thinning of silicon of a flip chip bonded integrated circuit

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